(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:1)(cid:3)(cid:7)(cid:8) (cid:13)(cid:14)(cid:15)(cid:5)(cid:6)(cid:11)(cid:16)(cid:17)(cid:15)(cid:18)(cid:19)(cid:20)(cid:11)(cid:15)(cid:21)(cid:5)(cid:2)(cid:1)(cid:19)(cid:5)(cid:21)(cid:20)(cid:2)(cid:15)(cid:11)(cid:6)(cid:5)(cid:15)(cid:14)(cid:22)(cid:20)(cid:1) (cid:23)(cid:24)(cid:15)(cid:22)(cid:11)(cid:25)(cid:17)(cid:1)(cid:15)(cid:5)(cid:15)(cid:20)(cid:11)(cid:13)(cid:26)(cid:15)(cid:19)(cid:26)(cid:15)(cid:1) SDAS277 − JANUARY 1995 • 3-State Buffer-Type Outputs Drive Bus SN54ALS580B...J OR W PACKAGE Lines Directly SN74ALS580B, SN74AS580...DW OR N PACKAGE • (TOP VIEW) Bus-Structured Pinout • Inverting-Logic Outputs OE 1 20 VCC • Package Options Include Plastic 1D 2 19 1Q Small-Outline (DW) Packages, Ceramic 2D 3 18 2Q Chip Carriers (FK), Standard Plastic (N) and 3D 4 17 3Q Ceramic (J) 300-mil DIPs, and Ceramic Flat 4D 5 16 4Q (W) Packages 5D 6 15 5Q 6D 7 14 6Q description 7D 8 13 7Q 8D 9 12 8Q These octal D-type transparent latches feature GND 10 11 LE 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for SN54ALS580B...FK PACKAGE (TOP VIEW) implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. C DD E CQ 21 OV 1 While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, 3 2 1 20 19 3D 4 18 2Q the outputs are latched to retain the data that was 4D 5 17 3Q set up. 5D 6 16 4Q A buffered output-enable (OE) input can be used 6D 7 15 5Q to place the eight outputs in either a normal logic 7D 8 14 6Q state (high or low) or a high-impedance state. In 9 10 1112 13 the high-impedance state, the outputs neither load D D EQ Q nor drive the bus lines significantly. The 8 N L8 7 G high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS580B is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ALS580B and SN74AS580 are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each latch) INPUTS OOUUTTPPUUTT OE LE D Q L H H L L H L H L L X Q0 H X X Z (cid:19)(cid:21)(cid:13)(cid:16)(cid:26)(cid:14)(cid:15)(cid:24)(cid:13)(cid:2) (cid:16)(cid:5)(cid:15)(cid:5) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’, Copyright  1995, Texas Instruments Incorporated (cid:19)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #-’ #’(cid:31)!$ (cid:30)(cid:29) (cid:15)’."$ (cid:24)(cid:28)$#(cid:31)&!’(cid:28)#$ $#"(cid:28)+"(cid:31)+ /"(cid:31)(cid:31)"(cid:28)#0, (cid:19)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:1)(cid:3)(cid:7)(cid:8) (cid:13)(cid:14)(cid:15)(cid:5)(cid:6)(cid:11)(cid:16)(cid:17)(cid:15)(cid:18)(cid:19)(cid:20)(cid:11)(cid:15)(cid:21)(cid:5)(cid:2)(cid:1)(cid:19)(cid:5)(cid:21)(cid:20)(cid:2)(cid:15)(cid:11)(cid:6)(cid:5)(cid:15)(cid:14)(cid:22)(cid:20)(cid:1) (cid:23)(cid:24)(cid:15)(cid:22)(cid:11)(cid:25)(cid:17)(cid:1)(cid:15)(cid:5)(cid:15)(cid:20)(cid:11)(cid:13)(cid:26)(cid:15)(cid:19)(cid:26)(cid:15)(cid:1) SDAS277 − JANUARY 1995 logic symbol† logic diagram (positive logic) 1 1 OE EN OE 11 LE C1 11 LE 2 19 1D 1D 1Q 3 18 2D 2Q C1 19 4 17 2 1Q 3D 3Q 1D 1D 5 16 4D 4Q 6 15 5D 5Q 7 14 6D 6Q 8 13 7D 7Q 9 12 To Seven Other Channels 8D 8Q †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, T : SN54ALS580B . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C A SN74ALS580B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS580B SN74ALS580B UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −1 −2.6 mA IOL Low-level output current 12 24 mA tw Pulse duration, LE high 15 15 ns tsu Setup time, data before LE↓ 20 10 ns th Hold time, data after LE↓ 12 10 ns TA Operating free-air temperature −55 125 0 70 °C 2 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:1)(cid:3)(cid:7)(cid:8) (cid:13)(cid:14)(cid:15)(cid:5)(cid:6)(cid:11)(cid:16)(cid:17)(cid:15)(cid:18)(cid:19)(cid:20)(cid:11)(cid:15)(cid:21)(cid:5)(cid:2)(cid:1)(cid:19)(cid:5)(cid:21)(cid:20)(cid:2)(cid:15)(cid:11)(cid:6)(cid:5)(cid:15)(cid:14)(cid:22)(cid:20)(cid:1) (cid:23)(cid:24)(cid:15)(cid:22)(cid:11)(cid:25)(cid:17)(cid:1)(cid:15)(cid:5)(cid:15)(cid:20)(cid:11)(cid:13)(cid:26)(cid:15)(cid:19)(cid:26)(cid:15)(cid:1) SDAS277 − JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ALS580B SN74ALS580B PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V VCC = 4.5 V to 5.5 V, IOH = −0.4 mA VCC −2 VCC −2 VVOOHH IOH = −1 mA 2.4 3.3 VV VVCCCC == 44..55 VV IOH = −2.6 mA 2.4 3.2 IOL = 12 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44..55 VV VV IOL = 24 mA 0.35 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 20 20 µA IOZL VCC = 5.5 V, VO = 0.4 V −20 −20 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL VCC = 5.5 V, VI = 0.4 V −0.13 −0.1 mA IO‡ VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA Outputs high 10 17 10 17 IICCCC VVCCCC == 55..55 VV Outputs low 16 26 16 26 mmAA Outputs disabled 17 29 17 29 †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, FROM TO R2 = 500 Ω, PARAMETER UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX§ SN54ALS580B SN74ALS580B MIN MAX MIN MAX tPLH 3 26 3 18 DD QQ nnss tPHL 3 15 3 14 tPLH 8 29 6 22 LLEE QQ nnss tPHL 4 22 6 21 tPZH 4 25 3 18 OOEE QQ nnss tPZL 4 21 4 18 tPHZ 2 12 1 10 OOEE QQ nnss tPLZ 3 22 1 15 §For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 3 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:1)(cid:3)(cid:7)(cid:8) (cid:13)(cid:14)(cid:15)(cid:5)(cid:6)(cid:11)(cid:16)(cid:17)(cid:15)(cid:18)(cid:19)(cid:20)(cid:11)(cid:15)(cid:21)(cid:5)(cid:2)(cid:1)(cid:19)(cid:5)(cid:21)(cid:20)(cid:2)(cid:15)(cid:11)(cid:6)(cid:5)(cid:15)(cid:14)(cid:22)(cid:20)(cid:1) (cid:23)(cid:24)(cid:15)(cid:22)(cid:11)(cid:25)(cid:17)(cid:1)(cid:15)(cid:5)(cid:15)(cid:20)(cid:11)(cid:13)(cid:26)(cid:15)(cid:19)(cid:26)(cid:15)(cid:1) SDAS277 − JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, T : SN74AS580 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74AS580 UUNNIITT MIN NOM MAX VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current −15 mA IOL Low-level output current 48 mA tw* Pulse duration, LE high 2 ns tsu* Setup time, data before LE↓ 2 ns th* Hold time, data after LE↓ 3 ns TA Operating free-air temperature 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74AS580 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP‡ MAX VIK VCC = 4.5 V, II = −18 mA −1.2 V VCC = 4.5 V to 5.5 V, IOH = −2 mA VCC −2 VVOOHH VV VCC = 4.5 V, IOH = −15 mA 2.4 3.3 VOL VCC = 4.5 V, IOL = 48 mA 0.33 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V 50 µA IOZL VCC = 5.5 V, VO = 0.4 V −50 µA II VCC = 5.5 V, VI = 7 V 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 µA IIL VCC = 5.5 V, VI = 0.4 V −0.5 mA IO§ VCC = 5.5 V, VO = 2.25 V −30 −112 mA Outputs high 62 100 IICCCC VVCCCC == 55..55 VV Outputs low 65 106 mmAA Outputs disabled 71 115 ‡All typical values are at VCC = 5 V, TA = 25°C. §The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 4 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:1)(cid:3)(cid:7)(cid:8) (cid:13)(cid:14)(cid:15)(cid:5)(cid:6)(cid:11)(cid:16)(cid:17)(cid:15)(cid:18)(cid:19)(cid:20)(cid:11)(cid:15)(cid:21)(cid:5)(cid:2)(cid:1)(cid:19)(cid:5)(cid:21)(cid:20)(cid:2)(cid:15)(cid:11)(cid:6)(cid:5)(cid:15)(cid:14)(cid:22)(cid:20)(cid:1) (cid:23)(cid:24)(cid:15)(cid:22)(cid:11)(cid:25)(cid:17)(cid:1)(cid:15)(cid:5)(cid:15)(cid:20)(cid:11)(cid:13)(cid:26)(cid:15)(cid:19)(cid:26)(cid:15)(cid:1) SDAS277 − JANUARY 1995 switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, FROM TO R2 = 500 Ω, PARAMETER UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX† SN74AS580 MIN MAX tPLH 3 7.5 DD QQ nnss tPHL 3 7 tPLH 5 9 LLEE QQ nnss tPHL 4 8 tPZH 2 6.5 OOEE QQ nnss tPZL 4 9.5 tPHZ 2 6.5 OOEE QQ nnss tPLZ 2 7 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 5 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:1)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:1)(cid:3)(cid:7)(cid:8) (cid:13)(cid:14)(cid:15)(cid:5)(cid:6)(cid:11)(cid:16)(cid:17)(cid:15)(cid:18)(cid:19)(cid:20)(cid:11)(cid:15)(cid:21)(cid:5)(cid:2)(cid:1)(cid:19)(cid:5)(cid:21)(cid:20)(cid:2)(cid:15)(cid:11)(cid:6)(cid:5)(cid:15)(cid:14)(cid:22)(cid:20)(cid:1) (cid:23)(cid:24)(cid:15)(cid:22)(cid:11)(cid:25)(cid:17)(cid:1)(cid:15)(cid:5)(cid:15)(cid:20)(cid:11)(cid:13)(cid:26)(cid:15)(cid:19)(cid:26)(cid:15)(cid:1) SDAS277 − JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC RL = R1 = R2 S1 RL R1 From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point (see Note CAL) RL CL (see Note CAL) R2 (see Note A) LOAD CIRCUIT FOR BI-STATE LOAD CIRCUIT LOAD CIRCUIT TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3.5 V 3.5 V Timing High-Level Input 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V tsu th tw 3.5 V 3.5 V Data Low-Level Input 1.3 V 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3.5 V Output Control 1.3 V 1.3 V (low-level enabling) 0.3 V 3.5 V tPZL Input 1.3 V 1.3 V tPLZ 0.3 V (cid:1)3.5 V Waveform 1 tPLH tPHL S1 Closed 1.3 V In-Phase VOH (see Note B) VOL Output 1.3 V 1.3 V tPHZ 0.3 V VOL tPZH tPLH VOH tPHL Waveform 2 Out-of-Phase VOH S1 Open 1.3 V 0.3 V Output 1.3 V 1.3 V (see Note B) (cid:1)0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 84012022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84012022A SNJ54ALS 580BFK 8401202RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8401202RA SNJ54ALS580BJ 8401202SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8401202SA SNJ54ALS580BW SN54ALS580BJ ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54ALS580BJ SN74ALS580BN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74ALS580BN (RoHS) SNJ54ALS580BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84012022A SNJ54ALS 580BFK SNJ54ALS580BJ ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8401202RA SNJ54ALS580BJ SNJ54ALS580BW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8401202SA SNJ54ALS580BW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS580B, SN74ALS580B : •Catalog: SN74ALS580B •Military: SN54ALS580B NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

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