SN54ALS38B, SN74ALS38B QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS SDAS196B – APRIL 1982 – REVISED DECEMBER 1994 • Package Options Include Plastic SN54ALS38B...J PACKAGE Small-Outline (D) Packages, Ceramic Chip SN74ALS38B...D OR N PACKAGE (TOP VIEW) Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1A 1 14 VCC description 1B 2 13 4B 1Y 3 12 4A These devices contain four independent 2-input 2A 4 11 4Y positive-NAND buffers with open-collector 2B 5 10 3B outputs. They perform the Boolean functions 2Y 6 9 3A Y = A • B or Y = A + B in positive logic. The GND 7 8 3Y open-collector outputs require pullup resistors to perform correctly. These outputs may be SN54ALS38B...FK PACKAGE connected to other open-collector outputs to (TOP VIEW) implement active-low wired-OR or active-high wired-AND functions. Open-collector devices C B A C CB often are used to generate higher V levels. 1 1 N V 4 OH The SN54ALS38B is characterized for operation 3 2 1 20 19 1Y 4 18 4A over the full military temperature range of –55°C NC 5 17 NC to 125°C. The SN74ALS38B is characterized for 2A 6 16 4Y operation from 0°C to 70°C. NC 7 15 NC 2B 8 14 3B FUNCTION TABLE 9 10 11 12 13 (each gate) Y DCY A INPUTS OUTPUT 2 NN3 3 G A B Y NC – No internal connection H H L L X H X L H logic symbol† logic diagram (positive logic) 1 1 1A & 3 1A 3 2 1Y 2 1Y 1B 1B 4 2A 6 4 5 2Y 2A 6 2B 5 2Y 2B 9 3A 8 9 10 3Y 3A 8 3B 10 3Y 12 3B 4A 11 12 13 4Y 4A 11 4B 13 4Y 4B †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. PRODUCTION DATA information is current as of publication date. Copyright  1994, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ALS38B, SN74ALS38B QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS SDAS196B – APRIL 1982 – REVISED DECEMBER 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Operating free-air temperature range, T : SN54ALS38B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C A SN74ALS38B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS38B SN74ALS38B UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V VOH High-level output voltage 5.5 5.5 V IOL Low-level output current 12 24 mA TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ALS38B SN74ALS38B PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V IOL = 12 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44.55 VV VV IOL = 24 mA 0.35 0.5 II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A IIL VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA IOH VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mA ICCH VCC = 5.5 V, VI = 0 0.86 1.6 0.86 1.6 mA ICCL VCC = 5.5 V, VI = 4.5 V 4.8 7.8 4.8 7.8 mA ‡All typical values are at VCC = 5 V, TA = 25°C. switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, FROM TO RL = 500 W , PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX§ UNIT SN54ALS38B SN74ALS38B MIN MAX MIN MAX tPLH 7 59 10 33 AA oorr BB YY nnss tPHL 2 20 1 12 §For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS38B, SN74ALS38B QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS SDAS196B – APRIL 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC RL = R1 = R2 S1 RL R1 From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point (see NoteC AL) RL CL (see NoteC AL) R2 (see Note A) LOAD CIRCUIT FOR BI-STATE LOAD CIRCUIT LOAD CIRCUIT TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3.5 V 3.5 V Timing High-Level Input 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V tsu th tw 3.5 V 3.5 V Data Low-Level Input 1.3 V 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3.5 V Output Control 1.3 V 1.3 V (low-level enabling) 0.3 V 3.5 V tPZL Input 1.3 V 1.3 V tPLZ (cid:1)3.5 V 0.3 V Waveform 1 tPLH tPHL S1 Closed 1.3 V In-Phase VOH (see Note B) VOL Output 1.3 V 1.3 V tPHZ 0.3 V VOL tPZH tPLH VOH tPHL Waveform 2 Out-of-Phase VOH S1 Open 1.3 V 0.3 V Output 1.3 V 1.3 V (see Note B) (cid:1)0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-86871012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 86871012A SNJ54 ALS38BFK 5962-8687101CA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8687101CA SNJ54ALS38BJ 5962-8687101DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8687101DA SNJ54ALS38BW SN74ALS38BD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS38B & no Sb/Br) SN74ALS38BDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS38B & no Sb/Br) SN74ALS38BDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS38B & no Sb/Br) SN74ALS38BN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74ALS38BN & no Sb/Br) SN74ALS38BNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS38B & no Sb/Br) SNJ54ALS38BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 86871012A SNJ54 ALS38BFK SNJ54ALS38BJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8687101CA SNJ54ALS38BJ SNJ54ALS38BW ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8687101DA SNJ54ALS38BW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS38B, SN74ALS38B : •Catalog: SN74ALS38B •Military: SN54ALS38B NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALS38BDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ALS38BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALS38BDR SOIC D 14 2500 367.0 367.0 38.0 SN74ALS38BNSR SO NS 14 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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