SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 (cid:0) D-Type Flip-Flops in a Single Package With SN54ALS374A, SN54AS374...J PACKAGE 3-State Bus Driving True Outputs SN74ALS374A, SN74AS374...DW OR N PACKAGE (cid:0) (TOP VIEW) Full Parallel Access for Loading (cid:0) Buffered Control Inputs OE 1 20 VCC (cid:0) Package Options Include Plastic 1Q 2 19 8Q Small-Outline (DW) Packages, Ceramic 1D 3 18 8D Chip Carriers (FK), and Standard Plastic (N) 2D 4 17 7D and Ceramic (J) DIPs 2Q 5 16 7Q 3Q 6 15 6Q description 3D 7 14 6D 4D 8 13 5D These octal D-type edge-triggered flip-flops 4Q 9 12 5Q feature 3-state outputs designed specifically for GND 10 11 CLK driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O SN54ALS374A, SN54AS374...FK PACKAGE ports, bidirectional bus drivers, and working (TOP VIEW) registers. C DQ E CQ 11 OV 8 On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at 3 2 1 20 19 2D 4 18 8D the data (D) inputs. 2Q 5 17 7D A buffered output-enable (OE) input places the 3Q 6 16 7Q eight outputs in either a normal logic state (high or 3D 7 15 6Q low logic levels) or the high-impedance state. In 4D 8 14 6D the high-impedance state, the outputs neither 9 10 1112 13 load nor drive the bus lines significantly. The Q D KQ D high-impedance state and the increased drive 4 N L5 5 G C provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 logic symbol† logic diagram (positive logic) 1 1 OE OE EN 11 11 CLK C1 CLK C1 2 3 2 3 1Q 1D 1D 1D 1D 1Q 4 5 2D 2Q 7 6 3D 3Q 8 9 4D 4Q To Seven Other Channels 13 12 5D 5Q 14 15 6D 6Q 17 16 7D 7Q 18 19 8D 8Q †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, q (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W JA N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions SN54ALS374A SN74ALS374A UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA TA Operating free-air temperature –55 125 0 70 °C 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ALS374A SN74ALS374A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 VOH IOH = –1 mA 2.4 3.3 V VVCCCC == 44.55 VV IOH = –2.6 mA 2.4 3.2 IOL = 12 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44.55 VV VV IOL = 24 mA 0.35 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 20 20 m A IOZL VCC = 5.5 V, VO = 0.4 V –20 –20 m A II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA IO‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA Outputs high 11 20 11 19 ICC VCC = 5.5 V Outputs low 19 28 19 28 mA Outputs disabled 20 31 20 31 †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) SN54ALS374A SN74ALS374A UUNNIITT MIN MAX MIN MAX fclock Clock frequency 30 35 MHz tw Pulse duration CLK high or low 16.5 14 ns tsu Setup time Data before CLK↑ 10 10 ns th Hold time Data after CLK↑ 4 0 ns switching characteristics over recommended operating conditions (unless otherwise noted (see Figure 3) FROM TO SN54ALS374A SN74ALS374A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 30 35 MHz tPLH 3 14 3 12 CCLLKK QQ nnss tPHL 5 17 5 16 tPZH 3 18 3 17 OOEE QQ nnss tPZL 5 21 5 18 tPHZ 1 11 1 10 OOEE QQ nnss tPLZ 2 19 2 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 recommended operating conditions SN54AS374 SN74AS374 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –12 –15 mA IOL Low-level output current 32 48 mA TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54AS374 SN74AS374 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2 VOH IOH = –12 mA 2.4 3.2 V VVCCCC == 44.55 VV IOH = –15 mA 2.4 3.3 IOL = 32 mA 0.29 0.5 VVOOLL VVCCCC == 44.55 VV VV IOL = 48 mA 0.34 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 50 50 m A IOZL VCC = 5.5 V, VO = 0.4 V –50 –50 m A II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A OE, CLK –0.5 –0.5 IIIILL VVCCCC == 55.55 VV, VVII == 00.44 VV mmAA Data –3 –2 IO‡ VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA Outputs high 77 120 77 120 ICC VCC = 5.5 V Outputs low 84 128 84 128 mA Outputs disabled 84 128 84 128 †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) SN54AS374 SN74AS374 UUNNIITT MIN MAX MIN MAX fclock Clock frequency 100* 125 MHz CLK high 5.5* 4 ttw PPuullssee dduurraattiioonn nnss CLK low 3* 3 tsu Setup time Data before CLK↑ 3* 2 ns th Hold time Data after CLK↑ 3* 2 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 3) FROM TO SN54AS374 SN74AS374 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 100* 125 MHz tPLH 3 11 3 8 CCLLKK QQ nnss tPHL 4 11.5 4 9 tPZH 2 7 2 6 OOEE QQ nnss tPZL 3 11 3 10 tPHZ 2 10 2 6 OOEE QQ nnss tPLZ 2 7 2 6 * On products compliant to MIL-PRF-38535, this parameter is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 APPLICATION INFORMATION Four SN54ALS374A, SN74ALS374A, or ’AS374 EN C 8 8 ’ALS139 A X/Y 0 EN 1 Output-Enable B 1 C Select 2 2 G 8 8 EN 3 A Input Clock B EN Select G C 8 8 Clock EN C 8 8 8 8 Input Output Figure 1. Expandable 4-Word by 8-Bit General File Register 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 APPLICATION INFORMATION SN54ALS374A, SN74ALS374A, or ’AS374 Output Enable 1 EN Clock 1 C1 1D Bidirectional Bidirectional Data Bus 1 Data Bus 2 SN54ALS374A, SN74ALS374A, or ’AS374 Output Enable 2 EN Clock 2 C1 1D Clock 1 H Bus-Exchange Clock Clock 2 H Clock Circuit for Bus Exchange Figure 2. Bidirectional Bus Driver POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC S1 500 W 500 W From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point CL = 50 pF 500 W CL = 50 pF (sCeeL N= o5t0e pAF) 500 W (see Note A) (see Note A) LOAD CIRCUIT FOR LOAD CIRCUIT FOR LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS OPEN-COLLECTOR OUTPUTS 3-STATE OUTPUTS Timing 3.5 V High-Level 3.5 V Input 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V tsu th tw 3.5 V 3.5 V Data Low-Level 1.3 V 1.3 V 1.3 V 1.3 V Input Pulse 0.3 V 0.3 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3.5 V Output 1.3 V 1.3 V Control 0.3 V 3.5 V 1.3 V 1.3 V tPZL tPLZ Input 0.3 V ≈3.5 V Waveform 1 tPLH tPHL S1 Closed 1.3 V VOH (see Note B) VOL + 0.3 V In-Phase 1.3 V 1.3 V VOL Output VOL tPZH tPHZ tPHL tPLH VOH Waveform 2 VOH – 0.3 V Out-of-Phase VOH S1 Open 1.3 V Output 1.3 V 1.3 V (see Note B) ≈0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9756201QRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9756201QR A SNJ54AS374J 83020022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83020022A SNJ54ALS 374AFK 8302002RA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8302002RA SNJ54ALS374AJ 8302002SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8302002SA SNJ54ALS374AW JM38510/37204B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type JM38510/ 37204B2A JM38510/37204BRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type JM38510/ 37204BRA M38510/37204B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37204B2A M38510/37204BRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 37204BRA SN54ALS374AJ ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type SN54ALS374AJ SN54AS374J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54AS374J SN74ALS374ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS374A & no Sb/Br) SN74ALS374ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS374A & no Sb/Br) SN74ALS374ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS374A & no Sb/Br) SN74ALS374AN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74ALS374AN (RoHS) SN74ALS374ANE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74ALS374AN (RoHS) SN74ALS374ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS374A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74AS374DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AS374 & no Sb/Br) SN74AS374N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74AS374N (RoHS) SNJ54ALS374AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83020022A SNJ54ALS 374AFK SNJ54ALS374AJ ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8302002RA SNJ54ALS374AJ SNJ54ALS374AW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8302002SA SNJ54ALS374AW SNJ54AS374J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9756201QR A SNJ54AS374J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 : •Catalog: SN74ALS374A, SN74AS374 •Military: SN54ALS374A, SN54AS374 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALS374ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74ALS374ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALS374ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS374ANSR SO NS 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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