SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER 1994 • Contain Eight Flip-Flops With Single-Rail SN54ALS273...J PACKAGE Outputs SN74ALS273...DW OR N PACKAGE • (TOP VIEW) Buffered Clock and Direct-Clear Inputs • Individual Data Input to Each Flip-Flop CLR 1 20 VCC • Applications Include: 1Q 2 19 8Q Buffer/Storage Registers 1D 3 18 8D Shift Registers 2D 4 17 7D Pattern Generators 2Q 5 16 7Q • Package Options Include Plastic 3Q 6 15 6Q Small-Outline (DW) Packages, Ceramic 3D 7 14 6D Chip Carriers (FK), and Standard Plastic (N) 4D 8 13 5D and Ceramic (J) 300-mil DIPs 4Q 9 12 5Q GND 10 11 CLK description These octal positive-edge-triggered flip-flops SN54ALS273...FK PACKAGE (TOP VIEW) utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear (CLR) input. R C D Q L CQ Information at the data (D) inputs meeting the 1 1 CV 8 setup-time requirements is transferred to the 3 2 1 20 19 Q outputs on the positive-going edge of the clock 2D 4 18 8D (CLK) pulse. Clock triggering occurs at a particular 2Q 5 17 7D voltage level and is not directly related to the 3Q 6 16 7Q transition time of the positive-going pulse. When 3D 7 15 6Q CLK is at either the high or low level, the D input 4D 8 14 6D 9 10 11 1213 signal has no effect at the output. Q D K Q D The SN54ALS273 is characterized for operation 4 N L 5 5 over the full military temperature range of –55°C G C to 125°C. The SN74ALS273 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT CLR CLK D Q L X X L H ↑ H H H ↑ L L H H or L X Q0 PRODUCTION DATA information is current as of publication date. Copyright  1994, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER 1994 logic symbol† 1 CLR R 11 CLK C1 3 2 1D 1D 1Q 4 5 2D 2Q 7 6 3D 3Q 8 9 4D 4Q 13 12 5D 5Q 14 15 6D 6Q 17 16 7D 7Q 18 19 8D 8Q †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1D 2D 3D 4D 5D 6D 7D 8D 3 4 7 8 13 14 17 18 11 CLK 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 R R R R R R R R 1 CLR 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Operating free-air temperature range, T : SN54ALS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C A SN74ALS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER 1994 recommended operating conditions SN54ALS273 SN74ALS273 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA fclock Clock frequency 0 30 0 35 MHz CLR low 10 10 tw Pulse duration CLK high 16.5 14 ns CLK low 16.5 14 Data 10 10 ttsu SSeettupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss CLR inactive state 15 15 th Hold time, data after CLK↑ 0 0 ns TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ALS273 SN74ALS273 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 VOH IOH = –1 mA 2.4 3.3 V VVCCCC == 44.55 VV IOH = –2.6 mA 2.4 3.2 IOL = 12 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44.55 VV VV IOL = 24 mA 0.35 0.5 II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA IO‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA ICCH VCC = 5.5 V 11 20 11 20 mA ICCL VCC = 5.5 V 19 29 19 29 mA †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER 1994 switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, FROM TO RL = 500 W , PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX† UNIT SN54ALS273 SN74ALS273 MIN MAX MIN MAX fmax 30 35 MHz tPHL CLR Any Q 4 24 4 18 ns tPLH 2 20 2 12 CCLLKK AAnnyy QQ nnss tPHL 3 17 3 15 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC RL = R1 = R2 S1 RL R1 From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point (see NoteC AL) RL CL (see NoteC AL) R2 (see Note A) LOAD CIRCUIT FOR BI-STATE LOAD CIRCUIT LOAD CIRCUIT TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3.5 V 3.5 V Timing High-Level Input 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V tsu th tw 3.5 V 3.5 V Data Low-Level Input 1.3 V 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3.5 V Output Control 1.3 V 1.3 V (low-level enabling) 0.3 V 3.5 V tPZL Input 1.3 V 1.3 V tPLZ (cid:1)3.5 V 0.3 V Waveform 1 tPLH tPHL S1 Closed 1.3 V In-Phase VOH (see Note B) VOL Output 1.3 V 1.3 V tPHZ 0.3 V VOL tPZH tPLH VOH tPHL Waveform 2 Out-of-Phase VOH S1 Open 1.3 V 0.3 V Output 1.3 V 1.3 V (see Note B) (cid:1)0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 84136012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84136012A SNJ54ALS 273FK 8413601RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8413601RA SNJ54ALS273J 8413601SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8413601SA SNJ54ALS273W SN54ALS273J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54ALS273J SN74ALS273DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS273 & no Sb/Br) SN74ALS273DWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS273 & no Sb/Br) SN74ALS273DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS273 & no Sb/Br) SN74ALS273N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74ALS273N (RoHS) SN74ALS273NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS273 & no Sb/Br) SNJ54ALS273FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84136012A SNJ54ALS 273FK SNJ54ALS273J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8413601RA SNJ54ALS273J SNJ54ALS273W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8413601SA SNJ54ALS273W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS273, SN74ALS273 : •Catalog: SN74ALS273 •Military: SN54ALS273 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALS273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74ALS273NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALS273DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS273NSR SO NS 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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