SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 (cid:0) Internal Look-Ahead Circuitry for Fast SN54ALS161B, SN54ALS162B, SN54ALS163B, Counting SN54AS161, SN54AS163...J PACKAGE (cid:0) SN74ALS161B, SN74AS161, Carry Output for n-Bit Cascading SN74AS163...D OR N PACKAGE (cid:0) Synchronous Counting SN74ALS163B...D, DB, OR N PACKAGE (cid:0) (TOP VIEW) Synchronously Programmable (cid:0) Package Options Include Plastic CLR 1 16 VCC Small-Outline (D) and Shrink Small-Outline CLK 2 15 RCO (DB) Packages, Ceramic Chip Carriers (FK), A 3 14 QA Standard Plastic (N) and Ceramic (J) DIPs B 4 13 QB description C 5 12 QC D 6 11 QD These synchronous, presettable, 4-bit decade ENP 7 10 ENT and binary counters feature an internal carry GND 8 9 LOAD look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit SN54ALS161B, SN54ALS162B, SN54ALS163B, decade counter. The ’ALS161B, ’ALS163B, SN54AS161, SN54AS163...FK PACKAGE ’AS161, and ’AS163 devices are 4-bit binary (TOP VIEW) counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that LKLR C CCCO CC N V R the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) 3 2 1 2019 inputs and internal gating. This mode of operation A 4 18 QA eliminates the output counting spikes normally B 5 17 QB associated with asynchronous (ripple-clock) NC 6 16 NC counters. A buffered clock (CLK) input triggers the C 7 15 QC four flip-flops on the rising (positive-going) edge of D 8 14 QD 9 10 11 12 13 the clock input waveform. P D C DT These counters are fully programmable; they can N N N AN E G OE be preset to any number between 0 and 9 or 15. L Because presetting is synchronous, setting up a NC – No internal connection low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 description (continued) produces a high-level pulse while the count is maximum (9 or 15, with Q high). The high-level overflow A ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C. logic symbols† ’ALS161B AND ’AS161 BINARY COUNTERS ’ALS163B AND ’AS163 BINARY COUNTERS WITH DIRECT CLEAR WITH SYNCHRONOUS CLEAR CTRDIV16 CTRDIV16 1 1 CLR CT=0 CLR 5CT=0 9 9 LOAD M1 LOAD M1 15 15 M2 M2 10 3CT=15 RCO 10 3CT=15 RCO ENT G3 ENT G3 7 7 ENP G4 ENP G4 2 2 CLK C5/2,3,4+ CLK C5/2,3,4+ 3 14 3 14 A 1, 5D [1] QA A 1, 5D [1] QA 4 13 4 13 B [2] QB B [2] QB 5 12 5 12 C [4] QC C [4] QC 6 11 6 11 D [8] QD D [8] QD SN54ALS162B DECADE COUNTER WITH SYNCHRONOUS CLEAR CTRDIV10 1 CLR 5CT=0 9 LOAD M1 15 M2 10 3CT=9 RCO ENT G3 7 ENP G4 2 CLK C5/2,3,4+ 3 14 A 1, 5D [1] QA 4 13 B [2] QB 5 12 C [4] QC 6 11 D [8] QD †These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 logic diagram (positive logic) 9 SN54ALS162B LOAD 10 ENT 15 RCO 7 ENP 1 CLR 2 CLK 14 C1 QA 1D 3 A 13 C1 QB 1D 4 B 12 C1 QC 1D 5 C 11 C1 QD 1D 6 D Pin numbers shown are for the J package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 logic diagram (positive logic) ’ALS163B and ’AS163 1 CLR 9 LOAD 10 ENT 15 7 RCO ENP 2 CLK 14 C1 QA 1D 3 A 13 C1 QB 1D 4 B 12 C1 QC 1D 5 C 11 C1 QD 1D 6 D Pin numbers shown are for the D, DB, J, and N packages. ’ALS161B and ’AS161 synchronous binary counters are similar; however, CLR is asynchronous. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 typical clear, preset, count, and inhibit sequences SN54ALS162B The following sequence is illustrated below: 1. Clear outputs to zero (SN54ALS162B is synchronous) 2. Preset to BCD 7 3. Count to 8, 9, 0, 1, 2, and 3 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Data Outputs QC QD RCO 7 8 9 0 1 2 3 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 typical clear, preset, count, and inhibit sequences ’ALS161B, ’AS161, ’ALS163B, and ’AS163 The following sequence is illustrated below: 1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are synchronous.) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Data Outputs QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear Async Clear 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Package thermal impedance, q (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions SN54ALS161B SN74ALS161B SN54ALS162B SN54ALS163B SN74ALS163B UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –0.4 –0.4 mA IOL Low-level output current 4 8 mA TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ALS161B SN74ALS161B SN54ALS162B PARAMETER TEST CONDITIONS SN54ALS163B SN74ALS163B UNIT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V IOL = 4 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44.55 VV VV IOL = 8 mA 0.35 0.5 II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA IO§ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA ICC VCC = 5.5 V 12 21 12 21 mA ‡All typical values are at VCC = 5 V, TA = 25°C. §The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) SN54ALS161B SN74ALS161B SN54ALS162B SN54ALS163B SN74ALS163B UNIT MIN MAX MIN MAX fclock Clock frequency 22 40 MHz CLR high or low 20 12.5 ttw PPuullssee dduurraattiioonn nnss ’ALS161B CLR low 20 15 A, B, C, D 50 15 LOAD 20 15 ’ALS161B 25 15 EENNPP, EENNTT tsu Setup time, before CLK↑↑↑↑ SN54ALS162B, ’ALS163B 20 15 ns ’ALS161B CLR inactive 10 10 CLR low 20 15 SSNN5544AALLSS116622BB, ’’AALLSS116633BB CLR high 20 10 th Hold time, all synchronous inputs after CLK↑ 0 0 ns switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1) FROM TO SN54ALS161B SN74ALS161B PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 22 40 MHz tPLH 5 34 5 20 CCLLKK RRCCOO nnss tPHL 5 27 5 20 tPLH 4 19 4 15 CCLLKK AAnnyy QQ nnss tPHL 6 25 6 20 tPLH 3 18 3 13 EENNTT RRCCOO nnss tPHL 3 17 3 13 Any Q 8 27 8 24 ttPPHHLL CCLLRR nnss RCO 11 32 11 23 switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1) SN54ALS162B FROM TO SN74ALS163B PARAMETER SN54ALS163B UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX fmax 22 40 MHz tPLH 5 25 5 20 CCLLKK RRCCOO nnss tPHL 5 25 5 20 tPLH 4 18 4 15 CCLLKK AAnnyy QQ nnss tPHL 6 25 6 20 tPLH 3 16 3 13 EENNTT RRCCOO nnss tPHL 3 16 3 13 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 recommended operating conditions SN54AS161 SN74AS161 SN54AS163 SN74AS163 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –2 –2 mA IOL Low-level output current 20 20 mA TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54AS161 SN74AS161 PARAMETER TEST CONDITIONS SN54AS163 SN74AS163 UNIT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VOH VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VCC –2 V VOL VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V LOAD 0.3 0.3 II ENT VCC = 5.5 V, VI = 7 V 0.2 0.2 mA All others 0.1 0.1 LOAD 60 60 IIH ENT VCC = 5.5 V, VI = 2.7 V 40 40 m A All others 20 20 LOAD –1.5 –1.5 IIL ENT VCC = 5.5 V, VI = 0.4 V –1 –1 mA All others –0.5 –0.5 IO‡ VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA ICC VCC = 5.5 V 35 53 35 53 mA †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 timing requirements over recommended operating conditions (see Figure 1) SN54AS161 SN74AS161 SN54AS163 SN74AS163 UNIT MIN MAX MIN MAX fclock Clock frequency 65 75 MHz CLR high or low 7.7 6.7 ttw PPuullssee dduurraattiioonn nnss ’AS161 CLR low 10 8 A, B, C, D 10 8 LOAD 10 8 ENP, ENT 10 8 ttsu SSeettuupp ttiimmee, bbeeffoorree CCLLKK↑↑↑↑ nnss ’AS161 CLR inactive 10 8 CLR low 14 12 ’’AASS116633 CLR high (inactive) 10 9 th Hold time, all synchronous inputs after CLK↑ 2 0 ns switching characteristics over recommended operating conditions (see Figure 1) FROM TO SN54AS161 SN74AS161 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 65* 75 MHz RCO (with LOAD high) 1 8.5 1 8 ttPPLLHH CCLLKK nnss RCO (with LOAD low) 3 17.5 3 16.5 tPHL CLK RCO 2 14 2 12.5 ns tPLH 1 7.5 1 7 CCLLKK AAnnyy QQ nnss tPHL 2 14 2 13 tPLH 1.5 10 1.5 9 EENNTT RRCCOO nnss tPHL 1 9.5 1 8.5 Any Q 2 14 2 13 ttPPHHLL CCLLRR nnss RCO 2 14 2 12.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating conditions (see Figure 1) FROM TO SN54AS163 SN74AS163 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 65* 75 MHz RCO (with LOAD high) 1 8.5 1 8 ttPPLLHH CCLLKK nnss RCO (with LOAD low) 3 17.5 3 16.5 tPHL CLK RCO 2 14 2 12.5 ns tPLH 1 7.5 1 7 CCLLKK AAnnyy QQ nnss tPHL 2 14 2 13 tPLH 1.5 10 1.5 9 EENNTT RRCCOO nnss tPHL 1 9.5 1 8.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC S1 500 W 500 W From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point CL = 50 pF 500 W CL = 50 pF CL = 50 pF 500 W (see Note A) (see Note A) (see Note A) LOAD CIRCUIT FOR LOAD CIRCUIT LOAD CIRCUIT BI-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V 3 V Timing High-Level Input 1.5 V Pulse 1.5 V 1.5 V 0 V 0 V tsu th tw 3 V 3 V Data Low-Level Input 1.5 V 1.5 V 1.5 V 1.5 V Pulse 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS Output 3 V Control 1.5 V 1.5 V (low-level enabling) 0 V 3 V tPZL tPLZ Input 1.5 V 1.5 V 0 V ≈3 V Waveform 1 tPLH tPHL S1 Closed 1.5 V (see Note B) In-Phase VOH VOL 1.5 V 1.5 V Output tPHZ 0.3 V VOL tPZH tPHL tPLH Waveform 2 VOH S1 Open 1.5 V Out-of-Phase VOH (see Note B) 0.3 V Output 1.5 V 1.5 V ≈0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 APPLICATION INFORMATION n-bit synchronous counters This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit (see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The ’ALS161B, ’AS161, ’ALS163B, and ’AS163 devices count in binary. When additional stages are added, the f max decreases in Figure 2, but remains unchanged in Figure 3. LSB LSB Clear (L) CLR CT=0 CTR Clear (L) CLR CT=0 CTR LOAD M1 LOAD M1 Count (H) ENT RCO Count (H) ENT RCO G3 3CT=MAX G3 3CT=MAX Disable (L) ENP Disable (L) ENP G4 G4 CLK CLK C5/T,3,4+ Clock C5/T,3,4+ Load (L) A 1,5D QA Load (L) A 1,5D QA B QB B QB Count (H) C QC C QC Disable (L) D QD D QD Clock CLR CT=0 CTR CLR CT=0 CTR LOAD M1 LOAD M1 ENT RCO ENT RCO G3 3CT=MAX G3 3CT=MAX ENP ENP G4 G4 CLK CLK C5/T,3,4+ C5/T,3,4+ A 1,5D QA A 1,5D QA B QB B QB C QC C QC D QD D QD CLR CT=0 CTR CLR CT=0 CTR LOAD LOAD M1 M1 ENT RCO ENT RCO G3 3CT=MAX G3 3CT=MAX ENP ENP G4 G4 CLK CLK C5/T,3,4+ C5/T,3,4+ A 1,5D QA A 1,5D QA B QB B QB C QC C QC D QD D QD CLR CT=0 CTR CLR CT=0 CTR LOAD M1 LOAD M1 ENT RCO ENT RCO G3 3CT=MAX G3 3CT=MAX ENP ENP G4 G4 CLK CLK C5/T,3,4+ C5/T,3,4+ A 1,5D QA A 1,5D QA B QB B QB C QC C QC D QD D QD To More Significant Stages To More Significant Stages fmax = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N – 2) + (ENT tsu) fmax = 1/(CLK to RCO tPLH) + (ENP tsu) Figure 2. Ripple-Mode Carry Circuit Figure 3. Carry Look-Ahead Circuit 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 83022012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83022012A SNJ54ALS 161BFK 8302201EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8302201EA SNJ54ALS161BJ 8302201FA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8302201FA SNJ54ALS161BW 83022022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83022022A SNJ54ALS 163BFK 8302202EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8302202EA SNJ54ALS163BJ JM38510/38001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 38001B2A JM38510/38001BEA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 38001BEA JM38510/38002B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 38002B2A JM38510/38002BEA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 38002BEA M38510/38001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 38001B2A M38510/38001BEA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 38001BEA M38510/38002B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 38002B2A M38510/38002BEA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 38002BEA SN54ALS161BJ ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54ALS161BJ SN54ALS163BJ ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54ALS163BJ SN74ALS161BD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS161B & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74ALS161BDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS161B & no Sb/Br) SN74ALS161BDRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS161B & no Sb/Br) SN74ALS161BN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74ALS161BN & no Sb/Br) SN74ALS161BNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS161B & no Sb/Br) SN74ALS163BD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B & no Sb/Br) SN74ALS163BDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B & no Sb/Br) SN74ALS163BDRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B & no Sb/Br) SN74ALS163BN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74ALS163BN & no Sb/Br) SN74ALS163BNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B & no Sb/Br) SN74AS161N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74AS161N & no Sb/Br) SN74AS161NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74AS161 & no Sb/Br) SN74AS163D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AS163 & no Sb/Br) SN74AS163N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74AS163N & no Sb/Br) SN74AS163NE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74AS163N & no Sb/Br) SNJ54ALS161BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83022012A SNJ54ALS 161BFK SNJ54ALS161BJ ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8302201EA SNJ54ALS161BJ SNJ54ALS161BW ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8302201FA SNJ54ALS161BW Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SNJ54ALS163BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83022022A SNJ54ALS 163BFK SNJ54ALS163BJ ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8302202EA SNJ54ALS163BJ SNJ54AS161J ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 SNJ54AS161J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS161B, SN54ALS163B, SN54AS161, SN74ALS161B, SN74ALS163B, SN74AS161 : •Catalog: SN74ALS161B, SN74ALS163B, SN74AS161 •Military: SN54ALS161B, SN54ALS163B, SN54AS161 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALS161BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74ALS161BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74ALS163BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74ALS163BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AS161NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALS161BDR SOIC D 16 2500 333.2 345.9 28.6 SN74ALS161BNSR SO NS 16 2000 367.0 367.0 38.0 SN74ALS163BDR SOIC D 16 2500 333.2 345.9 28.6 SN74ALS163BNSR SO NS 16 2000 367.0 367.0 38.0 SN74AS161NSR SO NS 16 2000 367.0 367.0 38.0 PackMaterials-Page2

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