数量阶梯 | 香港交货 | 国内含税 |
+xxxx | $xxxx | ¥xxxx |
查看当月历史价格
查看今年历史价格
SN74AHCT573PWR产品简介:
ICGOO电子元器件商城为您提供SN74AHCT573PWR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74AHCT573PWR价格参考¥0.80-¥2.31。Texas InstrumentsSN74AHCT573PWR封装/规格:逻辑 - 锁销, D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP。您可以下载SN74AHCT573PWR参考资料、Datasheet数据手册功能说明书,资料中有SN74AHCT573PWR 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC OCT TRNSP D-TYP LATCH 20TSSOP闭锁 Tri-St Octal D-Type |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,闭锁,Texas Instruments SN74AHCT573PWR74AHCT |
数据手册 | |
产品型号 | SN74AHCT573PWR |
产品目录页面 | |
产品种类 | 闭锁 |
传播延迟时间 | 8 ns at 5 V |
低电平输出电流 | 32 mA |
供应商器件封装 | 20-TSSOP |
其它名称 | 296-1121-6 |
包装 | Digi-Reel® |
单位重量 | 77 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | 20-TSSOP(0.173",4.40mm 宽) |
封装/箱体 | TSSOP-20 |
工作温度 | -40°C ~ 85°C |
工厂包装数量 | 2000 |
延迟时间-传播 | 1ns |
最大工作温度 | + 85 C |
最小工作温度 | - 40 C |
极性 | Non-Inverting |
标准包装 | 1 |
独立电路 | 1 |
电压-电源 | 4.5 V ~ 5.5 V |
电流-输出高,低 | 8mA,8mA |
电源电压-最大 | 5.5 V |
电源电压-最小 | 4.5 V |
电路 | 8:8 |
电路数量 | 8 Circuit |
系列 | SN74AHCT573 |
输入线路数量 | 3 Line |
输出类型 | 三态 |
输出线路数量 | 1 Line |
逻辑类型 | D 型透明锁存器 |
逻辑系列 | 74AHCT |
高电平输出电流 | - 8 mA |
Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54AHCT573,SN74AHCT573 SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 SNx4AHCT573 Octal Transparent D-Type Latches With 3-State Outputs 1 Features 3 Description • InputsareTTL-VoltageCompatible The SNx4AHCT573 devices are octal transparent D- 1 type latches. When the latch-enable (LE) input is • Latch-UpPerformanceExceeds250mAPer high, the Q outputs follow the data (D) inputs. When JESD17 LEislow,theQoutputsarelatchedatthelogiclevels • OnProductsComplianttoMIL-PRF-38535, oftheDinputs. AllParametersAreTestedUnlessOtherwise Noted.OnAllOtherProducts,Production DeviceInformation(1) ProcessingDoesNotNecessarilyIncludeTesting PARTNUMBER PACKAGE BODYSIZE(NOM) ofAllParameters. SSOP(20) 7.20mm×5.30mm • ESDProtectionExceedsJESD22 TVSOP(20) 5.00mm×4.40mm – 2000-VHuman-BodyModel(A114-A) SNx4AHCT573 SOIC(20) 12.80mm×7.50mm – 200-VMachineModel(A115-A) PDIP(20) 25.40mm×6.35mm – 1000-VCharged-DeviceModel(C101) TSSOP(20) 6.50mm×4.40mm (1) For all available packages, see the orderable addendum at 2 Applications theendofthedatasheet. • Servers • PCsandNotebooks • NetworkSwitches • WearableHealthandFitnessDevices • TelecomInfrastructures • ElectronicPointsofSale 4 Simplified Schematic OE LE C1 1Q 1D 1D ToSevenOtherChannels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
SN54AHCT573,SN74AHCT573 SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9.1 Overview...................................................................8 2 Applications........................................................... 1 9.2 FunctionalBlockDiagram.........................................8 3 Description............................................................. 1 9.3 FeatureDescription...................................................8 9.4 DeviceFunctionalModes..........................................8 4 SimplifiedSchematic............................................. 1 10 ApplicationandImplementation.......................... 9 5 RevisionHistory..................................................... 2 10.1 ApplicationInformation............................................9 6 PinConfigurationandFunctions......................... 3 10.2 TypicalApplication .................................................9 7 Specifications......................................................... 4 11 PowerSupplyRecommendations..................... 10 7.1 AbsoluteMaximumRatings......................................4 12 Layout................................................................... 10 7.2 HandlingRatings.......................................................4 12.1 LayoutGuidelines.................................................10 7.3 RecommendedOperatingConditions.......................4 12.2 LayoutExample....................................................10 7.4 ThermalInformation..................................................5 13 DeviceandDocumentationSupport................. 11 7.5 ElectricalCharacteristics...........................................5 7.6 TimingRequirements................................................5 13.1 RelatedLinks........................................................11 7.7 SwitchingCharacteristics..........................................6 13.2 Trademarks...........................................................11 7.8 OperatingCharacteristics..........................................6 13.3 ElectrostaticDischargeCaution............................11 7.9 TypicalCharacteristics..............................................6 13.4 Glossary................................................................11 8 ParameterMeasurementInformation..................7 14 Mechanical,Packaging,andOrderable Information........................................................... 11 9 DetailedDescription.............................................. 8 5 Revision History ChangesfromRevisionN(July2003)toRevisionO Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 • AddedMilitaryDisclaimertoFeatureslist.............................................................................................................................. 1 • AddedApplications................................................................................................................................................................. 1 • AddedPinFunctionstable...................................................................................................................................................... 3 • AddedHandlingRatingstable................................................................................................................................................ 4 • ChangedMAXoperatingtemperatureto125°CinRecommendedOperatingConditionstable. ......................................... 4 • AddedThermalInformationtable........................................................................................................................................... 5 • Added–40°Cto125°CtemperaturerangeforSN74AHCT573inElectricalCharacteristicstable........................................ 5 • Added–40°Cto125°CtemperaturerangeforSN74AHCT573inTimingRequirementstable............................................. 5 • AddedTypicalCharacteristics................................................................................................................................................ 6 • AddedDetailedDescriptionsection........................................................................................................................................ 8 • AddedApplicationandImplementationsection...................................................................................................................... 9 • AddedPowerSupplyRecommendationsandLayoutsections............................................................................................ 10 2 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 www.ti.com SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 6 Pin Configuration and Functions SN54AHCT573...JORWPACKAGE SN54AHCT573...FKPACKAGE SN74AHCT573...DB,DGV,DW,N,NS,ORPWPACKAGE (TOPVIEW) (TOPVIEW) C D D E CQ 2 1 OV 1 OE 1 20 V CC 1D 2 19 1Q 3 2 1 20 19 3D 4 18 2Q 2D 3 18 2Q 4D 5 17 3Q 3D 4 17 3Q 5D 6 16 4Q 4D 5 16 4Q 6D 7 15 5Q 5D 6 15 5Q 7D 8 14 6Q 6D 7 14 6Q 9 10 11 12 13 7D 8 13 7Q 8D 9 12 8Q D D EQ Q 8 N L8 7 GND 10 11 LE G PinFunctions PIN I/O DESCRIPTION NO. NAME 1 OE I OutputEnable 2 1D I 1DInput 3 2D I 2DInput 4 3D I 3DInput 5 4D I 4DInput 6 5D I 5DInput 7 6D I 6DInput 8 7D I 7DInput 9 8D I 8DInput 10 GND — Ground 11 LE I LatchEnable 12 8Q O 8QOutput 13 7Q O 7QOutput 14 6Q O 6QOutput 15 5Q O 5QOutput 16 4Q O 4QOutput 17 3Q O 3QOutput 18 2Q O 2QOutput 19 1Q O 1QOutput 20 V — PowerPin CC Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 7 V CC V Inputvoltagerange(2) –0.5 7 V I V Outputvoltagerange(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0orV >V ±20 mA OK O O CC I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±75 mA CC (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) SN54AHCT573 SN74AHCT573 UNIT MIN MAX MIN MAX V Supplyvoltage 4.5 5.5 4.5 5.5 V CC V High-levelinputvoltage 2 2 V IH V Low-levelinputvoltage 0.8 0.8 V IL V Inputvoltage 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V V O CC CC I High-leveloutputcurrent –8 –8 mA OH I Low-leveloutputcurrent 8 8 mA OL ∆t/∆v Inputtransitionriseorfallrate 20 20 ns/V T Operatingfree-airtemperature –55 125 –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs(SCBA004). 4 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 www.ti.com SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 7.4 Thermal Information SN74AHCT573 THERMALMETRIC(1) DW DB DGV N NS PW UNIT 20PINS R Junction-to-ambientthermalresistance 79.4 97.9 117.2 53.3 79.2 103.3 θJA R Junction-to-case(top)thermalresistance 45.7 59.6 32.7 40.0 45.7 37.8 θJC(top) R Junction-to-boardthermalresistance 46.9 53.1 58.7 34.2 46.8 54.3 θJB °C/W ψ Junction-to-topcharacterizationparameter 18.7 21.3 1.15 26.4 19.3 2.9 JT ψ Junction-to-boardcharacterizationparameter 46.5 52.7 58.0 34.1 46.4 53.8 JB R Junction-to-case(bottom)thermalresistance n/a n/a n/a n/a n/a n/a θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport(SPRA953). 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto125°C PARAMETER TESTCONDITIONS VCC TA=25°C SN54AHCT573 SN74AHCT573 SN74AHCT573 UNIT MIN TYP MAX MIN MAX MIN MAX MIN MAX IOH=−50µA 4.4 4.5 4.4 4.4 4.4 VOH 4.5V V IOH=−8mA 3.94 3.8 3.8 3.8 IOL=50µA 0.1 0.1 0.1 0.1 VOL 4.5V V IOL=8mA 0.36 0.44 0.44 0.44 II VI=5.5VorGND 05.V5tVo ±0.1 ±1(1) ±1 ±2 µA IOZ VO=VCCorGND 5.5V ±0.25 ±2.5 ±2.5 ±2.5 µA ICC VI=VCCorGND,IO=0 5.5V 4 40 40 40 µA ΔICC(2) OOntheerinipnuptuatsta3t.4VVCC, orGND 5.5V 1.35 1.5 1.5 1.5 mA Ci VI=VCCorGND 5V 2.5 10 10 10 pF Co VO=VCCorGND 5V 3 pF (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontestedatV =0V. CC (2) ThisistheincreaseinsupplycurrentforeachinputatoneofthespecifiedTTLvoltagelevels,ratherthan0VorV . CC 7.6 Timing Requirements overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure2) CC –40°Cto125°C T =25°C SN54AHCT573 SN74AHCT573 PARAMETER A SN74AHCT573 UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhigh 5 5 5 5 ns w t Setuptime,databeforeLE↓ 3.5 3.5 3.5 3.5 ns su t Holdtime,dataafterLE↓ 1.5 1.5 1.5 1.5 ns h Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 www.ti.com 7.7 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure2) CC PARAMETER FROM TO LOAD TA=25°C SN54AHCT573 SN74AHCT573 TAS=N–7440A°CHCtoT517235°C UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX tPLH 4.2(1) 6(1) 1(1) 6.5(1) 1 6.5 1 7 tPHL D Q CL=15pF 5.1(1) 7(1) 1(1) 9(1) 1 9 1 9.5 ns tPLH 4.7(1) 6.5(1) 1(1) 7.5(1) 1 7.5 1 8 tPHL LE Q CL=15pF 5.6(1) 7.5(1) 1(1) 9(1) 1 9 1 9.5 ns tPZH 4.1(1) 6.5(1) 1(1) 7(1) 1 7 1 8 tPZL OE Q CL=15pF 5.5(1) 7.5(1) 1(1) 9(1) 1 10 1 11 ns tPHZ 5.5(1) 8(1) 1(1) 11(1) 1 11 1 12 tPLZ OE Q CL=15pF 5.4(1) 8(1) 1(1) 9.5(1) 1 9.5 1 10.5 ns tPLH 5.2 7 1 7.5 1 7.5 1 8.5 D Q CL=50pF ns tPHL 6.1 8 1 10 1 10 1 10.5 tPLH 5.7 7.5 1 8.5 1 8.5 1 9.5 LE Q CL=50pF ns tPHL 6.6 8.5 1 10 1 10 1 10.5 tPZH 5.1 7.5 1 8 1 8 1 9 OE Q CL=50pF ns tPZL 6.5 8.5 1 11 1 11 1 11.5 tPHZ 6.7 9 1 12 1 12 1 12.5 OE Q CL=50pF ns tPLZ 6.4 9 1 10.5 1 10.5 1 11.5 tsk(o) CL=50pF 1.5(2) 1.5 ns (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. 7.8 Operating Characteristics V =5V,T =25°C CC A PARAMETER TESTCONDITIONS TYP UNIT C Powerdissipationcapacitance Noload, f=1MHz 16 pF pd 7.9 Typical Characteristics 6 5 4 s) n D ( 3 P T 2 1 TPD in ns 0 -100 -50 0 50 100 150 Temperature (qC) D001 Figure1.TPDvsTemperatureat5V 6 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 www.ti.com SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 8 Parameter Measurement Information VCC FromOutput Test FromOutput RL=1kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (seeNoteA) (seeNoteA) tPHZ/tPZH GND OpenDrain VCC LOADCIRCUITFOR LOADCIRCUITFOR TOTEM-POLEOUTPUTS 3-STATEANDOPEN-DRAINOUTPUTS 3V TimingInput 1.5V tw 0V th 3V tsu 3V Input 1.5V 1.5V DataInput 1.5V 1.5V 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPANDHOLDTIMES 3V 3V Output Input 1.5V 1.5V 1.5V 1.5V Control 0V 0V tPLH tPHL tPZL tPLZ Output VOH Waveform1 ≈VCC InO-Puhtapsuet 50%VCC 50%VCC S1atVCC 50%VCC VOL+0.3V VOL (seeNoteB) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50%VCC 50%VCVVCOOHL (WseSae1veNaftooGtremNBD2) 50%VCC VOH–0.3VV≈0OVH VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEANDDISABLETIMES INVERTINGANDNONINVERTINGOUTPUTS LOW-ANDHIGH-LEVELENABLING NOTES: A. CLincludesprobeandjigcapacitance. B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislowexceptwhendisabledbytheoutputcontrol. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishighexceptwhendisabledbytheoutputcontrol. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics: PRR≤1MHz,ZO=50Ω,tr≤3ns,tf≤3ns. D. Theoutputsaremeasuredoneatatimewithoneinputtransitionpermeasurement. E. Allparametersandwaveformsarenotapplicabletoalldevices. Figure2. LoadCircuitandVoltageWaveforms Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 www.ti.com 9 Detailed Description 9.1 Overview TheSNx4AHCT573devicesareoctaltransparentD-typelatches.Whenthelatch-enable(LE)inputishigh,theQ outputsfollowthedata(D)inputs.WhenLEislow,theQoutputsarelatchedatthelogiclevelsoftheDinputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interfaceorpull-upcomponents. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered whiletheoutputsareinthehigh-impedancestate. 9.2 Functional Block Diagram OE LE C1 1Q 1D 1D ToSevenOtherChannels 9.3 Feature Description • TTLinputs – Loweredswitchingthresholdallowsuptranslation3.3Vto5V • Slowedgesreduceoutputringing 9.4 Device Functional Modes Table1.FunctionTable (EachLatch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q 0 H X X Z 8 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 www.ti.com SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information The SN74AHCT573 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V V and2-VV .Thisfeaturemakesthedeviceidealfortranslatingupfrom3.3Vto5V.Figure4 showsthistype IL IH oftranslation. 10.2 Typical Application Regulated 5 V Regulated 3.3 V OE VCC LE 1D 1Q µC or 5 V µC System Logic System Logic 8D 8Q LEDs GND Figure3. TypicalApplicationSchematic 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads;therefore,routingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. Recommendedinputconditions – Risetimeandfalltimespecs:See(Δt/ΔV)intheRecommendedOperatingConditionstable. – SpecifiedHighandlowlevels:See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. Recommendoutputconditions – Loadcurrentsshouldnotexceed25mAperoutputand75mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 www.ti.com Typical Application (continued) 10.2.3 ApplicationCurves Figure4.UpTranslation 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μF bypass capacitor is recommended. If there are multiple V pins, 0.01 μF or 0.022 μF is CC recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed asclosetothepowerpinaspossibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsshouldnoteverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V ; whichever makes more sense or is more convenient. It is generally acceptable to float CC outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the IO’s so they cannot float when disabled. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure5. LayoutDiagram 10 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHCT573 SN74AHCT573
SN54AHCT573,SN74AHCT573 www.ti.com SCLS243O–OCTOBER1995–REVISEDSEPTEMBER2014 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54AHCT573 Clickhere Clickhere Clickhere Clickhere Clickhere SN74AHCT573 Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54AHCT573 SN74AHCT573
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9685501QRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685501QR A SNJ54AHCT573J 5962-9685501QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685501QS A SNJ54AHCT573W SN74AHCT573DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HB573 & no Sb/Br) SN74AHCT573DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HB573 & no Sb/Br) SN74AHCT573DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT573 & no Sb/Br) SN74AHCT573DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT573 & no Sb/Br) SN74AHCT573DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT573 & no Sb/Br) SN74AHCT573N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT573N (RoHS) SN74AHCT573NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT573N (RoHS) SN74AHCT573PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HB573 & no Sb/Br) SN74AHCT573PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HB573 & no Sb/Br) SN74AHCT573PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HB573 & no Sb/Br) SN74AHCT573PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HB573 & no Sb/Br) SNJ54AHCT573J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685501QR A SNJ54AHCT573J SNJ54AHCT573W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685501QS A SNJ54AHCT573W Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AHCT573, SN74AHCT573 : •Catalog: SN74AHCT573 •Military: SN54AHCT573 NOTE: Qualified Version Definitions: Addendum-Page 2
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHCT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AHCT573DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHCT573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74AHCT573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74AHCT573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74AHCT573PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHCT573DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AHCT573DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74AHCT573DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AHCT573PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74AHCT573PWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74AHCT573PWRG4 TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2
None
PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com
EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
None
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265
None
None
None
PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com
EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated