SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 (cid:0) Inputs Are TTL-Voltage Compatible SN54AHCT132...J OR W PACKAGE (cid:0) SN74AHCT132...D, DB, DGV, N, NS, OR PW PACKAGE Operation From Very Slow Input (TOP VIEW) Transitions (cid:0) Temperature-Compensated Threshold 1A 1 14 VCC Levels 1B 2 13 4B (cid:0) High Noise Immunity 1Y 3 12 4A (cid:0) Same Pinouts as ’AHCT00 2A 4 11 4Y (cid:0) 2B 5 10 3B Latch-Up Performance Exceeds 250 mA Per 2Y 6 9 3A JESD 17 (cid:0) GND 7 8 3Y ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) SN54AHCT132...FK PACKAGE (TOP VIEW) – 1000-V Charged-Device Model (C101) C B A C CB description 1 1 N V 4 3 2 1 20 19 The ’AHCT132 devices are quadruple 1Y 4 18 4A positive-NAND gates. NC 5 17 NC These devices perform the Boolean function 2A 6 16 4Y Y = A • B or Y = A + B in positive logic. NC 7 15 NC 2B 8 14 3B Each circuit functions as a NAND gate, but 9 10 1112 13 because of the Schmitt action, it has different input YD CY A threshold levels for positive- and negative-going 2N N3 3 G signals. NC – No internal connection These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP – N Tube SN74AHCT132N SN74AHCT132N Tube SN74AHCT132D SSOOIICC –– DD AAHHCCTT113322 Tape and reel SN74AHCT132DR –40°C to 85°C SOP – NS Tape and reel SN74AHCT132NSR AHCT132 SSOP – DB Tape and reel SN74AHCT132DBR HB132 TSSOP – PW Tape and reel SN74AHCT132PWR HB132 TVSOP – DGV Tape and reel SN74AHCT132DGVR HB132 CDIP – J Tube SNJ54AHCT132J SNJ54AHCT132J –55°C to 125°C CFP – W Tube SNJ54AHCT132W SNJ54AHCT132W LCCC – FK Tube SNJ54AHCT132FK SNJ54AHCT132FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  2002, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 FUNCTION TABLE (each gate) INPUTS OUTPUT A B Y H H L L X H X L H logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W JA DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 recommended operating conditions (see Note 3) SN54AHCT132 SN74AHCT132 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V IOH High-level output current –8 –8 mA IOL Low-level output current 8 8 mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AHCT132 SN74AHCT132 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX VT+ 4.5 V 0.9 1.9 0.9 1.9 0.9 1.9 PPoossiittiivvee-ggooiinngg iinnppuutt VV threshold voltage 5.5 V 1 2.1 1 2.1 1 2.1 VT– 4.5 V 0.5 1.5 0.5 1.5 0.5 1.5 NNeeggaattiivvee-ggooiinngg iinnppuutt VV threshold voltage 5.5 V 0.6 1.7 0.6 1.7 0.6 1.7 ∆VT 4.5 V 0.3 1.4 0.3 1.4 0.3 1.4 HHyysstteerreessiiss VV (VT+ – VT–) 5.5 V 0.3 1.5 0.3 1.5 0.3 1.5 IOH = –50 (cid:0)A 4.4 4.5 4.4 4.4 VVOOHH 44.55 VV VV IOH = –8 mA 3.94 3.8 3.8 IOL = 50 (cid:0)A 0.1 0.1 0.1 VVOOLL 44.55 VV VV IOL = 8 mA 0.36 0.5 0.44 II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 (cid:0)A ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 (cid:0)A One input at 3.4 V, ∆ICC† Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA Ci VI = VCC or GND 5 V 2 10 10 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. †This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 switching characteristics over recommended operating free-air temperature range, VCC = 5 V±0.5 V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 25°C SN54AHCT132 SN74AHCT132 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX tPLH 5.5* 8* 1* 9* 1 9 AA oorr BB YY CCLL == 1155 ppFF nnss tPHL 4.5* 6* 1* 7* 1 7 tPLH 6.5 9 1 10 1 10 AA oorr BB YY CCLL == 5500 ppFF nnss tPHL 5.5 7 1 8 1 8 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHCT132 PPAARRAAMMEETTEERR UUNNIITT MIN TYP MAX VOL(P) Quiet output, maximum dynamic VOL 0.5 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.28 –0.8 V VOH(V) Quiet output, minimum dynamic VOH 5 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 V NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 15 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS 3 V Timing Input 1.5 V tw 0 V th 3 V tsu 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 ≈VCC InO-Puhtapsuet 50% VCC 50% VCC S1 at VCC 50% VCC VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH – 0.3 VV≈0O VH VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AHCT132D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT132 & no Sb/Br) SN74AHCT132DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB132 & no Sb/Br) SN74AHCT132DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT132 & no Sb/Br) SN74AHCT132DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB132 & no Sb/Br) SN74AHCT132DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT132 & no Sb/Br) SN74AHCT132DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT132 & no Sb/Br) SN74AHCT132N ACTIVE PDIP N 14 25 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74AHCT132N (RoHS) SN74AHCT132NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT132 & no Sb/Br) SN74AHCT132PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB132 & no Sb/Br) SN74AHCT132PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB132 & no Sb/Br) SN74AHCT132PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB132 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHCT132DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74AHCT132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AHCT132NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AHCT132PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHCT132DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74AHCT132DR SOIC D 14 2500 367.0 367.0 38.0 SN74AHCT132NSR SO NS 14 2000 367.0 367.0 38.0 SN74AHCT132PWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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