Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 SNx4AHC574 Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 1 Features 3 Description • OperatingRange2-Vto5.5-VV The SNx4AHC574 devices are octal edge-triggered 1 CC D-type flip-flops that feature 3-state outputs designed • 3-StateOutputsDriveBusLinesDirectly specifically for driving highly capacitive or relatively • Latch-UpPerformanceExceeds250mA low-impedance loads. These devices are particularly PerJESD17 suitable for implementing buffer registers, I/O ports, • OnProductsComplianttoMIL-PRF-38535, bidirectionalbusdrivers,andworkingregisters. AllParametersAreTestedUnlessOtherwise DeviceInformation(1) Noted.OnAllOtherProducts,Production ProcessingDoesNotNecessarilyIncludeTesting PARTNUMBER PACKAGE BODYSIZE(NOM) ofAllParameters. SSOP(20) 7.50mm×5.30mm • ESDProtectionExceedsJESD22 TVSOP(20) 5.00mm×4.40mm – 2000-VHuman-BodyModel SOIC(20) 12.80mm×7.50 SNx4AHC574 mm – 200-VMachineModel 25.40mm×6.35 PDIP(20) – 1000-VCharged-DeviceModel mm TSSOP(20) 6.50mm×4.40mm 2 Applications (1) For all available packages, see the orderable addendum at • SmartGrids theendofthedatasheet. • TVs • SetTopBoxes • Audio • Servers • SurveillanceCameras • NetworkSwitches • Infotainment 4 Simplified Schematic OE CLK C1 1Q 1D 1D ToSevenOtherChannels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ParameterMeasurementInformation..................9 2 Applications........................................................... 1 9 DetailedDescription............................................ 10 3 Description............................................................. 1 9.1 Overview.................................................................10 4 SimplifiedSchematic............................................. 1 9.2 FunctionalBlockDiagram.......................................10 5 RevisionHistory..................................................... 2 9.3 FeatureDescription.................................................10 9.4 DeviceFunctionalModes........................................10 6 PinConfigurationandFunctions......................... 3 10 ApplicationandImplementation........................ 11 7 Specifications......................................................... 4 10.1 ApplicationInformation..........................................11 7.1 AbsoluteMaximumRatings......................................4 10.2 TypicalApplication ...............................................11 7.2 ESDRatings..............................................................4 11 PowerSupplyRecommendations..................... 12 7.3 RecommendedOperatingConditions.......................4 7.4 ThermalInformation..................................................5 12 Layout................................................................... 13 7.5 ElectricalCharacteristics...........................................5 12.1 LayoutGuidelines.................................................13 7.6 TimingRequirements,V =3.3V±0.3V..............5 12.2 LayoutExample....................................................13 CC 7.7 TimingRequirements,V =5V±0.5V.................6 13 DeviceandDocumentationSupport................. 13 CC 7.8 SwitchingCharacteristics,V =3.3V±0.3V........6 13.1 RelatedLinks........................................................13 CC 7.9 SwitchingCharacteristics,V =5V±0.5V...........7 13.2 Trademarks...........................................................13 CC 7.10 NoiseCharacteristics..............................................7 13.3 ElectrostaticDischargeCaution............................13 7.11 OperatingCharacteristics........................................7 13.4 Glossary................................................................13 7.12 TypicalCharacteristics............................................8 14 Mechanical,Packaging,andOrderable Information........................................................... 13 5 Revision History ChangesfromRevisionI(July2003)toRevisionJ Page • AddedApplications,DeviceInformationtable,PinFunctionstable,ESDRatingstable,ThermalInformationtable, TypicalCharacteristics,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 • AddedMilitaryDisclaimertoFeatureslist.............................................................................................................................. 1 • ChangedMAXoperatingtemperatureto125°CinRecommendedOperatingConditionstable. ......................................... 4 2 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 www.ti.com SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 6 Pin Configuration and Functions SN54AHC574...JORWPACKAGE SN54AHC574...FKPACKAGE SN74AHC574...DB,DGV,DW,N,NS,ORPWPACKAGE (TOPVIEW) (TOPVIEW) C D D E CQ 2 1 OV 1 OE 1 20 VCC 1D 2 19 1Q 3 2 1 20 19 3D 4 18 2Q 2D 3 18 2Q 4D 5 17 3Q 3D 4 17 3Q 5D 6 16 4Q 4D 5 16 4Q 6D 7 15 5Q 5D 6 15 5Q 7D 8 14 6Q 6D 7 14 6Q 9 10 11 12 13 7D 8 13 7Q 8D 9 12 8Q 8D ND LK8Q 7Q GND 10 11 CLK G C PinFunctions PIN TYPE DESCRIPTION NO. NAME 1 OE I OutputEnablePin 2 1D I 1DInput 3 2D I 2DInput 4 3D I 3DInput 5 4D I 4DInput 6 5D I 5DInput 7 6D I 6DInput 8 7D I 7DInput 9 8D I 8DInput 10 GND — GroundPin 11 CLK I ClockPin 12 8Q O 8QOutput 13 7Q O 7QOutput 14 6Q O 6QOutput 15 5Q O 5QOutput 16 4Q O 4QOutput 17 3Q O 3QOutput 18 2Q O 2QOutput 19 1Q O 1QOutput 20 V — PowerPin CC Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 7 V CC V Inputvoltagerange(2) –0.5 7 V I V Outputvoltagerange(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0orV >V ±20 mA OK O O CC I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±75 mA CC T Storagetemperaturerange –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) 2000 Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101, V(ESD) Electrostaticdischarge allpins(2) 1000 V MachineModel(MM) 200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) SN54AHC574 SN74AHC574 UNIT MIN MAX MIN MAX V Supplyvoltage 2 5.5 2 5.5 V CC V =2V 1.5 1.5 CC V High-levelinputvoltage V =3V 2.1 2.1 V IH CC V =5.5V 3.85 3.85 CC V =2V 0.5 0.5 CC V Low-levelInputvoltage V =3V 0.9 0.9 V IL CC V =5.5V 1.65 1.65 CC V Inputvoltage 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V V O CC CC V =2V –50 –50 µA CC I High-leveloutputcurrent V =3.3V±0.3V –4 –4 OH CC mA V =5V±0.5V –8 –8 CC V =2V 50 50 µA CC I Low-leveloutputcurrent V =3.3V±0.3V 4 4 OL CC mA V =5V±0.5V 8 8 CC V =3.3V±0.3V 100 100 CC Δt/Δv Inputtransitionriseorfallrate ns/V V =5V±0.5V 20 20 CC T Operatingfree-airtemperature –55 125 –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs(SCBA004). 4 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 www.ti.com SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 7.4 Thermal Information SN74AHC574 THERMALMETRIC(1) DB DGV DW N NS PW UNIT 20PINS R Junction-to-ambientthermalresistance 97.9 117.2 79.4 53.3 79.2 103.3 θJA R Junction-to-case(top)thermalresistance 59.6 32.7 45.7 40.0 45.7 37.8 θJC(top) R Junction-to-boardthermalresistance 53.1 58.7 46.9 34.2 46.8 54.3 °C/W θJB ψ Junction-to-topcharacterizationparameter 21.3 1.15 18.7 26.4 19.3 2.9 JT ψ Junction-to-boardcharacterizationparameter 52.7 58.0 46.5 34.1 46.4 53.8 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport(SPRA953). 7.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54AHC574 SN74AHC574 TA=25°C PARAMETER TESTCONDITIONS VCC –40°Cto85°C –40°Cto85°C –40°Cto125°C UNIT MIN TYP MAX MIN MAX MIN MAX MIN MAX 2V 1.9 2 1.9 1.9 1.9 IOH=–50µA 3V 2.9 3 2.9 2.9 2.9 VOH 4.5V 4.4 4.5 4.4 4.4 4.4 V IOH=–4mA 3V 2.58 2.48 2.48 2.48 IOH=–8mA 4.5V 3.94 3.8 3.8 3.8 2V 0.1 0.1 0.1 0.1 IOL=50µA 3V 0.1 0.1 0.1 0.1 VOL 4.5V 0.1 0.1 0.1 0.1 V IOH=4mA 3V 0.36 0.5 0.44 0.44 IOH=8mA 4.5V 0.36 0.5 0.44 0.44 II VI=5.5VorGND 05.V5tVo ±0.1 ±1(1) ±1 ±1 µA IOZ(2) VVOI(O=EV)C=CoVrILGoNrDVIH 5.5V ±0.25 ±2.5 ±2.5 ±2.5 µA ICC VI=VCCorGND, IO=0 5.5V 4 40 40 40 µA Ci VI=VCCorGND 5V 3 10 10 10 pF CO VO=VCCorGND 5V 3 pF (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontestedatV =0V. CC (2) Forinputandoutputpins,I includestheinputleakagecurrent. OZ 7.6 Timing Requirements, V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54AHC574 SN74AHC574 T =25°C A PARAMETER –40°Cto85°C –40°Cto85°C –40°Cto125°C UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,CLKhighorlow 5 5 5 5.5 ns w t Setuptime,databeforeCLK↑ 3.5 3.5 3.5 4 ns su t Holdtime,dataafterCLK↑ 1.5 1.5 1.5 2 ns h Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 www.ti.com 7.7 Timing Requirements, V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54AHC574 SN74AHC574 T =25°C A PARAMETER –40°Cto85°C –40°Cto85°C –40°Cto125°C UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,CLKhighorlow 5 5 5 5.5 ns w t Setuptime,databeforeCLK↑ 3 3 3 3.5 ns su t Holdtime,dataafterCLK↑ 1.5 1.5 1.5 2 ns h 7.8 Switching Characteristics, V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54AHC574 SN74AHC574 FROM TO LOAD TA=25°C PARAMETER –40°Cto85°C –40°Cto85°C –40°Cto125°C UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX CL=15pF 80(1) 125(1) 65(1) 65 65 fMAX MHz CL=50pF 50 75 45 45 45 tPLH 8.5(1) 13.2(1) 1(1) 15.5(1) 1 15.5 1 17 tPHL CLK Q CL=15pF 8.5(1) 13.2(1) 1(1) 15.5(1) 1 15.5 1 17 ns tPZH 8.2(1) 12.8(1) 1(1) 15(1) 1 15 1 16 tPZL OE Q CL=15pF 8.2(1) 12.8(1) 1(1) 15(1) 1 15 1 16 ns tPHZ 8.5(1) 13(1) 1(1) 15(1) 1 15 1 16 tPLZ OE Q CL=15pF 8.5(1) 13(1) 1(1) 15(1) 1 15 1 16 ns tPLH 11 16.7 1 19 1 19 1 20.5 CLK Q CL=50pF ns tPHL 11 16.7 1 19 1 19 1 20.5 tPZH 10.7 16.3 1 18.5 1 18.5 1 19.5 OE Q CL=50pF ns tPZL 10.7 16.3 1 18.5 1 18.5 1 19.5 tPHZ 11 15 1 17 1 17 1 18 OE Q CL=50pF ns tPLZ 11 15 1 17 1 17 1 18 tsk(o) CL=50pF 1.5(2) 1.5 ns (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. 6 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 www.ti.com SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 7.9 Switching Characteristics, V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54AHC574 SN74AHC574 FROM TO LOAD TA=25°C PARAMETER –40°Cto85°C –40°Cto85°C –40°Cto125°C UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX CL=15pF 130(1) 180(1) 110(1) 110 110 fMAX MHz CL=50pF 85 115 75 75 75 tPLH 5.6(1) 8.6(1) 1(1) 10(1) 1 10 1 11 tPHL CLK Q CL=15pF 5.6(1) 8.6(1) 1(1) 10(1) 1 10 1 11 ns tPZH 5.9(1) 9(1) 1(1) 10.5(1) 1 10.5 1 11.5 tPZL OE Q CL=15pF 5.9(1) 9(1) 1(1) 10.5(1) 1 10.5 1 11.5 ns tPHZ 5.5(1) 9(1) 1(1) 10.5(1) 1 10.5 1 11.5 tPLZ OE Q CL=15pF 5.5(1) 9(1) 1(1) 10.5(1) 1 10.5 1 11.5 ns tPLH 7.1 10.6 1 12 1 12 1 13 CLK Q CL=50pF ns tPHL 7.1 10.6 1 12 1 12 1 13 tPZH 7.4 11 1 12.5 1 12.5 1 13.5 OE Q CL=50pF ns tPZL 7.4 11 1 12.5 1 12.5 1 13.5 tPHZ 7.1 10.1 1 11.5 1 11.5 1 12.5 OE Q CL=50pF ns tPLZ 7.1 10.1 1 11.5 1 11.5 1 12.5 tsk(o) CL=50pF 1(2) 1 1 ns (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. 7.10 Noise Characteristics V =5V,C =50pF,T =25°C(1) CC L A SN74AHC574 PARAMETER UNIT MIN MAX V Quietoutput,maximumdynamicV 0.8 V OL(P) OL V Quietoutput,minimumdynamicV –0.8 V OL(V) OL V Quietoutput,minimumdynamicV 4.2 V OH(V) OH V High-leveldynamicinputvoltage 3.5 V IH(D) V Low-leveldynamicinputvoltage 1.5 V IL(D) (1) Characteristicsareforsurface-mountpackagesonly. 7.11 Operating Characteristics V =5V,T =25°C CC A PARAMETER TESTCONDITIONS TYP UNIT C Powerdissipationcapacitance Noload, f=1MHz 28 pF pd Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 www.ti.com 7.12 Typical Characteristics 7 8 7 6 6 5 5 s) s) n n D ( 4 D ( 4 P P T T 3 3 2 2 1 TPD in ns TPD in ns 1 0 -100 -50 0 50 100 150 0 1 2 3 4 5 6 Temperature (qC) D001 VCC D001 Figure1.TPDvsTemperature Figure2.TPDvsV at25°C CC 8 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 www.ti.com SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 8 Parameter Measurement Information VCC FromOutput Test FromOutput RL=1kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (seeNoteA) (seeNoteA) tPHZ/tPZH GND OpenDrain VCC LOADCIRCUITFOR LOADCIRCUITFOR TOTEM-POLEOUTPUTS 3-STATEANDOPEN-DRAINOUTPUTS VCC TimingInput 50%VCC tw th 0V VCC tsu VCC Input 50%VCC 50%VCC DataInput 50%VCC 50%VCC 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPANDHOLDTIMES VCC VCC Output Input 50%VCC 50%VCC Control 50%VCC 50%VCC 0V 0V tPLH tPHL tPZL tPLZ Output VOH Waveform1 ≈VCC InO-Puhtapsuet 50%VCC 50%VCC S1atVCC 50%VCC VOL+0.3V VOL (seeNoteB) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50%VCC 50%VCVVCOOHL (WseSae1veNaftooGtremNBD2) 50%VCC VOH–0.3VV≈0OVH VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEANDDISABLETIMES INVERTINGANDNONINVERTINGOUTPUTS LOW-ANDHIGH-LEVELENABLING NOTES: A. CLincludesprobeandjigcapacitance. B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislowexceptwhendisabledbytheoutputcontrol. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishighexceptwhendisabledbytheoutputcontrol. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,ZO=50Ω,tr≤3ns,tf≤3ns. D. Theoutputsaremeasuredoneatatimewithoneinputtransitionpermeasurement. E. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 www.ti.com 9 Detailed Description 9.1 Overview The SNx4AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable forimplementingbufferregisters,I/Oports,bidirectionalbusdrivers,andworkingregisters. Onthepositivetransitionoftheclock(CLK)input,theQoutputsaresettothelogiclevelsofthedata(D)inputs. ThestatesoftheQoutputsarenotpredictableuntilthefirstvalidclock. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interfaceorpull-upcomponents. 9.2 Functional Block Diagram OE CLK C1 1Q 1D 1D ToSevenOtherChannels 9.3 Feature Description • 5.5-Vtolerantinputallowsfor5Vto3.3Vvoltagetranslation • Slowedgesreduceoutputringing 9.4 Device Functional Modes Table1.FunctionTable (EachFlip-Flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ L L L HorL X Q 0 H X X Z 10 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 www.ti.com SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information SN74AHC574 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on theoutputs.Theinputscanacceptvoltagesto5.5VatanyvalidV makingitIdealfordowntranslation CC 10.2 Typical Application 5-V regulated 3.3-V or 5-V regulated OE VCC CLK 1D 1Q µC or µC System Logic System Logic LEDs 8D 8Q GND Figure4. TypicalApplicationSchematic 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads,soroutingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Forrisetimeandfalltimespecifications,see Δt/ΔVintheRecommendedOperatingConditions table. – ForspecifiedHighandlowlevels,seeV andV intheRecommendedOperatingConditions table. IH IL 2. RecommendOutputConditions – Loadcurrentsshouldnotexceed25mAperoutputand75mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 www.ti.com Typical Application (continued) 10.2.3 ApplicationCurves Figure5.SwitchingCharactersiticsComparison 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μF is recommended. If there are multiple V pins, 0.01 μF or 0.022 μF is recommended for each CC power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possibleforbestresults. 12 SubmitDocumentationFeedback Copyright©1995–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC574 SN74AHC574

SN54AHC574,SN74AHC574 www.ti.com SCLS244J–OCTOBER1995–REVISEDDECEMBER2014 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V , whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a CC transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted.ThiswillnotdisabletheinputsectionoftheI/Ossotheyalsocannotfloatwhendisabled. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1995–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54AHC574 SN74AHC574

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9685401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9685401Q2A SNJ54AHC 574FK 5962-9685401QRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685401QR A SNJ54AHC574J 5962-9685401QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685401QS A SNJ54AHC574W SN74AHC574DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 & no Sb/Br) SN74AHC574DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 & no Sb/Br) SN74AHC574DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 & no Sb/Br) SN74AHC574DWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 & no Sb/Br) SN74AHC574DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 & no Sb/Br) SN74AHC574DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 & no Sb/Br) SN74AHC574N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74AHC574N (RoHS) SN74AHC574NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 & no Sb/Br) SN74AHC574PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 & no Sb/Br) SN74AHC574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 & no Sb/Br) SN74AHC574PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 & no Sb/Br) SNJ54AHC574FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9685401Q2A SNJ54AHC Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 574FK SNJ54AHC574J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685401QR A SNJ54AHC574J SNJ54AHC574W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685401QS A SNJ54AHC574W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF SN54AHC574, SN74AHC574 : •Catalog: SN74AHC574 •Military: SN54AHC574 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHC574DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AHC574DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHC574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74AHC574NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74AHC574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHC574DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AHC574DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74AHC574DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AHC574NSR SO NS 20 2000 367.0 367.0 45.0 SN74AHC574PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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