Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 SNx4AHC540 Octal Buffers/Drivers With 3-State Outputs 1 Features 3 Description • OperatingRange2-Vto5.5-VV The SNx4AHC540 octal buffers/drivers are ideal for 1 CC driving bus lines or buffer memory address registers. • Latch-UpPerformanceExceeds250mA These devices feature inputs and outputs on opposite PerJESD17 sides of the package to facilitate printed circuit board • OnProductsComplianttoMIL-PRF-38535, layout. AllParametersAreTestedUnlessOtherwise Noted.OnAllOtherProducts,Production DeviceInformation(1) ProcessingDoesNotNecessarilyIncludeTesting PARTNUMBER PACKAGE(PINS) BODYSIZE(NOM) ofAllParameters. SN74AHC540N PDIP(20) 25.40mm×6.35mm SN74AHC540DB SSOP(20) 7.50mm×5.30mm 2 Applications SN74AHC540PW TSSOP(20) 6.50mm×4.40mm • Servers SN74AHC540DGV TVSOP(20) 5.00mm×4.40mm SN74AHC540DW SOIC(20) 12.80mm×7.50mm • PCsandNotebooks SNJ54AHC540FK LCCC(20) 9.0mmx9.0mm • NetworkSwitches SNJ54AHC540W CFP(20) 13.72mmx8.13mm • WearableHealthandFitnessDevices (1) For all available packages, see the orderable addendum at • TelecomInfrastructures theendofthedatasheet. • ElectronicPointsofSale SimplifiedSchematic OE1 OE2 A1 Y1 ToSevenOtherChannels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................10 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................10 3 Description............................................................. 1 8.3 FeatureDescription.................................................10 8.4 DeviceFunctionalModes........................................10 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 11 5 PinConfigurationandFunctions......................... 4 9.1 ApplicationInformation............................................11 6 Specifications......................................................... 5 9.2 TypicalApplication .................................................11 6.1 AbsoluteMaximumRatings......................................5 10 PowerSupplyRecommendations..................... 12 6.2 ESDRatings..............................................................5 10.1 LayoutGuidelines.................................................12 6.3 RecommendedOperatingConditions.......................5 11 Layout................................................................... 12 6.4 ThermalInformation..................................................6 6.5 ElectricalCharacteristics...........................................6 11.1 LayoutExample....................................................12 6.6 SwitchingCharacteristics,V =3.3V±0.3V........7 12 DeviceandDocumentationSupport................. 13 CC 6.7 SwitchingCharacteristics,V =5V±0.5V...........7 12.1 CommunityResources..........................................13 CC 6.8 NoiseCharacteristics................................................8 12.2 RelatedLinks........................................................13 6.9 OperatingCharacteristics..........................................8 12.3 Trademarks...........................................................13 6.10 TypicalCharacteristics............................................8 12.4 ElectrostaticDischargeCaution............................13 7 ParameterMeasurementInformation..................9 12.5 Glossary................................................................13 8 DetailedDescription............................................ 10 13 Mechanical,Packaging,andOrderable Information........................................................... 13 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionL(October2015)toRevisionM Page • UpdatedfrontpageSimplifiedSchematicdiagram ............................................................................................................... 1 • UpdatedPinOutdrawingdiagramstonewstandard............................................................................................................ 4 • UpdatedFunctionalBlockDiagram ..................................................................................................................................... 10 • UpdatedOutputsinFunctionTableofDeviceFunctionalModessection .......................................................................... 10 ChangesfromRevisionK(September2014)toRevisionL Page • Addedjunctiontemperature .................................................................................................................................................. 5 • UpdatedtheHandlingRatingstabletoanESDRatingstableandmovethestoragetemperaturetotheAbsolute MaximumRatingstable ......................................................................................................................................................... 5 • CorrectedtheOverviewtostatethattheoutputsprovidenon-inverteddata ...................................................................... 10 • AddedCommunityResources ............................................................................................................................................. 13 ChangesfromRevisionJ(July2003)toRevisionK Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 • AddedMilitaryDisclaimertoFeatureslist.............................................................................................................................. 1 • AddedApplications................................................................................................................................................................. 1 • Updatedthesimplifiedschematic........................................................................................................................................... 1 • AddedPinFunctionstable...................................................................................................................................................... 4 • AddedHandlingRatingstable................................................................................................................................................ 5 • Extendedoperatingtemperaturerangeto125°C................................................................................................................... 5 • AddedThermalInformationtable........................................................................................................................................... 6 • Added–40°Cto125°CrangeforSN74AHC540inElectricalCharacteristicstable............................................................... 6 2 SubmitDocumentationFeedback Copyright©1995–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 www.ti.com SCLS260M–DECEMBER1995–REVISEDMAY2016 • AddedT =–40°Cto125°CforSN74AHC540inbothSwitchingCharacteristicstables...................................................... 7 A • AddedTypicalCharacteristics................................................................................................................................................ 8 • AddedDetailedDescriptionsection...................................................................................................................................... 10 • AddedApplicationandImplementationsection.................................................................................................................... 11 • AddedPowerSupplyRecommendationsandLayoutsections............................................................................................ 12 Copyright©1995–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 www.ti.com 5 Pin Configuration and Functions SN54AHC540:JorWPackage;SN74AHC540:DB,DGV,DW, N,NS,orPWPackage SN54AHC540:FKPackage SN54AHC540:20-PinCDIPorCFP;SN74AHC540:20-Pin 20-PinLCCC SSOP,TVSOP,SOIC,PDIP,PDIP,orTSSOP TopView TopView 1 C2 2 1 E CE A A O V O OE 1 1 20 VCC A1 2 19 OE 2 3 2 1 0 9 A2 3 18 Y1 2 1 A3 4 18 Y1 A3 4 17 Y2 A4 5 17 Y2 A4 5 16 Y3 A5 6 16 Y3 A5 6 15 Y4 A6 7 15 Y4 A6 7 14 Y5 A7 8 14 Y5 A7 8 13 Y6 A8 9 12 Y7 0 1 2 3 9 1 1 1 1 GND 10 11 Y8 Not to scale 8 D 8 7 6 A N Y Y Y G Not to scale PinFunctions PIN I/O DESCRIPTION NO. NAME 1 OE1 I OutputEnable1 2 A1 I A1Input 3 A2 I A2Input 4 A3 I A3Input 5 A4 I A4Input 6 A5 I A5Input 7 A6 I A6Input 8 A7 I A7Input 9 A8 I A8Input 10 GND — Ground 11 Y8 O Y8Output 12 Y7 O Y7Output 13 Y6 O Y6Output 14 Y5 O Y5Output 15 Y4 O Y4Output 16 Y3 O Y3Output 17 Y2 O Y2Output 18 Y1 O Y1Output 19 OE2 I OutputEnable2 20 V — PowerPin CC 4 SubmitDocumentationFeedback Copyright©1995–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 www.ti.com SCLS260M–DECEMBER1995–REVISEDMAY2016 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 7 V CC V Inputvoltagerange(2) –0.5 7 V I V Outputvoltagerange(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0orV >V ±20 mA OK O O CC I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±75 mA CC T Junctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) 1000 Electrostatic V(ESD) discharge Cpihnasr(g2)eddevicemodel(CDM),perJEDECspecificationJESD22-C101,all 2000 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) SN54AHC540 SN74AHC540 UNIT MIN MAX MIN MAX V Supplyvoltage 2 5.5 2 5.5 V CC V =2V 1.5 1.5 CC V High-levelinputvoltage V =3V 2.1 2.1 V IH CC V =5.5V 3.85 3.85 CC V =2V 0.5 0.5 CC V Low-levelInputvoltage V =3V 0.9 0.9 V IL CC V =5.5V 1.65 1.65 CC V Inputvoltage 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V V O CC CC V =2V –50 –50 µA CC I High-leveloutputcurrent V =3.3V±0.3V –4 –4 OH CC mA V =5V±0.5V –8 –8 CC V =2V 50 50 µA CC I Low-leveloutputcurrent V =3.3V±0.3V 4 4 OL CC mA V =5V±0.5V 8 8 CC V =3.3V±0.3V 100 100 CC Δt/Δv Inputtransitionriseorfallrate ns/V V =5V±0.5V 20 20 CC T Operatingfree-airtemperature –55 125 –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs(SCBA004). Copyright©1995–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 www.ti.com 6.4 Thermal Information SN74AHC540 THERMALMETRIC(1) DB DGV DW N NS PW UNIT (SSOP) (TVSOP) (SOIC) (PDIP) (PDIP) (TSSOP) 20PINS 20PINS 20PINS 20PINS 20PINS 20PINS R Junction-to-ambientthermalresistance 99.9 119.2 83.0 54.9 80.4 105.4 °C/W θJA R Junction-to-case(top)thermalresistance 61.7 34.5 48.9 41.7 46.9 39.5 °C/W θJC(top) R Junction-to-boardthermalresistance 55.2 60.7 50.5 35.8 47.9 56.4 °C/W θJB Junction-to-topcharacterization ψ 22.6 1.2 21.1 27.9 19.9 3.1 °C/W JT parameter Junction-to-boardcharacterization ψ 54.8 60.0 50.1 35.7 47.5 55.8 °C/W JB parameter (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report(SPRA953). 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto125°C T =25°C SN54AHC540 SN74AHC540 PARAMETER TESTCONDITIONS V A SN74AHC540 UNIT CC MIN TYP MAX MIN MAX MIN MAX MIN MAX 2V 1.9 2 1.9 1.9 1.9 I =–50µA 3V 2.9 3 2.9 2.9 2.9 OH V 4.5V 4.4 4.5 4.4 4.4 4.4 V OH I =–4mA 3V 2.58 2.48 2.48 2.48 OH I =–8mA 4.5V 3.94 3.8 3.8 3.8 OH 2V 0.1 0.1 0.1 0.1 I =50µA 3V 0.1 0.1 0.1 0.1 OL V 4.5V 0.1 0.1 0.1 0.1 V OL I =4mA 3V 0.36 0.5 0.44 0.44 OH I =8mA 4.5V 0.36 0.5 0.44 0.44 OH I V =5.5VorGND 0Vto5.5 ±0.1 ±1(1) ±1 ±1 µA I I V I (2) VO=VCCorGND 5.5V ±0.2 ±2.5 ±2.5 ±2.5 µA OZ V (OE)=V orV 5 I IL IH V =V or I = I I CC O 5.5V 4 40 40 40 µA CC GND 0 C V =V orGND 5V 2 10 10 pF i I CC C V =V orGND 5V 4 pF O O CC (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontestedatV =0V. CC (2) Forinputandoutputpins,I includestheinputleakagecurrent. OZ 6 SubmitDocumentationFeedback Copyright©1995–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 www.ti.com SCLS260M–DECEMBER1995–REVISEDMAY2016 6.6 Switching Characteristics, V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) PARAMETER FROM TO LOAD TA=25°C SN54AHC540 SN74AHC540 TA=SN–4704°ACHtCo514205°C UNIT (INPUT) (OUTPUT) CAPACITANCE TYP MAX MIN MAX MIN MAX MIN MAX tPLH 4.8(1) 7(1) 1(1) 8.5(1) 1 8.5 1 9.5 tPHL A Y CL=15pF 4.8(1) 7(1) 1(1) 8.5(1) 1 8.5 1 9.5 ns tPZH 6.8(1) 10.5(1) 1(1) 12.5(1) 1 12.5 1 13.5 tPZL OE Y CL=15pF 6.8(1) 10.5(1) 1(1) 12.5(1) 1 12.5 1 13.5 ns tPHZ 6.8(1) 10.5(1) 1(1) 12.5(1) 1 12.5 1 13.5 tPLZ OE Y CL=15pF 6.8(1) 10.5(1) 1(1) 12.5(1) 1 12.5 1 13.5 ns tPLH 7.3 10.5 1 12 1 12 1 13.5 A Y CL=50pF ns tPHL 7.3 10.5 1 12 1 12 1 13.5 tPZH 8 14 1 16 1 16 1 17 OE Y CL=50pF ns tPZL 8 14 1 16 1 16 1 17 tPHZ 8 15.4 1 17.5 1 17.5 1 18.5 OE Y CL=50pF ns tPLZ 8 15.4 1 17.5 1 17.5 1 18.5 tsk(o) CL=50pF 1.5(2) 1.5 ns (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. 6.7 Switching Characteristics, V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) PARAMETER FROM TO LOAD TA=25°C SN54AHC540 SN74AHC540 TA=SN–4704°ACHtCo514205°C UNIT (INPUT) (OUTPUT) CAPACITANCE TYP MAX MIN MAX MIN MAX MIN MAX tPLH 3.7(1) 5(1) 1(1) 6(1) 1 6 1 7 tPHL A Y CL=15pF 3.7(1) 5(1) 1(1) 6(1) 1 6 1 7 ns tPZH 4.7(1) 7.2(1) 1(1) 8.5(1) 1 8.5 1 9.5 tPZL OE Y CL=15pF 4.7(1) 7.2(1) 1(1) 8.5(1) 1 8.5 1 9.5 ns tPHZ 4.5(1) 6.8(1) 1(1) 8(1) 1 8 1 8.5 tPLZ OE Y CL=15pF 4.5(1) 6.8(1) 1(1) 8(1) 1 8 1 8.5 ns tPLH 5.2 7 1 8 1 8 1 9 A Y CL=50pF ns tPHL 5.2 7 1 8 1 8 1 9 tPZH 6.2 9.2 1 10.5 1 10.5 1 11.5 OE Y CL=50pF ns tPZL 6.2 9.2 1 10.5 1 10.5 1 11.5 tPHZ 6 8.8 1 10 1 10 1 10.5 OE Y CL=50pF ns tPLZ 6 8.8 1 10 1 10 1 10.5 tsk(o) CL=50pF 1(2) 1 ns (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. Copyright©1995–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 www.ti.com 6.8 Noise Characteristics V =5V,C =50pF,T =25°C(1) CC L A SN74AHC540 PARAMETER UNIT MIN MAX V Quietoutput,maximumdynamicV 0.8 V OL(P) OL V Quietoutput,minimumdynamicV –0.8 V OL(V) OL V Quietoutput,minimumdynamicV 4.7 V OH(V) OH V High-leveldynamicinputvoltage 3.5 V IH(D) V Low-leveldynamicinputvoltage 1.5 V IL(D) (1) Characteristicsareforsurface-mountpackagesonly. 6.9 Operating Characteristics V =5V,T =25°C CC A PARAMETER TESTCONDITIONS TYP UNIT C Powerdissipationcapacitance Noload, f=1MHz 12 pF pd 6.10 Typical Characteristics 9 5 TPD in ns 8 7 4 6 ns) 5 ns) 3 D ( D ( P 4 P T T 2 3 2 1 1 TPD in ns 0 0 0 1 2 3 4 5 6 -100 -50 0 50 100 150 VCC (V) D001 Temperature qC D001 Figure1.TPDvsV Figure2.TPDvsTemperature CC 8 SubmitDocumentationFeedback Copyright©1995–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 www.ti.com SCLS260M–DECEMBER1995–REVISEDMAY2016 7 Parameter Measurement Information VCC FromOutput Test FromOutput RL=1kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (seeNoteA) (seeNoteA) tPHZ/tPZH GND OpenDrain VCC LOADCIRCUITFOR LOADCIRCUITFOR TOTEM-POLEOUTPUTS 3-STATEANDOPEN-DRAINOUTPUTS VCC TimingInput 50%VCC tw th 0V VCC tsu VCC Input 50%VCC 50%VCC DataInput 50%VCC 50%VCC 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPANDHOLDTIMES VCC VCC Output Input 50%VCC 50%VCC Control 50%VCC 50%VCC 0V 0V tPLH tPHL tPZL tPLZ Output VOH Waveform1 ≈VCC InO-Puhtapsuet 50%VCC 50%VCC S1atVCC 50%VCC VOL+0.3V VOL (seeNoteB) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50%VCC 50%VCVVCOOHL (WseSae1veNaftooGtremNBD2) 50%VCC VOH–0.3VV≈0OVH VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEANDDISABLETIMES INVERTINGANDNONINVERTINGOUTPUTS LOW-ANDHIGH-LEVELENABLING NOTES: A. CLincludesprobeandjigcapacitance. B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislowexceptwhendisabledbytheoutputcontrol. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishighexceptwhendisabledbytheoutputcontrol. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,ZO=50Ω,tr≤3ns,tf≤3ns. D. Theoutputsaremeasuredoneatatimewithoneinputtransitionpermeasurement. E. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms Copyright©1995–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 www.ti.com 8 Detailed Description 8.1 Overview The SNx4AHC540 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These devicesfeatureinputsandoutputsonoppositesidesofthepackagetofacilitateprintedcircuitboardlayout. The 3-state control gate is a two-input AND gate with active-low inputs. If either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data when theyarenotinthehigh-impedancestate. OE should be tied to V through a pullup resistor to ensure the high-impedance state during power up or power CC down.Theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. 8.2 Functional Block Diagram OE1 OE2 A1 Y1 ToSevenOtherChannels 8.3 Feature Description SNx4AHC540 device has a wide operating voltage range and operates from 2 V to 5.5 V. The inputs accept voltages up to 5.5 V, which allows for down translation. Slow input edges and low drive will minimize output overshootsandundershoots. 8.4 Device Functional Modes Table1showsthedevicefunctionsforeachbufferanddriver. Table1.FunctionTable(EachBuffer/Driver) INPUTS OUTPUT OE1 OE2 A Y L L L H L L H L H X X Hi-Z X H X Hi-Z 10 SubmitDocumentationFeedback Copyright©1995–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 www.ti.com SCLS260M–DECEMBER1995–REVISEDMAY2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information TheSN74AHC540isalowdriveCMOSdevicethatcanbeusedforamultitudeofbusinterfacetypeapplications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs accept voltages up to 5.5 V, which allows down translation to the V level. Figure 5 CC showshowthesloweredgescanreduceringingontheoutputcomparedtohigherdrivepartslikeAC. 9.2 Typical Application Regulated 5.0 V OE VCC A1 Y1 µC or System Logic 5-V µC A8 Y8 System logic LEDs GND Figure4. TypicalApplicationSchematic 9.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloadssoroutingandloadconditionsshouldbeconsideredtopreventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions: – Forrisetimeandfalltimespecifications,see Δt/ΔVintheRecommendedOperatingConditions table. – Forspecifiedhighandlowlevels,seeV andV intheRecommendedOperatingConditionstable. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV CC. 2. RecommendedOutputConditions: – Loadcurrentsshouldnotexceed25mAperoutputand75mAtotalforthepart. – OutputsshouldnotbepulledaboveV CC. Copyright©1995–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 SCLS260M–DECEMBER1995–REVISEDMAY2016 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurve Figure5.SwitchingCharacteristicsComparison 10 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each V terminal should have a good bypass capacitor to prevent CC power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple V terminals CC then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitorshouldbeinstalledasclosetothepowerterminalaspossibleforbestresults. 10.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates.SpecifiedintheFigure6 are rulesthatmustbeobservedunderallcircumstances.Allunusedinputsofdigitallogicdevicesmustbeconnected toahighorlowbiastopreventthemfromfloating.Thelogiclevelthatshouldbeappliedtoanyparticularunused input depends on the function of the device. Generally they will be tied to GND or V , whichever makes more CC sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the inputsectionoftheI/Ossotheyalsocannotfloatwhendisabled. 11 Layout 11.1 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram 12 SubmitDocumentationFeedback Copyright©1995–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC540 SN74AHC540

SN54AHC540,SN74AHC540 www.ti.com SCLS260M–DECEMBER1995–REVISEDMAY2016 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54AHC540 Clickhere Clickhere Clickhere Clickhere Clickhere SN74AHC540 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1995–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54AHC540 SN74AHC540

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9685001Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9685001Q2A SNJ54AHC 540FK 5962-9685001QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685001QS A SNJ54AHC540W SN74AHC540DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA540 & no Sb/Br) SN74AHC540DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA540 & no Sb/Br) SN74AHC540DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC540 & no Sb/Br) SN74AHC540DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC540 & no Sb/Br) SN74AHC540N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74AHC540N (RoHS) SN74AHC540PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA540 & no Sb/Br) SN74AHC540PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA540 & no Sb/Br) SN74AHC540PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA540 & no Sb/Br) SNJ54AHC540FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9685001Q2A SNJ54AHC 540FK SNJ54AHC540W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9685001QS A SNJ54AHC540W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AHC540, SN74AHC540 : •Catalog: SN74AHC540 •Military: SN54AHC540 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Jan-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHC540DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AHC540DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHC540DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74AHC540PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Jan-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHC540DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AHC540DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74AHC540DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AHC540PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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