(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12) (cid:10)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:11)(cid:19)(cid:2)(cid:16)(cid:13)(cid:20) (cid:16)(cid:21)(cid:1)(cid:19)(cid:20)(cid:19)(cid:22)(cid:18)(cid:11)(cid:21)(cid:15) (cid:23)(cid:5)(cid:20)(cid:18) SGDS019A − FEBRUARY 2002 − REVISED APRIL 2008 (cid:1) Qualified for Automotive Applications D OR PW PACKAGE (cid:1) EPIC (Enhanced-Performance Implanted (TOP VIEW) CMOS) Process (cid:1) 1A 1 14 VCC Operating Range 2-V to 5.5-V VCC 1B 2 13 4B (cid:1) Latch-Up Performance Exceeds 250 mA Per 1Y 3 12 4A JESD 17 2A 4 11 4Y (cid:1) ESD Protection Exceeds 2000 V Per 2B 5 10 3B MIL-STD-883, Method 3015; Exceeds 200 V 2Y 6 9 3A Using Machine Model (C = 200 pF, R = 0) GND 7 8 3Y description The SN74AHC32Q is a quadruple 2-input positive-OR gate. This device performs the Boolean function Y(cid:1)A•BorY(cid:1)A(cid:2)B in positive logic. (cid:1) ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE‡ PART NUMBER MARKING SOIC − D Tape and reel SN74AHC32QDRQ1 AHC32Q −−4400°°CC ttoo 112255°°CC TSSOP − PW Tape and reel SN74AHC32QPWRQ1 HA32Q †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each gate) INPUTS OOUUTTPPUUTT A B Y H X H X H H L L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. (cid:16)(cid:15)(cid:21)(cid:14)(cid:13)(cid:7)(cid:20)(cid:19)(cid:21)(cid:2) (cid:14)(cid:5)(cid:20)(cid:5) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2008, Texas Instruments Incorporated (cid:16)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:20)$+(cid:30)! (cid:19)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:16)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12) (cid:10)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:11)(cid:19)(cid:2)(cid:16)(cid:13)(cid:20) (cid:16)(cid:21)(cid:1)(cid:19)(cid:20)(cid:19)(cid:22)(cid:18)(cid:11)(cid:21)(cid:15) (cid:23)(cid:5)(cid:20)(cid:18) SGDS019A − FEBRUARY 2002 − REVISED APRIL 2008 logic symbol† 1 1A ≥1 3 2 1Y 1B 4 2A 6 5 2Y 2B 9 3A 8 10 3Y 3B 12 4A 11 13 4Y 4B †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to7 V I Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V toV + 0.5 V O CC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W JA PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12) (cid:10)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:11)(cid:19)(cid:2)(cid:16)(cid:13)(cid:20) (cid:16)(cid:21)(cid:1)(cid:19)(cid:20)(cid:19)(cid:22)(cid:18)(cid:11)(cid:21)(cid:15) (cid:23)(cid:5)(cid:20)(cid:18) SGDS019A − FEBRUARY 2002 − REVISED APRIL 2008 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2 5.5 V VCC = 2 V 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 3 V 2.1 VV VCC = 5.5 V 3.85 VCC = 2 V 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 3 V 0.9 VV VCC = 5.5 V 1.65 VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 2 V −50 (cid:1)A IIOOHH HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt VCC = 3.3 V ± 0.3 V −4 mmAA VCC = 5 V ± 0.5 V −8 VCC = 2 V 50 (cid:1)A IIOOLL LLooww--lleevveell oouuttppuutt ccuurrrreenntt VCC = 3.3 V ± 0.3 V 4 mmAA VCC = 5 V ± 0.5 V 8 VCC = 3.3 V ± 0.3 V 100 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee oorr ffaallll rraattee nnss//VV VCC = 5 V ± 0.5 V 20 TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC MMIINN MMAAXX UUNNIITT MIN TYP MAX 2 V 1.9 2 1.9 IIOOHH == −−5500 (cid:1)(cid:1)AA 3 V 2.9 3 2.9 VVOOHH 4.5 V 4.4 4.5 4.4 VV IOH = −4 mA 3 V 2.58 2.48 IOH = −8 mA 4.5 V 3.94 3.8 2 V 0.1 0.1 IIOOLL == 5500 (cid:1)(cid:1)AA 3 V 0.1 0.1 VVOOLL 4.5 V 0.1 0.1 VV IOL = 4 mA 3 V 0.36 0.5 IOL = 8 mA 4.5 V 0.36 0.5 II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 (cid:1)A ICC VI = VCC or GND, IO = 0 5.5 V 2 20 (cid:1)A Ci VI = VCC or GND 5 V 2 10 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12) (cid:10)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:11)(cid:19)(cid:2)(cid:16)(cid:13)(cid:20) (cid:16)(cid:21)(cid:1)(cid:19)(cid:20)(cid:19)(cid:22)(cid:18)(cid:11)(cid:21)(cid:15) (cid:23)(cid:5)(cid:20)(cid:18) SGDS019A − FEBRUARY 2002 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1) FFRROOMM TTOO LLOOAADD TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX tPLH 5.5 7.9 1 9.5 AA oorr BB YY CCLL == 1155 ppFF nnss tPHL 5.5 7.9 1 9.5 tPLH 8 11.4 1 13 AA oorr BB YY CCLL == 5500 ppFF nnss tPHL 8 11.4 1 13 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1) FFRROOMM TTOO LLOOAADD TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX tPLH 3.8 5.5 1 6.5 AA oorr BB YY CCLL == 1155 ppFF nnss tPHL 3.8 5.5 1 6.5 tPLH 5.3 7.5 1 8.5 AA oorr BB YY CCLL == 5500 ppFF nnss tPHL 5.3 7.5 1 8.5 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.3 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.7 V VIH(D) High-level dynamic input voltage 3.5 V VIL(D) Low-level dynamic input voltage 1.5 V NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 14 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12) (cid:10)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:11)(cid:19)(cid:2)(cid:16)(cid:13)(cid:20) (cid:16)(cid:21)(cid:1)(cid:19)(cid:20)(cid:19)(cid:22)(cid:18)(cid:11)(cid:21)(cid:15) (cid:23)(cid:5)(cid:20)(cid:18) SGDS019A − FEBRUARY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw th 0 V VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC VCC Output Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 ≈VCC InO-Puhtapsuet 50% VCC 50% VCC S1 at VCC 50% VCC VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH − 0.3 VV≈0O VH VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AHC32QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC32Q & no Sb/Br) SN74AHC32QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC32Q & no Sb/Br) SN74AHC32QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA32Q & no Sb/Br) SN74AHC32QPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA32Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHC32QPWRG4Q1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHC32QPWRQ1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHC32QPWRG4Q1 TSSOP PW 14 2000 367.0 367.0 35.0 SN74AHC32QPWRQ1 TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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