Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 SNx4AHC273 Octal D-Type Flip-Flops With Clear 1 Features 3 Description • OperatingRange2-Vto5.5-VV These devices are positive-edge-triggered D-type 1 CC flip-flopswithadirectclear(CLR)input. • ContainEightFlip-FlopsWithSingle-RailOutputs Information at the data (D) inputs meeting the setup • DirectClearInput time requirements is transferred to the Q outputs on • IndividualDataInputtoEachFlip-Flop the positive-going edge of the clock (CLK) pulse. • Latch-UpPerformanceExceeds250mAPer Clock triggering occurs at a particular voltage level JESD17 and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high • ESDProtectionExceedsJESD22 orlowlevel,theDinputhasnoeffectattheoutput. – 2000-VHuman-BodyModel(A114-A) – 1000-VCharged-DeviceModel(C101) DeviceInformation(1) • OnProductsComplianttoMIL-PRF-38535, PARTNUMBER PACKAGE BODYSIZE(NOM) AllParametersAreTestedUnlessOtherwise PDIP(20) 24.33mm×6.35mm Noted.OnAllOtherProducts,Production SSOP(20) 7.20mm×5.30mm ProcessingDoesNotNecessarilyIncludeTesting SNx4AHC273 TSSOP(20) 6.50mm×4.40mm ofAllParameters. TVSOP(20) 5.00mm×4.40mm 2 Applications SOIC(20) 12.80mm×7.50mm (1) For all available packages, see the orderable addendum at • BuffersandStorageRegisters theendofthedatasheet. • ShiftRegisters • PatternGenerators • Servers • PCsandNotebooks • NetworkSwitches • MemorySystems • Databases 4 Simplified Schematics 1D 2D 3D 4D 5D 6D 7D 8D 3 4 7 8 13 14 17 18 11 CLK 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 R R R R R R R R 1 CLR 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C C D TG TG Q C C C C TG CLK(I) C TG C C C R 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ParameterMeasurementInformation..................8 2 Applications........................................................... 1 9 DetailedDescription.............................................. 9 3 Description............................................................. 1 9.1 Overview...................................................................9 4 SimplifiedSchematics........................................... 1 9.2 FunctionalBlockDiagrams.......................................9 5 RevisionHistory..................................................... 2 9.3 FeatureDescription.................................................10 9.4 DeviceFunctionalModes........................................10 6 PinConfigurationandFunctions......................... 3 10 ApplicationandImplementation........................ 11 7 Specifications......................................................... 4 10.1 ApplicationInformation..........................................11 7.1 AbsoluteMaximumRatings......................................4 10.2 TypicalApplication................................................11 7.2 HandlingRatings.......................................................4 11 PowerSupplyRecommendations..................... 12 7.3 RecommendedOperatingConditions.......................4 7.4 ThermalInformation..................................................5 12 Layout................................................................... 12 7.5 ElectricalCharacteristics...........................................5 12.1 LayoutGuidelines.................................................12 7.6 TimingRequirements,V =3.3V±0.3V..............5 12.2 LayoutExample....................................................12 CC 7.7 TimingRequirements,V =5V±0.5V.................6 13 DeviceandDocumentationSupport................. 13 CC 7.8 SwitchingCharacteristics,V =3.3V±0.3V........6 13.1 RelatedLinks........................................................13 CC 7.9 SwitchingCharacteristics,V =5V±0.5V...........6 13.2 Trademarks...........................................................13 CC 7.10 NoiseCharacteristics..............................................7 13.3 ElectrostaticDischargeCaution............................13 7.11 OperatingCharacteristics........................................7 13.4 Glossary................................................................13 7.12 TypicalCharacteristics............................................7 14 Mechanical,Packaging,andOrderable Information........................................................... 13 5 Revision History ChangesfromRevisionH(July2014)toRevisionI Page • ChangedI testconditionsforV frommAtoµAtofixtypographicalerror. ..................................................................... 5 OH OH ChangesfromRevisionG(June1997)toRevisionH Page • UpdateddocumenttonewTIdatasheetstandards.............................................................................................................. 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 • AddedMilitaryDisclaimertoFeatureslist.............................................................................................................................. 1 • AddedApplications................................................................................................................................................................. 1 • AddedHandlingRatingstable................................................................................................................................................ 4 • ChangedMAXoperatingtemperaturefrom85°Cto125°CinRecommendedOperatingConditionstable. ........................4 • AddedThermalInformationtable........................................................................................................................................... 5 • AddedTypicalCharacteristics................................................................................................................................................ 7 • AddedDetailedDescriptionsection........................................................................................................................................ 9 • AddedApplicationandImplementationsection.................................................................................................................... 11 2 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 www.ti.com SCLS376I–JUNE1997–REVISEDMARCH2015 6 Pin Configuration and Functions SN54AHC273...JORWPACKAGE SN54AHC273...FKPACKAGE SN74AHC273...DB,DGV,DW,N,NS,ORPWPACKAGE (TOPVIEW) (TOPVIEW) R C DQ L CQ CLR 1 20 VCC 11 CV 8 1Q 2 19 8Q 3 2 1 20 19 1D 3 18 8D 2D 4 18 8D 2D 4 17 7D 2Q 5 17 7D 3Q 6 16 7Q 2Q 5 16 7Q 3D 7 15 6Q 3Q 6 15 6Q 4D 8 14 6D 3D 7 14 6D 9 10 11 12 13 4D 8 13 5D 4Q 9 12 5Q Q D K Q D 4 N L 5 5 GND 10 11 CLK G C PinFunctions PIN I/O DESCRIPTION NO. NAME 1 CLR I ClearPin 2 1Q O 1QOutput 3 1D I 1DInput 4 2D I 2DInput 5 2Q O 2QOutput 6 3Q O 3QOutput 7 3D I 3DInput 8 4D I 4DInput 9 4Q O 4QOutput 10 GND — GroundPin 11 CLK I ClockPin 12 5Q O 5QOutput 13 5D I 5DInput 14 6D I 6DInput 15 6Q O 6QOutput 16 7Q O 7QOutput 17 7D I 7DInput 18 8D I 8DInput 19 8Q O 8QOutput 20 VCC — PowerPin Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 7 V CC V Inputvoltagerange(2) –0.5 7 V I V Outputvoltagerange(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0orV >V ±20 mA OK O O CC I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±75 mA CC (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) SN54AHC273 SN74AHC273 UNIT MIN MAX MIN MAX V Supplyvoltage 2 5.5 2 5.5 V CC V =2V 1.5 1.5 CC V High-levelinputvoltage V =3V 2.1 2.1 V IH CC V =5.5V 3.85 3.85 CC V =2V 0.5 0.5 CC V Low-levelinputvoltage V =3V 0.9 0.9 V IL CC V =5.5V 1.65 1.65 CC V Inputvoltage 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V V O CC CC V =2V –50 –50 µA CC I High-leveloutputcurrent V =3V±0.3V –4 –4 OH CC mA V =5.5V±0.5V –8 –8 CC V =2V 50 50 µA CC I Low-leveloutputcurrent V =3V±0.3V 4 4 OL CC mA V =5.5V±0.5V 8 8 CC V =3V±0.3V 100 100 CC ∆t/∆v Inputtransitionriseandfalltime ns/V V =5.5V±0.5V 20 20 CC T Operatingfree-airtemperature –55 125 –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,(SCBA004). 4 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 www.ti.com SCLS376I–JUNE1997–REVISEDMARCH2015 7.4 Thermal Information SN74AHC273 THERMALMETRIC(1) N DW NS DB PW DGV UNIT 20PINS R Junction-to-ambientthermalresistance 53.9 81.8 79.4 98.7 104.7 118.1 θJA Junction-to-case(top)thermal R 38.8 47.8 45.9 60.4 38.8 33.4 θJC(top) resistance R Junction-to-boardthermalresistance 34.7 49.4 46.9 56.9 55.7 59.6 θJB ψ Junction-to-topcharacterization 26.9 20.1 19.1 21.6 2.9 1.1 °C/W JT parameter Junction-to-boardcharacterization ψ 34.7 49.0 46.5 53.5 55.1 58.9 JB parameter Junction-to-case(bottom)thermal R n/a n/a n/a n/a n/a n/a θJC(bot) resistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheTIapplicationreportICPackageThermalMetrics(SPRA953). 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) T =25°C SN54AHC273 SN74AHC273 A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP MAX MIN MAX MIN MAX 2V 1.9 1.9 1.9 I =–50µA 3V 2.9 2.9 2.9 OH V 4.5V 4.4 4.4 4.4 V OH I =–4mA 3V 2.58 2.48 2.48 OH I =–8mA 4.5V 3.94 3.8 3.8 OH 2V 0.1 0.1 0.1 I =50µA 3V 0.1 0.1 0.1 OL V 4.5V 0.1 0.1 0.1 V OL I =4mA 3V 0.36 0.5 0.44 OL I =8mA 4.5V 0.36 0.5 0.44 OL I V =5.5VorGND 0to5.5 ±0.1 ±1(1) ±1 µA I I V I V =V orGND I =0 5.5V 4 40 40 µA CC I CC O C V =V orGND 5V 2.5 10 10 pF i I CC (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontestedatV =0V. CC 7.6 Timing Requirements, V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54AHC273 SN74AHC273 T =25°C T =25°C UNIT A A MIN MAX MIN MAX MIN MAX MIN MAX CLRlow 5 6 5 6 t PulseDuration ns w CLKhighorlow 5 6.5 5 6.5 DatabeforeCLK↑ 5.5 6.5 5.5 6.5 t Setuptime ns su CLRbeforeCLK↑ 2.5 2.5 2.5 2.5 t Holdtime,dataafterCLK↑ 1.5 2 1 1 ns h Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 www.ti.com 7.7 Timing Requirements, V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54AHC273 SN74AHC273 T =25°C T =25°C UNIT A A MIN MAX MIN MAX MIN MAX MIN MAX CLRlow 5 5 5 5 t PulseDuration ns w CLKhighorlow 5 5 5 5 DatabeforeCLK↑ 4.5 4.5 4.5 4.5 t Setuptime ns su CLRbeforeCLK↑ 2 2 2 2 t Holdtime,dataafterCLK↑ 1.5 2 1 1 ns h 7.8 Switching Characteristics, V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) FROM TO LOAD TA=25°C SN54AHC273 SN74AHC273 PARAMETER UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX C =15pF 75(1) 120(1) 65(1) 65 L f MHz max C =50pF 50 75 45 45 L t CLR Q C =15pF 8.9(1) 13.6(1) 1(1) 16(1) 1 16 PHL L ns t 8.7(1) 13.6(1) 1(1) 16(1) 1 16 PLH CKL Q C =15pF t L 8.7(1) 13.6(1) 1(1) 16(1) 1 16 PHL ns t CLR Q C =50pF 11.4 17.1 1 19.5 1 19.5 PHL L t 11.2 17.1 1 19.5 1 19.5 ns PLH CLK Q C =50pF L t 11.2 17.1 1 19.5 1 19.5 ns PHL t C =50pF 1.5(2) 1.5 ns sk(o) L (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. 7.9 Switching Characteristics, V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) FROM TO LOAD TA=25°C SN54AHC273 SN74AHC273 PARAMETER UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX C =15pF 120(1) 165(1) 100(1) 100 L f MHz max C =50pF 80 110 70 70 L t CLR Q C =15pF 5.2(1) 8.5(1) 1(1) 10(1) 1 10 PHL L ns t 5.8(1) 9(1) 1(1) 10.5(1) 1 10.5 PLH CKL Q C =15pF t L 5.8(1) 9(1) 1(1) 10.5(1) 1 10.5 PHL ns t CLR Q C =50pF 6.7 10.5 1 12 1 12 PHL L t 7.3 11 1 12.5 1 12.5 ns PLH CLK Q C =50pF L t 7.3 11 1 12.5 1 12.5 ns PHL t C =50pF 1(2) 1 ns sk(o) L (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) OnproductscomplianttoMIL-PRF-38535,thisparameterdoesnotapply. 6 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 www.ti.com SCLS376I–JUNE1997–REVISEDMARCH2015 7.10 Noise Characteristics(1) V =5V,C =50pF,T =25°C CC L A SN74AHC273 PARAMETER UNIT MIN TYP MAX V Quietoutput,maximumdynamicV 0.7 V OL(P) OL V Quietoutput,minimumdynamicV –0.7 V OL(V) OL V Quietoutput,minimumdynamicV 4.7 V OH(V) OH V High-leveldynamicinputvoltage 3.5 V IH(D) V Low-leveldynamicinputvoltage 1.5 V IL(D) (1) Characteristicsareforsurface-mountpackagesonly. 7.11 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS TYP UNIT C Powerdissipationcapacitance Noload, f=1MHz 31 pF pd 7.12 Typical Characteristics 14 9.4 TPD in ns 12 9.2 9 10 8.8 s) 8 s) n n D ( D ( 8.6 P 6 P T T 8.4 4 8.2 2 8 TPD in ns 0 7.8 0 1 2 3 4 5 6 -100 -50 0 50 100 150 VCC (V) D001 Temperature (qC) D002 Figure1.TPDvsV Figure2.TPDvsTemperature CC Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 www.ti.com 8 Parameter Measurement Information VCC FromOutput Test FromOutput RL=1kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (seeNoteA) (seeNoteA) tPHZ/tPZH GND OpenDrain VCC LOADCIRCUITFOR LOADCIRCUITFOR TOTEM-POLEOUTPUTS 3-STATEANDOPEN-DRAINOUTPUTS VCC TimingInput 50%VCC tw th 0V VCC tsu VCC Input 50%VCC 50%VCC DataInput 50%VCC 50%VCC 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPANDHOLDTIMES VCC VCC Output Input 50%VCC 50%VCC Control 50%VCC 50%VCC 0V 0V tPLH tPHL tPZL tPLZ Output VOH Waveform1 ≈VCC InO-Puhtapsuet 50%VCC 50%VCC S1atVCC 50%VCC VOL+0.3V VOL (seeNoteB) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50%VCC 50%VCVVCOOHL (WseSae1veNaftooGtremNBD2) 50%VCC VOH–0.3VV≈0OVH VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEANDDISABLETIMES INVERTINGANDNONINVERTINGOUTPUTS LOW-ANDHIGH-LEVELENABLING NOTES: A. CLincludesprobeandjigcapacitance. B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislowexceptwhendisabledbytheoutputcontrol. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishighexceptwhendisabledbytheoutputcontrol. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,ZO=50Ω,tr≤3ns,tf≤3ns. D. Theoutputsaremeasuredoneatatimewithoneinputtransitionpermeasurement. E. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 www.ti.com SCLS376I–JUNE1997–REVISEDMARCH2015 9 Detailed Description 9.1 Overview These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The inputs are 5 V tolerant and can be driven from 5-V devices. This feature allows the use of these devices as downtranslatorsinamixed5-Vto3.3-Vsystemenvironment. 9.2 Functional Block Diagrams 1D 2D 3D 4D 5D 6D 7D 8D 3 4 7 8 13 14 17 18 11 CLK 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 R R R R R R R R 1 CLR 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C C D TG TG Q C C C C TG CLK(I) C TG C C C R Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 www.ti.com 9.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom2Vto5.5V • Allowsdownvoltagetranslation – Inputsacceptvoltagesto5.5V • Slowedgeratesminimizeoutputringing 9.4 Device Functional Modes Table1.FunctionTable INPUTS OUTPUT CLR CLK D Y L X X L H ↑ H H H ↑ L L H L X Q 0 10 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 www.ti.com SCLS376I–JUNE1997–REVISEDMARCH2015 10 Application and Implementation 10.1 Application Information The SNx4AHC273 is a low-drive CMOS device that can be used for a multitude of applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs are tolerant to 5.5 V at any valid V . This feature makes the device ideal for translating down to the CC V level.Figure5showsthereductioninringingcomparedtohigherdrivepartssuchasAC. CC 10.2 Typical Application Regulated 3.3 V CLR VCC CLK 1Q 1D 5 V System Logic µC or 8Q 8D System Logic GND Figure4. SpecificApplicationSchematic 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads,soroutingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. Recommendedinputconditions – Risetimeandfalltimespecs:See(Δt/ΔV)intheRecommendedOperatingConditionstable. – SpecifiedHighandlowlevels:See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV CC 2. Recommendoutputconditions – Loadcurrentsshouldnotexceed25mAperoutputand75mAtotalforthepart – OutputsshouldnotbepulledaboveV CC Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 SCLS376I–JUNE1997–REVISEDMARCH2015 www.ti.com Typical Application (continued) 10.2.3 ApplicationCurves Figure5.SwitchingCharacteristicsComparison 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each powerpin.Itisacceptabletoparallelmultiplebypasscapstorejectdifferentfrequenciesofnoise.A0.1 μFand1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsshouldnoteverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 6 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally inputs will be tied to GND or V , whichever makes more sense or is more convenient. It is generally acceptable to float CC outputsunlessthepartisatransceiver. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram 12 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54AHC273 SN74AHC273

SN54AHC273,SN74AHC273 www.ti.com SCLS376I–JUNE1997–REVISEDMARCH2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54AHC273 Clickhere Clickhere Clickhere Clickhere Clickhere SN74AHC273 Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54AHC273 SN74AHC273

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9853001Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9853001Q2A SNJ54AHC 273FK 5962-9853001QRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9853001QR A SNJ54AHC273J 5962-9853001QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9853001QS A SNJ54AHC273W SN74AHC273DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA273 & no Sb/Br) SN74AHC273DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA273 & no Sb/Br) SN74AHC273DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC273 & no Sb/Br) SN74AHC273DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC273 & no Sb/Br) SN74AHC273N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74AHC273N (RoHS) SN74AHC273NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AHC273 & no Sb/Br) SN74AHC273PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA273 & no Sb/Br) SN74AHC273PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HA273 & no Sb/Br) SNJ54AHC273FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9853001Q2A SNJ54AHC 273FK SNJ54AHC273J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9853001QR A SNJ54AHC273J SNJ54AHC273W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9853001QS A Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SNJ54AHC273W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AHC273, SN74AHC273 : •Catalog: SN74AHC273 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Military: SN54AHC273 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHC273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AHC273DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHC273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74AHC273NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74AHC273PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHC273DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AHC273DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74AHC273DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AHC273NSR SO NS 20 2000 367.0 367.0 45.0 SN74AHC273PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

None

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

None

None

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated