SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 (cid:2) (cid:2) Operating Range 2-V to 5.5-V V Latch-Up Performance Exceeds 250 mA Per CC (cid:2) Designed Specifically for High-Speed JESD 17 (cid:2) Memory Decoders and Data-Transmission ESD Protection Exceeds JESD 22 Systems − 2000-V Human-Body Model (A114-A) (cid:2) Incorporate Three Enable Inputs to Simplify − 200-V Machine Model (A115-A) Cascading and/or Data Reception − 1000-V Charged-Device Model (C101) SN54AHC138...J OR W PACKAGE SN74AHC138...RGY PACKAGE SN54AHC138...FK PACKAGE SN74AHC138...D, DB, DGV, N, NS, (TOP VIEW) (TOP VIEW) OR PW PACKAGE C C (TOP VIEW) C C C0 A V BA N V Y A 1 16 VCC 1 16 3 2 1 20 19 B 2 15 Y0 B 2 15 Y0 C 4 18 Y1 C 3 14 Y1 C 3 14 Y1 G2A 5 17 Y2 G2A 4 13 Y2 G2A 4 13 Y2 NC 6 16 NC G2B 5 12 Y3 G2B 5 12 Y3 G2B 7 15 Y3 G1 6 11 Y4 G1 6 11 Y4 G1 8 14 Y4 9 10 1112 13 Y7 7 10 Y5 Y7 7 10 Y5 GND 8 9 Y6 8 9 7 D C6 5 Y N NY Y ND Y6 G G NC − No internal connection description/ordering information The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Tape and reel SN74AHC138RGYR HA138 PDIP − N Tube SN74AHC138N SN74AHC138N Tube SN74AHC138D SSOOIICC − DD AAHHCC113388 Tape and reel SN74AHC138DR −40°C to 85°C SOP − NS Tape and reel SN74AHC138NSR AHC138 SSOP − DB Tape and reel SN74AHC138DBR HA138 Tube SN74AHC138PW TTSSSSOOPP − PPWW HHAA113388 Tape and reel SN74AHC138PWR TVSOP − DGV Tape and reel SN74AHC138DGVR HA138 CDIP − J Tube SNJ54AHC138J SNJ54AHC138J −5555°CC ttoo 112255°CC CFP − W Tube SNJ54AHC138W SNJ54AHC138W LCCC − FK Tube SNJ54AHC138FK SNJ54AHC138FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 description/ordering information (continued) The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. FUNCTION TABLE ENABLE INPUTS SELECT INPUTS OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic diagram (positive logic) 15 Y0 1 A 14 Y1 13 Y2 Select B 2 Inputs 12 Y3 Data Outputs 11 Y4 3 C 10 Y5 9 Y6 4 G2A 7 Y7 Enable 5 G2B Inputs 6 G1 Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA CC Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) SN54AHC138 SN74AHC138 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2 5.5 2 5.5 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 3 V 2.1 2.1 VV VCC = 5.5 V 3.85 3.85 VCC = 2 V 0.5 0.5 VVIILL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 3 V 0.9 0.9 VV VCC = 5.5 V 1.65 1.65 VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V VCC = 2 V −50 −50 (cid:2)A IIOOHH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3.3 V ± 0.3 V −4 −4 mmAA VCC = 5 V ±0.5 V −8 −8 VCC = 2 V 50 50 (cid:2)A IIOOLL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3.3 V±0.3 V 4 4 mmAA VCC = 5 V ±0.5 V 8 8 VCC = 3.3 V ± 0.3 V 100 100 ΔΔtt//ΔΔvv IInnppuutt ttrraannssiittiioonn rriissee oorr ffaallll rraattee nnss//VV VCC = 5 V ±0.5 V 20 20 TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AHC138 SN74AHC138 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 1.9 2 1.9 1.9 IIOOHH = −5500 (cid:2)(cid:2)AA 3 V 2.9 3 2.9 2.9 VVOOHH 4.5 V 4.4 4.5 4.4 4.4 VV IOH = −4 mA 3 V 2.58 2.48 2.48 IOH = −8 mA 4.5 V 3.94 3.8 3.8 2 V 0.1 0.1 0.1 IIOOLL = 5500 (cid:2)(cid:2)AA 3 V 0.1 0.1 0.1 VVOOLL 4.5 V 0.1 0.1 0.1 VV IOL = 4 mA 3 V 0.36 0.5 0.44 IOL = 8 mA 4.5 V 0.36 0.5 0.44 II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 (cid:2)A ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 (cid:2)A Ci VI = VCC or GND 5 V 2 10 10 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V±0.3 V (unless otherwise noted) (see Figure 1) FFRROOMM TTOO LLOOAADD TA = 25°C SN54AHC138 SN74AHC138 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX tPLH 8.2** 11.4** 1** 13** 1 13 tPHL AA, BB, CC AAnnyy YY CCL = 1155 ppFF 8.2** 11.4** 1** 13** 1 13 nnss tPLH 8.1** 12.8** 1** 15** 1 15 tPHL GG11 AAnnyy YY CCL = 1155 ppFF 8.1** 12.8** 1** 15** 1 15 nnss tPLH 8.2** 11.4** 1** 13.5** 1 13.5 tPHL GG22AA, GG22BB AAnnyy YY CCL = 1155 ppFF 8.2** 11.4** 1** 13.5** 1 13.5 nnss tPLH 10 15.8 1 18 1 18 tPHL AA, BB, CC AAnnyy YY CCL = 5500 ppFF 10 15.8 1 18 1 18 nnss tPLH 10.6 16.3 1 18.5 1 18.5 tPHL GG11 AAnnyy YY CCL = 5500 ppFF 10.6 16.3 1 18.5 1 18.5 nnss tPLH 10.7 14.9 1 17 1 17 GG22AA, GG22BB AAnnyy YY CCL == 5500 ppFF nnss tPHL 10.7 14.9 1 17 1 17 ** On products compliant to MIL-PRF-38535, this parameter is not production tested. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V±0.5 V (unless otherwise noted) (see Figure 1) FFRROOMM TTOO LLOOAADD TA = 25°C SN54AHC138 SN74AHC138 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX tPLH 5.7* 8.1* 1* 9.5* 1 9.5 tPHL AA, BB, CC AAnnyy YY CCL = 1155 ppFF 5.7* 8.1* 1* 9.5* 1 9.5 nnss tPLH 5.6* 8.1* 1* 9.5* 1 9.5 tPHL GG11 AAnnyy YY CCL = 1155 ppFF 5.6* 8.1* 1* 9.5* 1 9.5 nnss tPLH 5.8* 8.1* 1* 9.5* 1 9.5 tPHL GG22AA, GG22BB AAnnyy YY CCL = 1155 ppFF 5.8* 8.1* 1* 9.5* 1 9.5 nnss tPLH 7.2 10.1 1 11.5 1 11.5 tPHL AA, BB, CC AAnnyy YY CCL = 5500 ppFF 7.2 10.1 1 11.5 1 11.5 nnss tPLH 7.1 10.1 1 11.5 1 11.5 tPHL GG11 AAnnyy YY CCL = 5500 ppFF 7.1 10.1 1 11.5 1 11.5 nnss tPLH 7.3 10.1 1 11.5 1 11.5 GG22AA, GG22BB AAnnyy YY CCL == 5500 ppFF nnss tPHL 7.3 10.1 1 11.5 1 11.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 13 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw th 0 V VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC Output VCC Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 ≈VCC InO-Puhtapsuet 50% VCC 50% VCC S1 at VCC 50% VCC VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH − 0.3 V V≈0O HV VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 APPLICATION INFORMATION SN74AHC138 BIN/OCT 15 1 0 0 1 14 2 1 1 2 13 2 2 3 12 4 3 3 6 11 VCC & 4 4 4 10 5 5 EN 5 9 6 6 7 7 7 SN74AHC138 BIN/OCT 15 1 0 8 A0 1 14 2 1 9 A1 2 13 2 10 3 A2 4 12 3 11 6 11 A3 & 4 12 4 10 A4 5 13 EN 5 9 6 14 7 7 15 SN74AHC138 BIN/OCT 15 1 0 16 1 14 2 1 17 2 13 2 18 3 12 4 3 19 6 11 & 4 20 4 10 5 21 EN 5 9 6 22 7 7 23 Figure 2. 24-Bit Decoding Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258L − DECEMBER 1995 − REVISED JULY 2003 APPLICATION INFORMATION SN74AHC138 BIN/OCT 15 1 0 0 A0 1 14 2 1 1 A1 2 13 2 2 3 A2 4 12 3 3 6 11 VCC & 4 4 4 10 A3 5 5 EN 5 9 A4 6 6 7 7 7 SN74AHC138 BIN/OCT 15 1 0 8 1 14 2 1 9 2 13 2 10 3 12 4 3 11 6 11 & 4 12 4 10 5 13 EN 5 9 6 14 7 7 15 SN74AHC138 BIN/OCT 15 1 0 16 1 14 2 1 17 2 13 2 18 3 12 4 3 19 6 11 & 4 20 4 10 5 21 EN 5 9 6 22 7 7 23 SN74AHC138 BIN/OCT 15 1 0 24 1 14 2 1 25 2 13 2 26 3 12 4 3 27 6 11 & 4 28 4 10 5 29 EN 5 9 6 30 7 7 31 Figure 3. 32-Bit Decoding Scheme 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9851601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9851601Q2A SNJ54AHC 138FK 5962-9851601QEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9851601QE A SNJ54AHC138J 5962-9851601QFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9851601QF A SNJ54AHC138W SN74AHC138D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 & no Sb/Br) SN74AHC138DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 & no Sb/Br) SN74AHC138DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 & no Sb/Br) SN74AHC138DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 & no Sb/Br) SN74AHC138DRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 & no Sb/Br) SN74AHC138DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 & no Sb/Br) SN74AHC138N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74AHC138N & no Sb/Br) SN74AHC138NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 & no Sb/Br) SN74AHC138PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 & no Sb/Br) SN74AHC138PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 & no Sb/Br) SN74AHC138PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 & no Sb/Br) SN74AHC138PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AHC138RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 HA138 & no Sb/Br) SNJ54AHC138FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9851601Q2A SNJ54AHC 138FK SNJ54AHC138J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9851601QE A SNJ54AHC138J SNJ54AHC138W ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9851601QF A SNJ54AHC138W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AHC138, SN74AHC138 : •Catalog: SN74AHC138 •Military: SN54AHC138 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHC138DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74AHC138DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74AHC138NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AHC138PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHC138RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHC138DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74AHC138DR SOIC D 16 2500 333.2 345.9 28.6 SN74AHC138NSR SO NS 16 2000 367.0 367.0 38.0 SN74AHC138PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74AHC138RGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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