(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:19)(cid:20)(cid:2)(cid:16)(cid:13)(cid:7) (cid:16)(cid:21)(cid:1)(cid:20)(cid:7)(cid:20)(cid:22)(cid:18)(cid:19)(cid:21)(cid:15) (cid:23)(cid:5)(cid:7)(cid:18)(cid:1) SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 (cid:1) (cid:1) 4.5-V to 5.5-V V Operation Max t of 10 ns at 5 V CC pd (cid:1) (cid:1) Inputs Accept Voltages to 5.5 V Inputs Are TTL-Voltage Compatible SN54ACT32...J OR W PACKAGE SN54ACT32...FK PACKAGE SN74ACT32...D, DB, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) C B A C CB 1 1 NV 4 1A 1 14 V CC 1B 2 13 4B 3 2 1 20 19 1Y 4 18 4A 1Y 3 12 4A NC 5 17 NC 2A 4 11 4Y 2A 6 16 4Y 2B 5 10 3B NC 7 15 NC 2Y 6 9 3A 2B 8 14 3B GND 7 8 3Y 9 10 11 12 13 YD CY A 2N N3 3 G NC − No internal connection description/ordering information The ’ACT32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function Y = A + B or Y = A • B in positive logic. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube SN74ACT32N SN74ACT32N Tube SN74ACT32D SSOOIICC −− DD AACCTT3322 Tape and reel SN74ACT32DR −−4400°CC ttoo 8855°CC SOP − NS Tape and reel SN74ACT32NSR ACT32 SSOP − DB Tape and reel SN74ACT32DBR AD32 Tube SN74ACT32PW TTSSSSOOPP −− PPWW AADD3322 Tape and reel SN74ACT32PWR CDIP − J Tube SNJ54ACT32J SNJ54ACT32J −−5555°CC ttoo 112255°CC CFP − W Tube SNJ54ACT32W SNJ54ACT32W LCCC − FK Tube SNJ54ACT32FK SNJ54ACT32FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OOUUTTPPUUTT A B Y H X H X H H L L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:13)(cid:2)(cid:17)(cid:18)(cid:1)(cid:1) (cid:21)(cid:7)(cid:24)(cid:18)(cid:15)(cid:25)(cid:20)(cid:1)(cid:18) (cid:2)(cid:21)(cid:7)(cid:18)(cid:14) (cid:26)(cid:27)(cid:28)(cid:29) (cid:30)(cid:31)!"#$%(cid:26) !(cid:31)%(cid:26)&(cid:28)%(cid:29) (cid:16)(cid:15)(cid:21)(cid:14)(cid:13)(cid:6)(cid:7)(cid:20)(cid:21)(cid:2) Copyright  2003, Texas Instruments Incorporated (cid:14)(cid:5)(cid:7)(cid:5) (cid:28)%’(cid:31)(#&(cid:26)(cid:28)(cid:31)% !"(($%(cid:26) &(cid:29) (cid:31)’ )"*+(cid:28)!&(cid:26)(cid:28)(cid:31)% (cid:30)&(cid:26)$, (cid:16)((cid:31)(cid:30)"!(cid:26)(cid:29) !(cid:31)%’(cid:31)(# (cid:26)(cid:31) (cid:29))$!(cid:28)’(cid:28)!&(cid:26)(cid:28)(cid:31)%(cid:29) )$( (cid:26)(cid:27)$ (cid:26)$(#(cid:29) (cid:31)’ (cid:7)$-&(cid:29) (cid:20)%(cid:29)(cid:26)("#$%(cid:26)(cid:29) (cid:29)(cid:26)&%(cid:30)&((cid:30) .&((&%(cid:26)/, (cid:16)((cid:31)(cid:30)"!(cid:26)(cid:28)(cid:31)% )((cid:31)!$(cid:29)(cid:29)(cid:28)%0 (cid:30)(cid:31)$(cid:29) %(cid:31)(cid:26) %$!$(cid:29)(cid:29)&((cid:28)+/ (cid:28)%!+"(cid:30)$ (cid:26)$(cid:29)(cid:26)(cid:28)%0 (cid:31)’ &++ )&(&#$(cid:26)$((cid:29), POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:19)(cid:20)(cid:2)(cid:16)(cid:13)(cid:7) (cid:16)(cid:21)(cid:1)(cid:20)(cid:7)(cid:20)(cid:22)(cid:18)(cid:19)(cid:21)(cid:15) (cid:23)(cid:5)(cid:7)(cid:18)(cid:1) SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V I CC Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54ACT32 SN74ACT32 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V IOH High-level output current −24 −24 mA IOL Low-level output current 24 24 mA ∆t/∆v Input transition rise or fall rate 8 8 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (cid:16)(cid:15)(cid:21)(cid:14)(cid:13)(cid:6)(cid:7) (cid:16)(cid:15)(cid:18)(cid:22)(cid:20)(cid:18)(cid:25) (cid:28)%’(cid:31)(#&(cid:26)(cid:28)(cid:31)% !(cid:31)%!$(%(cid:29) )((cid:31)(cid:30)"!(cid:26)(cid:29) (cid:28)% (cid:26)(cid:27)$ ’(cid:31)(#&(cid:26)(cid:28)1$ (cid:31)( (cid:30)$(cid:29)(cid:28)0% )(cid:27)&(cid:29)$ (cid:31)’ (cid:30)$1$+(cid:31))#$%(cid:26), (cid:6)(cid:27)&(&!(cid:26)$((cid:28)(cid:29)(cid:26)(cid:28)! (cid:30)&(cid:26)& &%(cid:30) (cid:31)(cid:26)(cid:27)$( (cid:29))$!(cid:28)’(cid:28)!&(cid:26)(cid:28)(cid:31)%(cid:29) &($ (cid:30)$(cid:29)(cid:28)0% 0(cid:31)&+(cid:29), (cid:7)$-&(cid:29) (cid:20)%(cid:29)(cid:26)("#$%(cid:26)(cid:29) ($(cid:29)$(1$(cid:29) (cid:26)(cid:27)$ ((cid:28)0(cid:27)(cid:26) (cid:26)(cid:31) !(cid:27)&%0$ (cid:31)( (cid:30)(cid:28)(cid:29)!(cid:31)%(cid:26)(cid:28)%"$ (cid:26)(cid:27)$(cid:29)$ )((cid:31)(cid:30)"!(cid:26)(cid:29) .(cid:28)(cid:26)(cid:27)(cid:31)"(cid:26) %(cid:31)(cid:26)(cid:28)!$, 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:19)(cid:20)(cid:2)(cid:16)(cid:13)(cid:7) (cid:16)(cid:21)(cid:1)(cid:20)(cid:7)(cid:20)(cid:22)(cid:18)(cid:19)(cid:21)(cid:15) (cid:23)(cid:5)(cid:7)(cid:18)(cid:1) SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ACT32 SN74ACT32 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 4.5 V 4.4 4.4 4.4 IIOOHH == −−5500 µAA 5.5 V 5.4 5.4 5.4 4.5 V 3.86 3.7 3.76 VVOOHH IIOOHH == −−2244 mmAA VV 5.5 V 4.86 4.7 4.76 IOH = −50 mA† 5.5 V 3.86 IOH = −75 mA† 5.5 V 3.85 4.5 V 0.001 0.1 0.1 0.1 IIOOLL == 5500 µAA 5.5 V 0.001 0.1 0.1 0.1 5.5 V 0.36 0.5 0.44 VVOOLL IIOOLL == 2244 mmAA VV 5.5 V 0.36 0.5 0.44 IOL = 50 mA† 5.5 V 1.65 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA One input at 3.4 V, (cid:1)ICC‡ Other inputs at VCC or GND 5.5 V 0.6 1.6 1.5 mA Ci VI = VCC or GND 5 V 2.6 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. ‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, V = 5 V (cid:1) 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C SN54ACT32 SN74ACT32 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX tPLH 1 6.5 9 1 10 AA oorr BB YY nnss tPHL 1 6.5 9 1 10 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF (cid:16)(cid:15)(cid:21)(cid:14)(cid:13)(cid:6)(cid:7) (cid:16)(cid:15)(cid:18)(cid:22)(cid:20)(cid:18)(cid:25) (cid:28)%’(cid:31)(#&(cid:26)(cid:28)(cid:31)% !(cid:31)%!$(%(cid:29) )((cid:31)(cid:30)"!(cid:26)(cid:29) (cid:28)% (cid:26)(cid:27)$ ’(cid:31)(#&(cid:26)(cid:28)1$ (cid:31)( (cid:30)$(cid:29)(cid:28)0% )(cid:27)&(cid:29)$ (cid:31)’ (cid:30)$1$+(cid:31))#$%(cid:26), (cid:6)(cid:27)&(&!(cid:26)$((cid:28)(cid:29)(cid:26)(cid:28)! (cid:30)&(cid:26)& &%(cid:30) (cid:31)(cid:26)(cid:27)$( (cid:29))$!(cid:28)’(cid:28)!&(cid:26)(cid:28)(cid:31)%(cid:29) &($ (cid:30)$(cid:29)(cid:28)0% 0(cid:31)&+(cid:29), (cid:7)$-&(cid:29) (cid:20)%(cid:29)(cid:26)("#$%(cid:26)(cid:29) ($(cid:29)$(1$(cid:29) (cid:26)(cid:27)$ ((cid:28)0(cid:27)(cid:26) (cid:26)(cid:31) !(cid:27)&%0$ (cid:31)( (cid:30)(cid:28)(cid:29)!(cid:31)%(cid:26)(cid:28)%"$ (cid:26)(cid:27)$(cid:29)$ )((cid:31)(cid:30)"!(cid:26)(cid:29) .(cid:28)(cid:26)(cid:27)(cid:31)"(cid:26) %(cid:31)(cid:26)(cid:28)!$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:5)(cid:14)(cid:15)(cid:13)(cid:16)(cid:17)(cid:18) (cid:9)(cid:19)(cid:20)(cid:2)(cid:16)(cid:13)(cid:7) (cid:16)(cid:21)(cid:1)(cid:20)(cid:7)(cid:20)(cid:22)(cid:18)(cid:19)(cid:21)(cid:15) (cid:23)(cid:5)(cid:7)(cid:18)(cid:1) SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 3 V TEST S1 Input 1.5 V 1.5 V tPLH/tPHL Open (see Note B) 0 V tPLH tPHL 2 × VCC VOH 500 Ω S1 Open InO-Puhtapsuet 50% VCC 50% VCC From Output VOL Under Test tPHL tPLH CL = 50 pF 500 Ω (see Note A) VOH Out-of-Phase 50% VCC 50% VCC Output VOL LOAD CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74ACT32D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 & no Sb/Br) SN74ACT32DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AD32 & no Sb/Br) SN74ACT32DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 & no Sb/Br) SN74ACT32DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 & no Sb/Br) SN74ACT32DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 & no Sb/Br) SN74ACT32N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74ACT32N & no Sb/Br) SN74ACT32NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 & no Sb/Br) SN74ACT32PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AD32 & no Sb/Br) SN74ACT32PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AD32 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ACT32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ACT32NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74ACT32PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ACT32DR SOIC D 14 2500 367.0 367.0 38.0 SN74ACT32NSR SO NS 14 2000 367.0 367.0 38.0 SN74ACT32PWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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