(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:9)(cid:10)(cid:5)(cid:11) (cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:9)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:9) (cid:9)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17) (cid:22)(cid:11)(cid:14)(cid:12)(cid:18)(cid:22)(cid:11)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24) (cid:6)(cid:11)(cid:17)(cid:5)(cid:20) (cid:5)(cid:2)(cid:9) (cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 (cid:1) 2-V to 6-V V Operation SN54AC74 ...J OR W PACKAGE CC (cid:1) SN74AC74 ...D, DB, N, NS, OR PW PACKAGE Inputs Accept Voltages to 6 V (TOP VIEW) (cid:1) Max t of 10 ns at 5 V pd 1CLR 1 14 VCC description/ordering information 1D 2 13 2CLR 1CLK 3 12 2D The ’AC74 devices are dual positive-edge- 1PRE 4 11 2CLK triggered D-type flip-flops. 1Q 5 10 2PRE A low level at the preset (PRE) or clear (CLR) input 1Q 6 9 2Q sets or resets the outputs, regardless of the levels GND 7 8 2Q of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the SN54AC74 ...FK PACKAGE outputs on the positive-going edge of the clock (TOP VIEW) pulse. Clock triggering occurs at a voltage level R R L CL and is not directly related to the rise time of the D C C CC 1 1 NV 2 clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels 3 2 1 20 19 1CLK 4 18 2D at the outputs. NC 5 17 NC 1PRE 6 16 2CLK NC 7 15 NC 1Q 8 14 2PRE 9 10 11 12 13 Q D CQ Q 1 N N2 2 G NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube SN74AC74N SN74AC74N Tube SN74AC74D SSOOIICC −− DD AACC7744 Tape and reel SN74AC74DR −−4400°CC ttoo 8855°CC SOP − NS Tape and reel SN74AC74NSR AC74 SSOP − DB Tape and reel SN74AC74DBR AC74 Tube SN74AC74PW TTSSSSOOPP −− PPWW AACC7744 Tape and reel SN74AC74PWR CDIP − J Tube SNJ54AC74J SNJ54AC74J −−5555°CC ttoo 112255°CC CFP − W Tube SNJ54AC74W SNJ54AC74W LCCC − FK Tube SNJ54AC74FK SNJ54AC74FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:12)(cid:20)(cid:13)(cid:9)(cid:10)(cid:6)(cid:15)(cid:14)(cid:13)(cid:2) (cid:9)(cid:5)(cid:15)(cid:5) (cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!(cid:25)(cid:28)(cid:26) (cid:25)" #$(cid:29)(cid:29)%(cid:26)! (cid:31)" (cid:28)(cid:27) &$’((cid:25)#(cid:31)!(cid:25)(cid:28)(cid:26) )(cid:31)!%* Copyright  2003, Texas Instruments Incorporated (cid:12)(cid:29)(cid:28))$#!" #(cid:28)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30) !(cid:28) "&%#(cid:25)(cid:27)(cid:25)#(cid:31)!(cid:25)(cid:28)(cid:26)" &%(cid:29) !+% !%(cid:29)(cid:30)" (cid:28)(cid:27) (cid:15)%,(cid:31)" (cid:14)(cid:26)"!(cid:29)$(cid:30)%(cid:26)!" (cid:13)(cid:26) &(cid:29)(cid:28))$#!" #(cid:28)(cid:30)&((cid:25)(cid:31)(cid:26)! !(cid:28) 0(cid:14)(cid:11)(cid:18)(cid:12)(cid:20)(cid:22)(cid:18)12(cid:3)1(cid:3)(cid:8) (cid:31)(( &(cid:31)(cid:29)(cid:31)(cid:30)%!%(cid:29)" (cid:31)(cid:29)% !%"!%) "!(cid:31)(cid:26))(cid:31)(cid:29)) -(cid:31)(cid:29)(cid:29)(cid:31)(cid:26)!.* (cid:12)(cid:29)(cid:28))$#!(cid:25)(cid:28)(cid:26) &(cid:29)(cid:28)#%""(cid:25)(cid:26)/ )(cid:28)%" (cid:26)(cid:28)! (cid:26)%#%""(cid:31)(cid:29)(cid:25)(. (cid:25)(cid:26)#($)% $(cid:26)(%"" (cid:28)!+%(cid:29)-(cid:25)"% (cid:26)(cid:28)!%)* (cid:13)(cid:26) (cid:31)(( (cid:28)!+%(cid:29) &(cid:29)(cid:28))$#!"(cid:8) &(cid:29)(cid:28))$#!(cid:25)(cid:28)(cid:26) !%"!(cid:25)(cid:26)/ (cid:28)(cid:27) (cid:31)(( &(cid:31)(cid:29)(cid:31)(cid:30)%!%(cid:29)"* &(cid:29)(cid:28)#%""(cid:25)(cid:26)/ )(cid:28)%" (cid:26)(cid:28)! (cid:26)%#%""(cid:31)(cid:29)(cid:25)(. (cid:25)(cid:26)#($)% !%"!(cid:25)(cid:26)/ (cid:28)(cid:27) (cid:31)(( &(cid:31)(cid:29)(cid:31)(cid:30)%!%(cid:29)"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:9)(cid:10)(cid:5)(cid:11) (cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:9)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:9) (cid:9)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17) (cid:22)(cid:11)(cid:14)(cid:12)(cid:18)(cid:22)(cid:11)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24) (cid:6)(cid:11)(cid:17)(cid:5)(cid:20) (cid:5)(cid:2)(cid:9) (cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H† H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 †This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG Q C C C CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:9)(cid:10)(cid:5)(cid:11) (cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:9)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:9) (cid:9)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17) (cid:22)(cid:11)(cid:14)(cid:12)(cid:18)(cid:22)(cid:11)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24) (cid:6)(cid:11)(cid:17)(cid:5)(cid:20) (cid:5)(cid:2)(cid:9) (cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54AC74 SN74AC74 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2 6 2 6 V VCC = 3 V 2.1 2.1 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 5.5 V 3.85 3.85 VCC = 3 V 0.9 0.9 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 5.5 V 1.65 1.65 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V −12 −12 IIOOHH HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V −24 −24 mmAA VCC = 5.5 V −24 −24 VCC = 3 V 12 12 IIOOLL LLooww--lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V 24 24 mmAA VCC = 5.5 V 24 24 ∆t/∆v Input transition rise or fall rate 8 8 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:9)(cid:10)(cid:5)(cid:11) (cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:9)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:9) (cid:9)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17) (cid:22)(cid:11)(cid:14)(cid:12)(cid:18)(cid:22)(cid:11)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24) (cid:6)(cid:11)(cid:17)(cid:5)(cid:20) (cid:5)(cid:2)(cid:9) (cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AC74 SN74AC74 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 3 V 2.9 4.49 2.9 2.9 IIOOHH == −−5500 µµAA 4.5 V 4.4 5.49 4.4 4.4 5.5 V 5.4 5.49 5.4 5.4 IOH = −12 mA 3 V 2.56 2.4 2.46 VVOOHH VV 4.5 V 3.86 3.7 3.76 IIOOHH == −−2244 mmAA 5.5 V 4.86 4.7 4.76 IOH = −50 mA† 5.5 V 3.85 IOH = −75 mA† 5.5 V 3.85 3 V 0.002 0.1 0.1 0.1 IIOOLL == 5500 µµAA 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 IOL = 12 mA 3 V 0.36 0.5 0.44 VVOOLL VV 4.5 V 0.36 0.5 0.44 IIOOLL == 2244 mmAA 5.5 V 0.36 0.5 0.44 IOL = 50 mA† 5.5 V 1.65 IOL = 75 mA† 5.5 V 1.65 Data pins ±0.1 ±1 ±1 IIII Control pins VVII == VVCCCC oorr GGNNDD 55..55 VV ±0.1 ±1 ±1 µAA ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA Ci VI = VCC or GND 5 V 3 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. timing requirements over recommended operating free-air temperature range, V = 3.3 V (cid:1) 0.3 V (unless otherwise noted) (see Figure 1) CC TA = 25°C SN54AC74 SN74AC74 UUNNIITT MIN MAX MIN MAX MIN MAX fclock Clock frequency 100 70 95 MHz PRE or CLR low 5.5 8 7 ttww PPuullssee dduurraattiioonn nnss CLK 5.5 8 7 Data 4 5 4.5 ttssuu SSeettuupp ttiimmee,, ddaattaa bbeeffoorree CCLLKK↑↑ nnss PRE or CLR inactive 0 0.5 0 th Hold time, data after CLK↑ 0.5 0.5 0.5 ns 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:9)(cid:10)(cid:5)(cid:11) (cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:9)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:9) (cid:9)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17) (cid:22)(cid:11)(cid:14)(cid:12)(cid:18)(cid:22)(cid:11)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24) (cid:6)(cid:11)(cid:17)(cid:5)(cid:20) (cid:5)(cid:2)(cid:9) (cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, V = 5 V(cid:1)0.5 V (unless otherwise noted) (see Figure 1) CC TA = 25°C SN54AC74 SN74AC74 UUNNIITT MIN MAX MIN MAX MIN MAX fclock Clock frequency 140 95 125 MHz PRE or CLR low 4.5 5.5 5 ttww PPuullssee dduurraattiioonn nnss CLK 4.5 5.5 5 Data 3 4 3 ttssuu SSeettuupp ttiimmee,, ddaattaa bbeeffoorree CCLLKK↑↑ nnss PRE or CLR inactive 0 0.5 0 th Hold time, data after CLK↑ 0.5 0.5 0.5 ns switching characteristics over recommended operating free-air temperature range, V = 3.3 V (cid:1) 0.3 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C SN54AC74 SN74AC74 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 100 125 70 95 MHz tPLH 3.5 8 12 1 13 2.5 13 PPRREE oorr CCLLRR QQ oorr QQ nnss tPHL 4 10.5 12 1 14 3.5 13.5 tPLH 4.5 8 13.5 1 17.5 4 16 CCLLKK QQ oorr QQ nnss tPHL 3.5 8 14 1 13.5 3.5 14.5 switching characteristics over recommended operating free-air temperature range, V = 5 V (cid:1) 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C SN54AC74 SN74AC74 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 140 160 95 125 MHz tPLH 2.5 6 9 1 9.5 2 10 PPRREE oorr CCLLRR QQ oorr QQ nnss tPHL 3 8 9.5 1 10.5 2.5 10.5 tPLH 3.5 6 10 1 12 3 10.5 CCLLKK QQ oorr QQ nnss tPHL 2.5 6 10 1 10 2.5 10.5 operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 45 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:9)(cid:10)(cid:5)(cid:11) (cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:9)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:9) (cid:9)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17) (cid:22)(cid:11)(cid:14)(cid:12)(cid:18)(cid:22)(cid:11)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24) (cid:6)(cid:11)(cid:17)(cid:5)(cid:20) (cid:5)(cid:2)(cid:9) (cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output 500 Ω S1 Open tPLH/tPHL Open Under Test CL = 50 pF 500 Ω (see Note A) LOAD CIRCUIT tw VCC Input 50% VCC 50% VCC VCC Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS tPLH tPHL VOH InO-Puhtapsuet 50% VCC 50% VCVCOL Timing Input 50% VCC VCC 0 V tPHL tPLH th Out-of-Phase VOH tsu VCC Output 50% VCC 50% VCC Data Input 50% VCC 50% VCC VOL 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES:A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr (cid:2)2.5 ns, tf (cid:2) 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-88520012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 88520012A SNJ54AC 74FK 5962-8852001CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8852001CA SNJ54AC74J 5962-8852001DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8852001DA SNJ54AC74W 5962-8852001VDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8852001VD A SNV54AC74W SN74AC74D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74AC74N & no Sb/Br) SN74AC74NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74AC74N & no Sb/Br) SN74AC74NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SN74AC74PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 & no Sb/Br) SNJ54AC74FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 88520012A SNJ54AC 74FK Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SNJ54AC74J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8852001CA SNJ54AC74J SNJ54AC74W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8852001DA SNJ54AC74W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AC74, SN54AC74-SP, SN74AC74 : Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: SN74AC74, SN54AC74 •Enhanced Product: SN74AC74-EP, SN74AC74-EP •Military: SN54AC74 •Space: SN54AC74-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AC74NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AC74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AC74DR SOIC D 14 2500 367.0 367.0 38.0 SN74AC74DR SOIC D 14 2500 333.2 345.9 28.6 SN74AC74NSR SO NS 14 2000 367.0 367.0 38.0 SN74AC74PWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated