SN54AC374, SN74AC374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003 (cid:2) 2-V to 6-V V Operation SN54AC374...J OR W PACKAGE CC (cid:2) SN74AC374...DB, DW, N, NS, OR PW PACKAGE Inputs Accept Voltages to 6 V (TOP VIEW) (cid:2) Max t of 9.5 ns at 5 V pd (cid:2) 3-State Noninverting Outputs Drive Bus OE 1 20 VCC Lines Directly 1Q 2 19 8Q (cid:2) Full Parallel Access for Loading 1D 3 18 8D 2D 4 17 7D description/ordering information 2Q 5 16 7Q 3Q 6 15 6Q These 8-bit flip-flops feature 3-state outputs 3D 7 14 6D designed specifically for driving highly capacitive 4D 8 13 5D or relatively low-impedance loads. The devices 4Q 9 12 5Q are particularly suitable for implementing buffer GND 10 11 CLK registers, I/O ports, bidirectional bus drivers, and working registers. SN54AC374...FK PACKAGE The eight flip-flops of the ’AC374 devices are (TOP VIEW) D-type edge-triggered flip-flops. On the positive C transition of the clock (CLK) input, the Q outputs D Q E CQ 1 1 OV 8 are set to the logic levels set up at the data (D) inputs. 3 2 1 20 19 2D 4 18 8D A buffered output-enable (OE) input can be used 2Q 5 17 7D to place the eight outputs in either a normal logic 3Q 6 16 7Q state (high or low logic levels) or the 3D 7 15 6Q high-impedance state. In the high-impedance 4D 8 14 6D state, the outputs neither load nor drive the bus 9 10 11 12 13 lines significantly. The high-impedance state and Q D KQ D the increased drive provide the capability to drive 4 N L5 5 G C bus lines in bus-organized systems without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube SN74AC374N SN74AC374N Tube SN74AC374DW SSOOIICC − DDWW AACC337744 Tape and reel SN74AC374DWR −4400°CC ttoo 8855°CC SOP − NS Tape and reel SN74AC374NSR AC374 SSOP − DB Tape and reel SN74AC374DBR AC374 Tube SN74AC374PW TTSSSSOOPP − PPWW AACC337744 Tape and reel SN74AC374PWR CDIP − J Tube SNJ54AC374J SNJ54AC374J −5555°CC ttoo 112255°CC CFP − W Tube SNJ54AC374W SNJ54AC374W LCCC − FK Tube SNJ54AC374FK SNJ54AC374FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright ©2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AC374, SN74AC374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT OE CLK D Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic diagram (positive logic) 1 OE 11 CLK C1 2 3 1Q 1D 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V I CC Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC) Output clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC) Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA CC Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AC374, SN74AC374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC374 SN74AC374 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2 6 2 6 V VCC = 3 V 2.1 2.1 VVIIHH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 5.5 V 3.85 3.85 VCC = 3 V 0.9 0.9 VVIILL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 4.5V 1.35 1.35 VV VCC = 5.5 V 1.65 1.65 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V −12 −12 IIOOHH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V −24 −24 mmAA VCC = 5.5 V −24 −24 VCC = 3 V 12 12 IIOOLL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V 24 24 mmAA VCC = 5.5 V 24 24 Δt/Δv Input transition rise or fall rate 8 8 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AC374 SN74AC374 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 3 V 2.9 2.9 2.9 IIOOHH = −5500 μμAA 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 VVOH IOH = −12 mA 3 V 2.56 2.4 2.46 VV 4.5 V 3.86 3.7 3.76 IIOH = −2244 mmAA 5.5 V 4.86 4.7 4.76 3 V 0.1 0.1 0.1 IIOOLL = 5500 μμAA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 VVOL IOL = 12 mA 3 V 0.36 0.5 0.44 VV 4.5 V 0.36 0.5 0.44 IIOL = 2244 mmAA 5.5 V 0.36 0.5 0.44 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 μA IOZ VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 μA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA Ci VI = VCC or GND 5 V 4.5 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AC374, SN74AC374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, V = 3.3 V ±0.3 V CC (unless otherwise noted) (see Figure 1) TA = 25°C SN54AC374 SN74AC374 UUNNIITT MIN MAX MIN MAX MIN MAX fclock Clock frequency 60 60 60 MHz tw Pulse duration, CLK high or low 5.5 6.5 6 ns tsu Setup time, data before CLK↑ 5.5 6.5 6 ns th Hold time, data after CLK↑ 1 1 1 ns timing requirements over recommended operating free-air temperature range, V = 5 V ± 0.5 V CC (unless otherwise noted) (see Figure 1) TA = 25°C SN54AC374 SN74AC374 UUNNIITT MIN MAX MIN MAX MIN MAX fclock Clock frequency 100 95 100 MHz tw Pulse duration, CLK high or low 4 5 4.5 ns tsu Setup time, data before CLK↑ 4 5 4.5 ns th Hold time, data after CLK↑ 1.5 1.5 1.5 ns switching characteristics over recommended operating free-air temperature range, V = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1) CC TTOO TTOO TA = 25°C SN54AC374 SN74AC374 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 60 110 60 60 MHz tPLH 3 11 13.5 3 16.5 1.5 15.5 CCLLKK QQ nnss tPHL 2.5 10 12.5 3 15 2 14 tPZH 3 9.5 11.5 1 14 1.5 13 OOEE QQ nnss tPZL 3.5 9 11.5 1 14 1.5 13 tPHZ 3 10.5 12.5 1 16 2 14.5 OOEE QQ nnss tPLZ 2 8 11.5 1 13 1 12.5 switching characteristics over recommended operating free-air temperature range, V = 5 V ±0.5 V (unless otherwise noted) (see Figure 1) CC TTOO TTOO TA = 25°C SN54AC374 SN74AC374 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 100 155 95 100 MHz tPLH 2.5 8 9.5 3 12 1.5 10.5 CCLLKK QQ nnss tPHL 2 7 9 3 11 1.5 10 tPZH 2 7 8.5 1.5 10 1 9.5 OOEE QQ nnss tPZL 2 6.5 8.5 1.5 10.5 1 9.5 tPHZ 2 8 11 1.5 12.5 2 12.5 OOEE QQ nnss tPLZ 1.5 6.5 8.5 1.5 10.5 1 10 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AC374, SN74AC374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 500 Ω S1 Open tPLH/tPHL Open From Output tPLZ/tPZL 2 × VCC Under Test tPHZ/tPZH Open CL = 50 pF 500 Ω (see Note A) LOAD CIRCUIT VCC Timing Input 50% VCC tw 0 V th 3 V tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VCC Output VCC Control Input 50% VCC 50% VCC (low-level 50% VCC 50% VCC 0 V 0 V enabling) tPLH tPHL tPZL tPLZ InO-Puhtapsuet 50% VCC 50% VCCVVOOHL SW1 aavt e2Of o×u rtVmpCu C1t 50% VCC VOL + 0.3 V V≈VOCLC (see Note B) tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVCOH WSa1v aetf oOrpme n2 50% VCC VOH − 0.3 V VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-87694012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 87694012A SNJ54AC 374FK 5962-8769401RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8769401RA SNJ54AC374J 5962-8769401SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8769401SA SNJ54AC374W SN74AC374DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74AC374N (RoHS) SN74AC374NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374NSRE4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SN74AC374PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC374 & no Sb/Br) SNJ54AC374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 87694012A SNJ54AC 374FK SNJ54AC374J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8769401RA SNJ54AC374J SNJ54AC374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8769401SA SNJ54AC374W Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AC374, SN74AC374 : •Catalog: SN74AC374 •Military: SN54AC374 NOTE: Qualified Version Definitions: Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AC374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AC374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74AC374NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74AC374PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AC374DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AC374DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AC374NSR SO NS 20 2000 367.0 367.0 45.0 SN74AC374PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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