SN54AC244, SN74AC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS514E − JUNE 1995 − REVISED OCTOBER 2003 (cid:2) 2-V to 6-V V Operation SN54AC244...J OR W PACKAGE CC (cid:2) SN74AC244...DB, DW, N, NS, OR PW PACKAGE Inputs Accept Voltages to 6 V (TOP VIEW) (cid:2) Max t of 7.5 ns at 5 V pd 1OE 1 20 V CC description/ordering information 1A1 2 19 2OE 2Y4 3 18 1Y1 These octal buffers and line drivers are designed 1A2 4 17 2A4 specifically to improve the performance and 2Y3 5 16 1Y2 density of 3-state memory address drivers, clock 1A3 6 15 2A3 drivers, and bus-oriented receivers and 2Y2 7 14 1Y3 transmitters. 1A4 8 13 2A2 The ’AC244 devices are organized as two 4-bit 2Y1 9 12 1Y4 buffers/drivers with separate output-enable (OE) GND 10 11 2A1 inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the SN54AC244...FK PACKAGE (TOP VIEW) high-impedance state. To ensure the high-impedance state during power Y4 A1 OE CCOE up or power down, OE should be tied to V 2 1 1V 2 CC through a pullup resistor; the minimum value of 3 2 1 20 19 the resistor is determined by the current-sinking 1A2 4 18 1Y1 capability of the driver. 2Y3 5 17 2A4 1A3 6 16 1Y2 2Y2 7 15 2A3 1A4 8 14 1Y3 9 10 11 12 13 1 D 14 2 Y N AY A 2 G 21 2 ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube SN74AC244N SN74AC244N Tube SN74AC244DW SSOOIICC − DDWW AACC224444 Tape and reel SN74AC244DWR −4400°CC ttoo 8855°CC SOP − NS Tape and reel SN74AC244NSR AC244 SSOP − DB Tape and reel SN74AC244DBR AC244 Tube SN74AC244PW TTSSSSOOPP − PPWW AACC224444 Tape and reel SN74AC244PWR CDIP − J Tube SNJ54AC244J SNJ54AC244J −5555°CC ttoo 112255°CC CFP − W Tube SNJ54AC244W SNJ54AC244W LCCC − FK Tube SNJ54AC244FK SNJ54AC244FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AC244, SN74AC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS514E − JUNE 1995 − REVISED OCTOBER 2003 FUNCTION TABLE (each buffer) INPUTS OOUUTTPPUUTT OE A Y L H H L L L H X Z logic diagram (positive logic) 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V I CC Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA CC Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AC244, SN74AC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS514E − JUNE 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC244 SN74AC244 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2 6 2 6 V VCC = 3 V 2.1 2.1 VVIIHH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 5.5 V 3.85 3.85 VCC = 3 V 0.9 0.9 VVIILL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 5.5 V 1.65 1.65 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V −12 −12 IIOOHH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V −24 −24 mmAA VCC = 5.5 V −24 −24 VCC = 3 V 12 12 IIOOLL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V 24 24 mmAA VCC = 5.5 V 24 24 Δt/Δv Input transition rise or fall rate 8 8 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AC244, SN74AC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS514E − JUNE 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AC244 SN74AC244 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 3 V 2.9 2.9 2.9 IIOOHH = −5500 μμAA 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 IOH = −12 mA 3 V 2.56 2.4 2.46 VVOH 4.5 V 3.86 3.7 3.76 VV IIOH = −2244 mAA 5.5 V 4.86 4.7 4.76 IOH = −50 mA† 5.5 V 3.85 IOH = −75 mA† 5.5 V 3.85 3 V 0.1 0.1 0.1 IIOOLL = 5500 μμAA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 IOL = 12 mA 3 V 0.36 0.5 0.44 VVOL 4.5 V 0.36 0.5 0.44 VV IIOL = 2244 mmAA 5.5 V 0.36 0.5 0.44 IOL = 50 mA† 5.5 V 1.65 IOL = 75 mA† 5.5 V 1.65 Data inputs VI = VCC or GND ±0.1 ±1 ±1 III Control inputs VI = VCC or GND 55.55 VV ±0.1 ±1 ±1 μAA IOZ VVOI(O =E )V =C CV IoL ro Gr NVIDH, 5.5 V ±0.25 ±5 ±2.5 μA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA Ci VI = VCC or GND 5 V 2.5 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. switching characteristics over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C SN54AC244 SN74AC244 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX tPLH 2 6.5 9 1 12.5 1.5 10 AA YY nnss tPHL 2 6.5 9 1 12 2 10 tPZH 2 6 10.5 1 11.5 1.5 11 OOEE YY nnss tPZL 2.5 7.5 10 1 13 2 11 tPHZ 3 7 10 1 12.5 1.5 10.5 OOEE YY nnss tPLZ 2.5 7.5 10.5 1 13 2.5 11.5 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AC244, SN74AC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS514E − JUNE 1995 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C SN54AC244 SN74AC244 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX tPLH 1.5 5 7 1 9.5 1 7.5 AA YY nnss tPHL 1.5 5 7 1 9 1 7.5 tPZH 1.5 5 7 1 9 1.5 8 OOEE YY nnss tPZL 1.5 5.5 8 1 10.5 1.5 8.5 tPHZ 2.5 6.5 9 1 10.5 1 9.5 OOEE YY nnss tPLZ 2 6.5 9 1 11 2 9.5 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per buffer/driver CL = 50 pF, f = 1 MHz 45 pF PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output 500 Ω S1 Open tPLH/tPHL Open Under Test tPLZ/tPZL 2 × VCC CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) Output LOAD CIRCUIT VCC Control (low-level 50% VCC 50% VCC 0 V enabling) tPZL tPLZ InputtPLH 50% VCC 50% VCC 0V CVC S(Ws1 eaaevt eN2Of oo×ut retVmp CBu C1)t 50% VCC VOL + 0.3 V V≈VOCLC tPHL tPZH tPHZ Output 50% VCC 50% VCVCOH WSa1v aeOtf oOurtpmpeu n2t 50% VCC VOH − 0.3 V VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-87552012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 87552012A SNJ54AC 244FK 5962-8755201RA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8755201RA SNJ54AC244J 5962-8755201SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8755201SA SNJ54AC244W 5962-8755201VRA ACTIVE CDIP J 20 20 TBD SNPB N / A for Pkg Type -55 to 125 5962-8755201VR A SNV54AC244J 5962-8755201VSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8755201VS A SNV54AC244W SN74AC244DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74AC244N (RoHS) SN74AC244NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74AC244N (RoHS) SN74AC244NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) SN74AC244PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC244 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SNJ54AC244FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 87552012A SNJ54AC 244FK SNJ54AC244J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8755201RA SNJ54AC244J SNJ54AC244W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8755201SA SNJ54AC244W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AC244, SN54AC244-SP, SN74AC244 : •Catalog: SN74AC244, SN54AC244 •Enhanced Product: SN74AC244-EP, SN74AC244-EP •Military: SN54AC244 •Space: SN54AC244-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AC244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AC244DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74AC244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74AC244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AC244DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AC244DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AC244NSR SO NS 20 2000 367.0 367.0 45.0 SN74AC244PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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