SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 (cid:0) State-of-the-Art EPIC-II B BiCMOS Design SN54ABTH245...J OR W PACKAGE Significantly Reduces Power Dissipation SN74ABTH245...DB, DGV, DW, N, OR PW PACKAGE (cid:0) (TOP VIEW) Latch-Up Performance Exceeds 500 mA Per JESD 17 DIR 1 20 VCC (cid:0) Typical VOLP (Output Ground Bounce) < 1 V A1 2 19 OE at VCC = 5 V, TA = 25°C A2 3 18 B1 (cid:0) I and Power-Up 3-State Support Hot A3 4 17 B2 off Insertion A4 5 16 B3 (cid:0) A5 6 15 B4 High-Drive Outputs (–32-mA I , 64-mA I ) OH OL (cid:0) A6 7 14 B5 Bus Hold on Data Inputs Eliminates the A7 8 13 B6 Need for External Pullup/Pulldown A8 9 12 B7 Resistors (cid:0) GND 10 11 B8 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and SN54ABTH245...FK PACKAGE (TOP VIEW) Thin Very Small-Outline (DGV) Packages, CCeerraammiicc C(Jh) iDpI CPsa,r rainerds C (FeKra)m, Picla Fsltaict ((WN)) and A2 A1 DIRVCCOE Package 3 2 1 20 19 A3 4 18 B1 description A4 5 17 B2 A5 6 16 B3 These octal bus transceivers are designed for A6 7 15 B4 asynchronous communication between data A7 8 14 B5 buses. The devices transmit data from the A bus 9 10 11 12 13 to the B bus or from the B bus to the A bus, depending on the logic level at the A8 ND B8B7 B6 direction-control (DIR) input. The output-enable G (OE) input can be used to disable the device so the buses are effectively isolated. When V is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. CC However, to ensure the high-impedance state above 2.1 V, OE should be tied to V through a pullup resistor; CC the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry off off disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH245 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH245 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-II B is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 FUNCTION TABLE INPUTS OOPPEERRAATTIIOONN OE DIR L L B data to A bus L H A data to B bus H X Isolation logic symbol† 19 OE G3 1 DIR 3 EN1 [BA] 3 EN2 [AB] 2 18 A1 1 B1 2 3 17 A2 B2 4 16 A3 B3 5 15 A4 B4 6 14 A5 B5 7 13 A6 B6 8 12 A7 B7 9 11 A8 B8 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1 DIR 19 OE 2 A1 18 B1 To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABTH245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABTH245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA OK O Package thermal impedance, q JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54ABTH245 SN74ABTH245 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA D t/D v Input transition rise or fall rate 5 5 ns/V D t/D VCC Power-up ramp rate 200 m s/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABTH245 SN74ABTH245 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3 VVOOHH VV IOH = –24 mA 2 2 VVCCCC == 44.55 VV IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44.55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV Control III inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 mm A A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20 ±100 ±20 VI = 0.8 V 100 100 100 IIII((hholldd)) VVCCCC == 44.55 VV mm AA VI = 2 V –100 –100 –100 IOZPU VVCOC = =0 .05 tVo 2to.1 2 V.7, V, OE = X ±50** ±50** ±50 m A IOZPD VVCOC = =0 .25. 1V V to t o2 .07, V, OE = X ±50** ±50** ±50 m A Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 m A ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 m A IO‡ VCC = 5.5 V, VO = 2.5 V –50 –140 –180 –50 –180 –50 –180 mA Outputs high 5 250 250 250 m A VVCCCC == 55..55 VV,, ICC A or B ports IO = 0, Outputs low 22 30 30 30 mA VI = VCC or GND Outputs disabled 1 250 250 250 m A VCC = 5.5 V, Outputs enabled 1.5 1.5 1.5 mA One input at 3.4 V,, DDaattaa iinnpputtss Other inputs at D ICC§§ VCC or GND Outputs disabled 1.5 1.5 1.5 mA Control VCC = 5.5 V, One input at 3.4 V, 1.5 1.5 1.5 mA inputs Other inputs at VCC or GND Control Ci inputs VI = 2.5 V or 0.5 V 4 pF Cio A or B ports VO = 2.5 V or 0.5 V 8 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. ** On products compliant to MIL-PRF-38535, this parameter is not production tested. †All typical values are at VCC = 5 V. ‡Not more than one output should be tested at a time, and the duration of the test should not exceed one second. §This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L VCC = 5 V, PARAMETER FROM TO TA = 25°C SN54ABTH245 SN74ABTH245 UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX MIN MAX tPLH 1 2 3.2 0.8 3.8 1 3.6 AA oorr BB BB oorr AA nnss tPHL 1 2.6 3.5 0.8 4.2 1 3.9 tPZH 2 3.5 4.5 1.2 6.2 2 5.6 OOEE AA oorr BB nnss tPZL 1.9 4 5.3 1.3 7 1.9 6.2 tPHZ 2.2 4.4 5.4 2.2 6.1 2.2 5.9 OOEE AA oorr BB nnss tPLZ 1.5 3 4 1 4.9 1.5 4.5 tsk(o) 0.5 0.5 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 W S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 W tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oatr m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH – 0.3 V VOL (see Note B) ≈ 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9762301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9762301Q2A SNJ54ABTH 245FK 5962-9762301QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9762301QS A SNJ54ABTH245W SN74ABTH245DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABH245 & no Sb/Br) SN74ABTH245DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABTH245 & no Sb/Br) SN74ABTH245DWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABTH245 & no Sb/Br) SN74ABTH245DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABTH245 & no Sb/Br) SN74ABTH245N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74ABTH245N (RoHS) SN74ABTH245PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABH245 & no Sb/Br) SNJ54ABTH245FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9762301Q2A SNJ54ABTH 245FK SNJ54ABTH245W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9762301QS A SNJ54ABTH245W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABTH245, SN74ABTH245 : •Catalog: SN74ABTH245 •Military: SN54ABTH245 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABTH245DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74ABTH245DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74ABTH245PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABTH245DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74ABTH245DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ABTH245PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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