SN54ABT16827, SN74ABT16827 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS220C – JUNE 1992 – REVISED MAY 1997 (cid:1) SN54ABT16827...WD PACKAGE Widebus Family SN74ABT16827...DL PACKAGE (cid:1) (TOP VIEW) State-of-the-Art EPIC-II B BiCMOS Design Significantly Reduces Power Dissipation 1OE1 1 56 1OE2 (cid:1) Latch-Up Performance Exceeds 500 mA Per 1Y1 2 55 1A1 JEDEC Standard JESD-17 1Y2 3 54 1A2 (cid:1) Typical VOLP (Output Ground Bounce) < 1 V GND 4 53 GND at VCC = 5 V, TA = 25°C 1Y3 5 52 1A3 (cid:1) High-Impedance State During Power Up 1Y4 6 51 1A4 and Power Down VCC 7 50 VCC (cid:1) 1Y5 8 49 1A5 Distributed V and GND Pin Configuration CC 1Y6 9 48 1A6 Minimizes High-Speed Switching Noise (cid:1) 1Y7 10 47 1A7 Flow-Through Architecture Optimizes PCB GND 11 46 GND Layout 1Y8 12 45 1A8 (cid:1) High-Drive Outputs (–32-mA IOH, 64-mA IOL) 1Y9 13 44 1A9 (cid:1) Package Options Include Plastic 300-mil 1Y10 14 43 1A10 Shrink Small-Outline (DL) Package and 2Y1 15 42 2A1 380-mil Fine-Pitch Ceramic Flat (WD) 2Y2 16 41 2A2 Package Using 25-mil Center-to-Center 2Y3 17 40 2A3 Spacings GND 18 39 GND 2Y4 19 38 2A4 description 2Y5 20 37 2A5 2Y6 21 36 2A6 The ’ABT16827 are noninverting 20-bit buffers composed of two 10-bit sections with separate VCC 22 35 VCC 2Y7 23 34 2A7 output-enable signals. For either 10-bit buffer 2Y8GN2D4 33 2A8 section, the two output-enable (1OE1 and 1OE2 2Y9 25 32 GND or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either 2Y10 26 31 2A9 output-enable input is high, the outputs of that 2OE1 27 30 2A10 10-bit buffer section are in the high-impedance 28 29 2OE2 state. When V is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. CC However, to ensure the high-impedance state above 2.1 V, OE should be tied to V through a pullup resistor; CC the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16827 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16827 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-II B are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  1997, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABT16827, SN74ABT16827 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS220C – JUNE 1992 – REVISED MAY 1997 FUNCTION TABLE (each 10-bit section) INPUTS OUTPUT OE1 OE2 A Y L L L L L L H H H X X Z X H X Z logic symbol† 1 & 1OE1 56 EN1 1OE2 28 & 2OE1 EN2 29 2OE2 55 2 1A1 1 1 1Y1 54 3 1A2 1Y2 52 5 1A3 1Y3 51 6 1A4 1Y4 49 8 1A5 1Y5 48 9 1A6 1Y6 47 10 1A7 1Y7 45 12 1A8 1Y8 44 13 1A9 1Y9 43 14 1A10 1Y10 42 15 2A1 1 2 2Y1 41 16 2A2 2Y2 40 17 2A3 2Y3 38 19 2A4 2Y4 37 20 2A5 2Y5 36 21 2A6 2Y6 34 23 2A7 2Y7 33 24 2A8 2Y8 31 26 2A9 2Y9 30 27 2A10 2Y10 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16827, SN74ABT16827 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS220C – JUNE 1992 – REVISED MAY 1997 logic diagram (positive logic) 1 28 1OE1 2OE1 56 29 1OE2 2OE2 55 2 42 15 1A1 1Y1 2A1 2Y1 To Nine Other Channels To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, q (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W JA Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16827 SN74ABT16827 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA Control pins 4 4 DD tt//DD vv IInnppuutt ttrraannssiittiioonn rriissee oorr ffaallll rraattee nnss//VV Data pins 10 10 D t/D VCC Power-up ramp rate 200 200 m s/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABT16827, SN74ABT16827 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS220C – JUNE 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT16827 SN74ABT16827 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3 VVOOHH VV IOH = –24 mA 2 2 VVCCCC == 44.55 VV IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44.55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV II VVCI =C V =C 0C t oo r5 G.5N VD, ±1 ±1 ±1 m A IOZPU‡ VVCOC = =0 .05 tVo 2to.1 2 V.7, V, OE = X ±50 ±50 ±50 m A IOZPD‡ VVCOC = =0 .25. 1V V to t o2 .07, V, OE = X ±50 ±50 ±50 m A IOZH VVCOC = =2 .27. 1V ,V O toE 5≥. 52 VV, 10 10 10 m A IOZL VVCOC = =0 .25. 1V ,V O toE 5≥. 52 VV, –10 –10 –10 m A Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 m A ICEX Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 m A IO§ VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA Outputs high 2 2 2 ICC Outputs low VVCC = 55.55 VV, IIO = 00, 32 32 32 mA VVII == VVCCCC oorr GGNNDD Outputs disabled 2 2 2 D ICC¶ VOCthCe r= i n5p.5u tVs ,a Ot nVeC iCn pourt GaNt 3D.4 V, 1.5 1.5 1.5 mA Ci VI = 2.5 V or 0.5 V 3 pF Co VO = 2.5 V or 0.5 V 7.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡This parameter is characterized, but not production tested. §Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L VCC = 5 V, PARAMETER FROM TO TA = 25°C SN54ABT16827 SN74ABT16827 UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX MIN MAX tPLH 1 1.9 3.1 1 3.6 1 3.4 AA YY nnss tPHL 1 2.1 3.7 1 4.5 1 4.2 tPZH 1 2.8 5 1 5.9 1 5.6 OOEE YY nnss tPZL 1 2.8 4.9 1 5.8 1 5.5 tPHZ 2.4 4.5 6.5 2.4 6.8 2.4 6.6 OOEE YY nnss tPLZ 1.6 3.7 5.7 1.6 7.1 1.6 6.1 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16827, SN74ABT16827 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS220C – JUNE 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 7 V 500 W S1 Open From Output TEST S1 Under Test GND tPLH/tPHL Open (sCeeL N= o5t0e pAF) 500 W tPLZ/tPZL 7 V tPHZ/tPZH Open LOAD CIRCUIT 3 V Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL tPLZ Output VOH 3.5 V Waveform 1 Output 1.5 V 1.5 V S1 at 7 V 1.5 V VOL + 0.3 V VOL VOL (see Note B) tPHZ tPHL tPLH tPZH Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH – 0.3 V VOL (see Note B) ≈ 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty SN74ABT16827DL ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT16827DLG4 ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT16827DLR ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT16827DLRG4 ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) SN74ABT16827DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT16827DLR SSOP DL 56 1000 346.0 346.0 49.0 PackMaterials-Page2

MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.005 (0,13) M 0.008 (0,203) 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 24 0°–(cid:1)8° 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.004 (0,10) 0.110 (2,79) MAX 0.008 (0,20) MIN PINS ** 28 48 56 DIM 0.380 0.630 0.730 A MAX (9,65) (16,00) (18,54) 0.370 0.620 0.720 A MIN (9,40) (15,75) (18,29) 4040048/E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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