SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 (cid:1) Members of the Texas Instruments SN54ABT16373A...WD PACKAGE Widebus Family SN74ABT16373A...DGG OR DL PACKAGE (cid:1) (TOP VIEW) State-of-the-Art EPIC-II B BiCMOS Design Significantly Reduces Power Dissipation 1OE 1 48 1LE (cid:1) Latch-Up Performance Exceeds 500 mA Per 1Q1 2 47 1D1 JEDEC Standard JESD-17 1Q2 3 46 1D2 (cid:1) Typical V (Output Ground Bounce) GND 4 45 GND OLP < 0.8 V at VCC = 5 V, TA = 25°C 1Q3 5 44 1D3 (cid:1) High-Impedance State During Power Up 1Q4 6 43 1D4 and Power Down VCC 7 42 VCC (cid:1) 1Q5 8 41 1D5 Distributed V and GND Pin Configuration CC 1Q6 9 40 1D6 Minimizes High-Speed Switching Noise (cid:1) GND 10 39 GND Flow-Through Architecture Optimizes PCB 1Q7 11 38 1D7 Layout 1Q8 12 37 1D8 (cid:1) High-Drive Outputs (–32-mA IOH, 64-mA IOL) 2Q1 13 36 2D1 (cid:1) Package Options Include Plastic 300-mil 2Q2 14 35 2D2 Shrink Small-Outline (DL) and Thin Shrink GND 15 34 GND Small-Outline (DGG) Packages and 380-mil 2Q3 16 33 2D3 Fine-Pitch Ceramic Flat (WD) Package 2Q4 17 32 2D4 Using 25-mil Center-to-Center Spacings VCC 18 31 VCC 2Q5 19 30 2D5 description 2Q6 20 29 2D6 GND 21 28 GND The ’ABT16373A are 16-bit transparent D-type 2Q7 22 27 2D7 latches with 3-state outputs designed specifically 2Q8 23 26 2D8 for driving highly capacitive or relatively 2OE 24 25 2LE low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When V is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. CC However, to ensure the high-impedance state above 2.1 V, OE should be tied to V through a pullup resistor; CC the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16373A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-II B are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 FUNCTION TABLE (each 8-bit section) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1 1OE 1EN 48 1LE C3 24 2OE 2EN 25 2LE C4 47 2 1D1 3D 1 1Q1 46 3 1D2 1Q2 44 5 1D3 1Q3 43 6 1D4 1Q4 41 8 1D5 1Q5 40 9 1D6 1Q6 38 11 1D7 1Q7 37 12 1D8 1Q8 36 13 2D1 4D 2 2Q1 35 14 2D2 2Q2 33 16 2D3 2Q3 32 17 2D4 2Q4 30 19 2D5 2Q5 29 20 2D6 2Q6 27 22 2D7 2Q7 26 23 2D8 2Q8 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1 24 1OE 2OE 48 25 1LE 2LE C1 2 C1 13 47 1Q1 36 2Q1 1D1 1D 2D1 1D To Seven Other Channels To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT16373A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT16373A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA OK O Package thermal impedance, q JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16373A SN74ABT16373A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA D t/D v Input transition rise or fall rate Outputs enabled 10 10 ns/V D t/D VCC Power-up ramp rate 200 200 m s/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT16373A SN74ABT16373A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3 VVOOHH VV IOH = –24 mA 2 2 VVCCCC == 44.55 VV IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44.55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV II VVCI =C V =C 0C t oo r5 G.5N VD, ±1 ±1 ±1 m A IOZPU‡ VVCOC = =0 .05 tVo 2to.1 2 V.7, V, OE = X ±50 ±50 ±50 m A IOZPD‡ VVCOC = =0 .25. 1V V to t o2 .07, V, OE = X ±50 ±50 ±50 m A IOZH VVCOC = =2 .27. 1V ,V O toE 5≥. 52 VV, 10 10 10 m A IOZL VVCOC = =0 .25. 1V ,V O toE 5≥. 52 VV, –10 –10 –10 m A Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 m A ICEX Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 m A IO§ VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA Outputs high 2 2 2 ICC Outputs low VVCC = 55.55 VV, IIO = 00, 85 85 85 mA VVII == VVCCCC oorr GGNNDD Outputs disabled 2 2 2 D ICC¶ VOCthCe r= i n5p.5u tVs ,a Ot nVeC iCn pourt GaNt 3D.4 V, 1.5 1.5 1.5 mA Ci VI = 2.5 V or 0.5 V 3.5 pF Co VO = 2.5 V or 0.5 V 9.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡This parameter is characterized, but not production tested. §Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C# SN54ABT16373A SN74ABT16373A UNIT MIN MAX MIN MAX MIN MAX tw Pulse duration, LE high 3.3 3.3 3.3 ns tsu Setup time, data before LE↓ 1.5 2.4 1.5 ns th Hold time, data after LE↓ 1 2.2 1 ns #These values apply only to the SN74ABT16373A. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN54ABT16373A FROM TO VCC = 5 V, PARAMETER (INPUT) (OUTPUT) TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH 1.4 3.7 5.3 1.4 6.5 DD QQ nnss tPHL 2 4 5.4 2 6.5 tPLH 1.7 4.1 5.7 1.7 7 LLEE QQ nnss tPHL 2.3 4.3 5.6 2.3 6.3 tPZH 1.1 3.4 5 1.1 6.4 OOEE QQ nnss tPZL 1.5 3.5 4.9 1.5 5.8 tPHZ 2.4 5.1 7.1 2.4 8.3 OOEE QQ nnss tPLZ 1.6 4.4 6.3 1.6 8 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN74ABT16373A FROM TO VCC = 5 V, PARAMETER (INPUT) (OUTPUT) TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH 1.4 3.7 5.3 1.4 6.3 DD QQ nnss tPHL 2 4 5.4 2 6.2 tPLH 1.7 4.1 5.7 1.7 6.7 LLEE QQ nnss tPHL 2.3 4.3 5.6 2.3 6.1 tPZH 1.1 3.4 5 1.1 6.1 OOEE QQ nnss tPZL 1.5 3.5 4.9 1.5 5.6 tPHZ 2.4 5.1 7.1 2.4 8.1 OOEE QQ nnss tPLZ 1.6 4.4 5.8 1.6 6.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 W S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 W tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL VOH Output tPLZ 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oatr m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHZ tPHL tPLH tPZH Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH – 0.3 V VOL (see Note B) ≈ 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9320001QXA ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9320001QX A SNJ54ABT16373A WD 74ABT16373ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A & no Sb/Br) 74ABT16373ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A & no Sb/Br) SN74ABT16373ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A & no Sb/Br) SN74ABT16373ADL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A & no Sb/Br) SN74ABT16373ADLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A & no Sb/Br) SN74ABT16373ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A & no Sb/Br) SNJ54ABT16373AWD ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9320001QX A SNJ54ABT16373A WD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT16373A, SN74ABT16373A : •Catalog: SN74ABT16373A •Enhanced Product: SN74ABT16373A-EP, SN74ABT16373A-EP •Military: SN54ABT16373A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT16373ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74ABT16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ABT16373ADLR SSOP DL 48 1000 367.0 367.0 55.0 PackMaterials-Page2

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.009 (0,23) 0.075 (1,91) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.390 (9,91) 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 1 48 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 24 25 NO. OF 48 56 LEADS** 0.640 0.740 A MAX (16,26) (18,80) 0.610 0.710 A MIN (15,49) (18,03) 4040176/D 10/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA GDFP1-F56 and JEDEC MO-146AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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