(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5)(cid:13) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5) (cid:10)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:6)(cid:17)(cid:18)(cid:18)(cid:19)(cid:20)(cid:1)(cid:21)(cid:22)(cid:20)(cid:16)(cid:23)(cid:19)(cid:20)(cid:1) (cid:24)(cid:16)(cid:7)(cid:25) (cid:26)(cid:15)(cid:1)(cid:7)(cid:5)(cid:7)(cid:19) (cid:27)(cid:17)(cid:7)(cid:28)(cid:17)(cid:7)(cid:1) SCBS248F − JULY 1993 − REVISED JUNE 2004 (cid:1) Members of the Texas Instruments SN54ABT162827A...WD PACKAGE Widebus Family SN74ABT162827A...DGG OR DL PACKAGE (cid:1) Output Ports Have Equivalent 25-Ω Series (TOP VIEW) Resistors, So No External Resistors Are 1OE1 1 56 1OE2 Required 1Y1 2 55 1A1 (cid:1) High-Impedance State During Power Up 1Y2 3 54 1A2 and Power Down GND 4 53 GND (cid:1) Typical V (Output Ground Bounce) 1Y3 5 52 1A3 OLP <1 V at VCC = 5 V, TA = 25°C 1Y4 6 51 1A4 (cid:1) Distributed VCC and GND Pins Minimize VCC 7 50 VCC High-Speed Switching Noise 1Y5 8 49 1A5 (cid:1) 1Y6 9 48 1A6 I and Power-Up 3-State Support Hot off 1Y7 10 47 1A7 Insertion (cid:1) GND 11 46 GND Flow-Through Architecture Optimizes PCB 1Y8 12 45 1A8 Layout 1Y9 13 44 1A9 (cid:1) Latch-Up Performance Exceeds 500 mA Per 1Y10 14 43 1A10 JEDEC Standard JESD-17 2Y1 15 42 2A1 (cid:1) ESD Protection Exceeds JESD 22 2Y2 16 41 2A2 − 2000-V Human-Body Model (A114-A) 2Y3 17 40 2A3 − 200-V Machine Model (A115-A) GND 18 39 GND 2Y4 19 38 2A4 description/ordering information 2Y5 20 37 2A5 2Y6 21 36 2A6 The ’ABT162827A devices are noninverting V 22 35 V 20-bit buffers composed of two 10-bit buffers with CC CC 2Y7 23 34 2A7 separate output-enable signals. For either 10-bit 2Y8 24 33 2A8 buffer, the two output-enable (1OE1 and 1OE2, or GND 25 32 GND 2OE1 and 2OE2) inputs must both be low for the 2Y9 26 31 2A9 corresponding Y outputs to be active. If either 2Y10 27 30 2A10 output-enable input is high, the outputs of that 2OE1 28 29 2OE2 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74ABT162827ADL SSSSOOPP −− DDLL AABBTT116622882277AA −−4400°CC ttoo 8855°CC Tape and reel SN74ABT162827ADLR TSSOP − DGG Tape and reel SN74ABT162827ADGGR ABT162827A −55°C to 125°C CFP − WD Tube SNJ54ABT162827AWD SNJ54ABT162827AWD †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. (cid:17)(cid:2)(cid:29)(cid:19)(cid:1)(cid:1) (cid:27)(cid:7)(cid:25)(cid:19)(cid:20)(cid:24)(cid:16)(cid:1)(cid:19) (cid:2)(cid:27)(cid:7)(cid:19)(cid:22) (cid:30)(cid:31)!" #$%&’()(cid:30) %$)(cid:30)*!)" (cid:28)(cid:20)(cid:27)(cid:22)(cid:17)+(cid:7)(cid:16)(cid:27)(cid:2) Copyright  2004, Texas Instruments Incorporated (cid:22)(cid:5)(cid:7)(cid:5) !),$-’*(cid:30)!$) %&--()(cid:30) *" $, .&/0!%*(cid:30)!$) #*(cid:30)(1 (cid:28)-$#&%(cid:30)" %$),$-’ (cid:30)$ ".(%!,!%*(cid:30)!$)" .(- (cid:30)(cid:31)( (cid:30)(-’" $, (cid:7)(2*" (cid:16))"(cid:30)-&’()(cid:30)" "(cid:30)*)#*-# 3*--*)(cid:30)41 (cid:28)-$#&%(cid:30)!$) .-$%(""!)5 #$(" )$(cid:30) )(%(""*-!04 !)%0&#( (cid:30)("(cid:30)!)5 $, *00 .*-*’((cid:30)(-"1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5)(cid:13) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5) (cid:10)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:6)(cid:17)(cid:18)(cid:18)(cid:19)(cid:20)(cid:1)(cid:21)(cid:22)(cid:20)(cid:16)(cid:23)(cid:19)(cid:20)(cid:1) (cid:24)(cid:16)(cid:7)(cid:25) (cid:26)(cid:15)(cid:1)(cid:7)(cid:5)(cid:7)(cid:19) (cid:27)(cid:17)(cid:7)(cid:28)(cid:17)(cid:7)(cid:1) SCBS248F − JULY 1993 − REVISED JUNE 2004 description/ordering information (continued) These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry off off disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE shall be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 10-bit buffer) INPUTS OOUUTTPPUUTT OE1 OE2 A Y L L L L L L H H H X X Z X H X Z logic diagram (positive logic) 1 28 1OE1 2OE1 56 29 1OE2 2OE2 55 2 42 15 1A1 1Y1 2A1 2Y1 To Nine Other Channels To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V O Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA O Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W JA DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5)(cid:13) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5) (cid:10)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:6)(cid:17)(cid:18)(cid:18)(cid:19)(cid:20)(cid:1)(cid:21)(cid:22)(cid:20)(cid:16)(cid:23)(cid:19)(cid:20)(cid:1) (cid:24)(cid:16)(cid:7)(cid:25) (cid:26)(cid:15)(cid:1)(cid:7)(cid:5)(cid:7)(cid:19) (cid:27)(cid:17)(cid:7)(cid:28)(cid:17)(cid:7)(cid:1) SCBS248F − JULY 1993 − REVISED JUNE 2004 recommended operating conditions (see Note 3) SN54ABT162827A SN74ABT162827A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current −3 −12 mA IOL Low-level output current 8 12 mA ∆t/∆V Input transition rise or fall rate 10 10 ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (cid:28)(cid:20)(cid:27)(cid:22)(cid:17)+(cid:7) (cid:28)(cid:20)(cid:19)(cid:23)(cid:16)(cid:19)(cid:24) !),$-’*(cid:30)!$) %$)%(-)" .-$#&%(cid:30)" !) (cid:30)(cid:31)( ,$-’*(cid:30)!6( $- #("!5) .(cid:31)*"( $, #(6(0$.’()(cid:30)1 +(cid:31)*-*%(cid:30)(-!"(cid:30)!% #*(cid:30)* *)# $(cid:30)(cid:31)(- ".(%!,!%*(cid:30)!$)" *-( #("!5) 5$*0"1 (cid:7)(2*" (cid:16))"(cid:30)-&’()(cid:30)" -("(-6(" (cid:30)(cid:31)( -!5(cid:31)(cid:30) (cid:30)$ %(cid:31)*)5( $- #!"%$)(cid:30)!)&( (cid:30)(cid:31)("( .-$#&%(cid:30)" 3!(cid:30)(cid:31)$&(cid:30) )$(cid:30)!%(1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5)(cid:13) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5) (cid:10)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:6)(cid:17)(cid:18)(cid:18)(cid:19)(cid:20)(cid:1)(cid:21)(cid:22)(cid:20)(cid:16)(cid:23)(cid:19)(cid:20)(cid:1) (cid:24)(cid:16)(cid:7)(cid:25) (cid:26)(cid:15)(cid:1)(cid:7)(cid:5)(cid:7)(cid:19) (cid:27)(cid:17)(cid:7)(cid:28)(cid:17)(cid:7)(cid:1) SCBS248F − JULY 1993 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT162827A SN74ABT162827A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 −1.2 V VCC = 4.5 V, IOH = −1 mA 3.35 3.35 3.35 VCC = 5 V, IOH = −1 mA 3.85 3.85 3.85 VVOOHH VV IOH = −3 mA 3.1 3.1 3.1 VVCCCC == 44..55 VV IOH = −12 mA 2.6* 2.6 IOL = 8 mA 0.4 0.8 0.65 VVOOLL VVCCCC == 44..55 VV VV IOL = 12 mA 0.8* 0.8 Vhys 100 mV II VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA IOZPU VVCOC = =0 .05 tVo 2to.1 2 V.7, V, OE = X ±50 ±50 ±50 µA IOZPD VVCOC = =0 .25. 1V V to t o2 .07, V, OE = X ±50 ±50 ±50 µA IOZH‡ VVCOC = =2 .27. 1V ,V O toE 5≥. 52 VV, 10 10 10 µA IOZL‡ VVCOC = =0 .25. 1V ,V O toE 5≥. 52 VV, −10 −10 −10 µA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 µA IO§ VCC = 5.5 V, VO = 2.5 V −25 −75 −100 −25 −100 −25 −100 mA Outputs high 2 2 2 VVCCCC == 55..55 VV,, IICCCC IIOO == 00,, Outputs low 32 32 32 mmAA VVI == VVCC oorr GGNNDD Outputs disabled 2 2 2 VCC = 5.5 V, Outputs enabled 1 1.5 1 DDaattaa OOnnee iinnppuutt aatt 33..44 VV,, inputs Other inputs at ∆ICCCC¶ VCC or GND Outputs disabled 0.05 1 0.05 mA Control VCC = 5.5 V, One input at 3.4 V, 1.5 1.5 1.5 inputs Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V 4 pF Co VO = 2.5 V or 0.5 V 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡The parameters IOZH and IOZL include the input leakage current. §Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. (cid:28)(cid:20)(cid:27)(cid:22)(cid:17)+(cid:7) (cid:28)(cid:20)(cid:19)(cid:23)(cid:16)(cid:19)(cid:24) !),$-’*(cid:30)!$) %$)%(-)" .-$#&%(cid:30)" !) (cid:30)(cid:31)( ,$-’*(cid:30)!6( $- #("!5) .(cid:31)*"( $, #(6(0$.’()(cid:30)1 +(cid:31)*-*%(cid:30)(-!"(cid:30)!% #*(cid:30)* *)# $(cid:30)(cid:31)(- ".(%!,!%*(cid:30)!$)" *-( #("!5) 5$*0"1 (cid:7)(2*" (cid:16))"(cid:30)-&’()(cid:30)" -("(-6(" (cid:30)(cid:31)( -!5(cid:31)(cid:30) (cid:30)$ %(cid:31)*)5( $- #!"%$)(cid:30)!)&( (cid:30)(cid:31)("( .-$#&%(cid:30)" 3!(cid:30)(cid:31)$&(cid:30) )$(cid:30)!%(1 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5)(cid:13) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5) (cid:10)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:6)(cid:17)(cid:18)(cid:18)(cid:19)(cid:20)(cid:1)(cid:21)(cid:22)(cid:20)(cid:16)(cid:23)(cid:19)(cid:20)(cid:1) (cid:24)(cid:16)(cid:7)(cid:25) (cid:26)(cid:15)(cid:1)(cid:7)(cid:5)(cid:7)(cid:19) (cid:27)(cid:17)(cid:7)(cid:28)(cid:17)(cid:7)(cid:1) SCBS248F − JULY 1993 − REVISED JUNE 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L VCC = 5 V, PPAARRAAMMEETTEERR FROM TO TA = 25°C SN54ABT162827A SN74ABT162827A UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX MIN MAX tPLH 1 2.1 3.6 1 4.1 1 3.9 AA YY nnss tPHL 1.1 2.8 4.2 1.1 5 1.1 4.7 tPZH 1.5 3.4 6.3 1.5 7.2 1.5 6.9 OOEE YY nnss tPZL 1.6 3.5 5.3 1.6 6.6 1.6 6.3 tPHZ 2.1 4.1 6.5 2.1 6.8 2.1 6.6 OOEE YY nnss tPLZ 1.5 3.5 5.9 1.5 7.3 1.5 6.3 (cid:28)(cid:20)(cid:27)(cid:22)(cid:17)+(cid:7) (cid:28)(cid:20)(cid:19)(cid:23)(cid:16)(cid:19)(cid:24) !),$-’*(cid:30)!$) %$)%(-)" .-$#&%(cid:30)" !) (cid:30)(cid:31)( ,$-’*(cid:30)!6( $- #("!5) .(cid:31)*"( $, #(6(0$.’()(cid:30)1 +(cid:31)*-*%(cid:30)(-!"(cid:30)!% #*(cid:30)* *)# $(cid:30)(cid:31)(- ".(%!,!%*(cid:30)!$)" *-( #("!5) 5$*0"1 (cid:7)(2*" (cid:16))"(cid:30)-&’()(cid:30)" -("(-6(" (cid:30)(cid:31)( -!5(cid:31)(cid:30) (cid:30)$ %(cid:31)*)5( $- #!"%$)(cid:30)!)&( (cid:30)(cid:31)("( .-$#&%(cid:30)" 3!(cid:30)(cid:31)$&(cid:30) )$(cid:30)!%(1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5)(cid:13) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:10)(cid:12)(cid:5) (cid:10)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:6)(cid:17)(cid:18)(cid:18)(cid:19)(cid:20)(cid:1)(cid:21)(cid:22)(cid:20)(cid:16)(cid:23)(cid:19)(cid:20)(cid:1) (cid:24)(cid:16)(cid:7)(cid:25) (cid:26)(cid:15)(cid:1)(cid:7)(cid:5)(cid:7)(cid:19) (cid:27)(cid:17)(cid:7)(cid:28)(cid:17)(cid:7)(cid:1) SCBS248F − JULY 1993 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION 7 V 500 Ω S1 Open From Output TEST S1 Under Test GND tPLH/tPHL Open (sCeeL N= o5t0e pAF) 500 Ω tPLZ/tPZL 7 V tPHZ/tPZH Open LOAD CIRCUIT 3 V Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL tPLZ Output VOH 3.5 V Waveform 1 Output 1.5 V 1.5 V S1 at 7 V 1.5 V VOL + 0.3 V VOL VOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH − 0.3 V VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 74ABT162827ADGGRE4 ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74ABT162827ADGGRG4 ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74ABT162827ADLRG4 ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT162827ADGGR ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT162827ADL ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT162827ADLG4 ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74ABT162827ADLR ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT162827ADGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74ABT162827ADLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT162827ADGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74ABT162827ADLR SSOP DL 56 1000 346.0 346.0 49.0 PackMaterials-Page2

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.005 (0,13) M 0.008 (0,203) 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 24 0°–(cid:1)8° 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.004 (0,10) 0.110 (2,79) MAX 0.008 (0,20) MIN PINS ** 28 48 56 DIM 0.380 0.630 0.730 A MAX (9,65) (16,00) (18,54) 0.370 0.620 0.720 A MIN (9,40) (15,75) (18,29) 4040048/E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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