(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4) (cid:8)(cid:9)(cid:13)(cid:6)(cid:14)(cid:7) (cid:6)(cid:15)(cid:16)(cid:16)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:14)(cid:21)(cid:17)(cid:18)(cid:1) (cid:22)(cid:14)(cid:7)(cid:23) (cid:24)(cid:13)(cid:1)(cid:7)(cid:5)(cid:7)(cid:17) (cid:25)(cid:15)(cid:7)(cid:26)(cid:15)(cid:7)(cid:1) SCBS238E − JUNE 1992 − REVISED JUNE 2004 (cid:1) Members of the Texas Instruments SN54ABT162244...WD PACKAGE Widebus(cid:1) Family SN74ABT162244...DGG, DGV, OR DL PACKAGE (cid:1) Output Ports Have Equivalent 25-Ω Series (TOP VIEW) Resistors, So No External Resistors Are 1OE 1 48 2OE Required 1Y1 2 47 1A1 (cid:1) Typical VOLP (Output Ground Bounce) 1Y2 3 46 1A2 <1 V at V = 5 V, T = 25°C CC A GND 4 45 GND (cid:1) High-Impedance State During Power Up 1Y3 5 44 1A3 and Power Down 1Y4 6 43 1A4 (cid:1) Ioff and Power-Up 3-State Support Hot VCC 7 42 VCC Insertion 2Y1 8 41 2A1 (cid:1) 2Y2 9 40 2A2 Distributed V and GND Pins Minimize CC GND 10 39 GND High-Speed Switching Noise (cid:1) 2Y3 11 38 2A3 Flow-Through Architecture Optimizes PCB 2Y4 12 37 2A4 Layout 3Y1 13 36 3A1 (cid:1) Latch-Up Performance Exceeds 500 mA Per 3Y2 14 35 3A2 JESD-17 GND 15 34 GND 3Y3 16 33 3A3 description/ordering information 3Y4 17 32 3A4 The ’ABT162244 devices are 16-bit buffers and VCC 18 31 VCC line drivers designed specifically to improve both 4Y1 19 30 4A1 the performance and density of 3-state memory 4Y2 20 29 4A2 address drivers, clock drivers, and bus-oriented GND 21 28 GND receivers and transmitters. These devices can be 4Y3 22 27 4A3 used as four 4-bit buffers, two 8-bit buffers, or one 4Y4 23 26 4A4 16-bit buffer. These devices provide noninverting 4OE 24 25 3OE outputs and symmetrical active-low output-enable (OE) inputs. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74ABT162244DL SSSSOOPP −− DDLL AABBTT116622224444 Tape and reel SN74ABT162244DLR −−4400°°CC ttoo 8855°°CC TSSOP − DGG Tape and reel SN74ABT162244DGGR ABT162244 TVSOP − DGV Tape and reel SN74ABT162244DGVR AH2244 −55°C to 125°C CFP − WD Tube SNJ54ABT162244WD SNJ54ABT162244WD †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. (cid:26)(cid:18)(cid:25)(cid:20)(cid:15)(cid:27)(cid:7)(cid:14)(cid:25)(cid:2) (cid:20)(cid:5)(cid:7)(cid:5) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$(- Copyright  2004, Texas Instruments Incorporated (cid:26)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $.( $(!"% (cid:31)(cid:30) (cid:7)(/#% (cid:14)(cid:29)%$!’"((cid:29)$% (cid:25)(cid:29) )!(cid:31),’&$% &(cid:31)")+(cid:28)#(cid:29)$ $(cid:31) 3(cid:14)4(cid:13)(cid:26)(cid:18)(cid:16)(cid:13)(cid:24)5(cid:3)(cid:24)(cid:3)(cid:11) #++ )#!#"($(!% #!( $(%$(, %$#(cid:29),#!, 0#!!#(cid:29)$1- (cid:26)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( ’(cid:29)+(%% (cid:31)$.(!0(cid:28)%( (cid:29)(cid:31)$(,- (cid:25)(cid:29) #++ (cid:31)$.(! )!(cid:31),’&$%(cid:11) )!(cid:31),’&$(cid:28)(cid:31)(cid:29) $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4) (cid:8)(cid:9)(cid:13)(cid:6)(cid:14)(cid:7) (cid:6)(cid:15)(cid:16)(cid:16)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:14)(cid:21)(cid:17)(cid:18)(cid:1) (cid:22)(cid:14)(cid:7)(cid:23) (cid:24)(cid:13)(cid:1)(cid:7)(cid:5)(cid:7)(cid:17) (cid:25)(cid:15)(cid:7)(cid:26)(cid:15)(cid:7)(cid:1) SCBS238E − JUNE 1992 − REVISED JUNE 2004 description/ordering information (continued) These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry off off disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE (each 4-bit buffer) INPUTS OOUUTTPPUUTT OE A Y L H H L L L H X Z logic diagram (positive logic) 1 25 1OE 3OE 47 2 36 13 1A1 1Y1 3A1 3Y1 46 3 35 14 1A2 1Y2 3A2 3Y2 44 5 33 16 1A3 1Y3 3A3 3Y3 43 6 32 17 1A4 1Y4 3A4 3Y4 48 24 2OE 4OE 41 8 30 19 2A1 2Y1 4A1 4Y1 40 9 29 20 2A2 2Y2 4A2 4Y2 38 11 27 22 2A3 2Y3 4A3 4Y3 37 12 26 23 2A4 2Y4 4A4 4Y4 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4) (cid:8)(cid:9)(cid:13)(cid:6)(cid:14)(cid:7) (cid:6)(cid:15)(cid:16)(cid:16)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:14)(cid:21)(cid:17)(cid:18)(cid:1) (cid:22)(cid:14)(cid:7)(cid:23) (cid:24)(cid:13)(cid:1)(cid:7)(cid:5)(cid:7)(cid:17) (cid:25)(cid:15)(cid:7)(cid:26)(cid:15)(cid:7)(cid:1) SCBS238E − JUNE 1992 − REVISED JUNE 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V O Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA O Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54ABT162244 SN74ABT162244 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current −3 −12 mA IOL Low-level output current 8 12 mA ∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature −55 125 −40 85 °C NOTES: 3. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4) (cid:8)(cid:9)(cid:13)(cid:6)(cid:14)(cid:7) (cid:6)(cid:15)(cid:16)(cid:16)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:14)(cid:21)(cid:17)(cid:18)(cid:1) (cid:22)(cid:14)(cid:7)(cid:23) (cid:24)(cid:13)(cid:1)(cid:7)(cid:5)(cid:7)(cid:17) (cid:25)(cid:15)(cid:7)(cid:26)(cid:15)(cid:7)(cid:1) SCBS238E − JUNE 1992 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT162244 SN74ABT162244 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 −1.2 V VCC = 4.5 V, IOH = −1 mA 3.35 3.35 3.35 VCC = 5 V, IOH = −1 mA 3.85 3.85 3.85 VVOOHH VV IOH = −3 mA 3.1 3.1 3.1 VVCCCC == 44..55 VV IOH = −12 mA 2.6* 2.6 IOL = 8 mA 0.4 0.8 0.65 VVOOLL VVCCCC == 44..55 VV VV IOL = 12 mA 0.8* 0.8 Vhys 100 mV II VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA IOZPU VVCOC = =0 .05 tVo 2to.1 2 V.7, V, OE = X ±50 ±50 ±50 µA IOZPD VVCOC = =0 .25. 1V V to t o2 .07, V, OE = X ±50 ±50 ±50 µA IOZH VVCOC = =2 .27. 1V ,V O toE 5≥. 52 VV, 10 10 10 µA IOZL VVCOC = =0 .25. 1V ,V O toE 5≥. 52 VV, −10 −10 −10 µA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 µA IO VCC = 5.5 V, VO = 2.5 V −25 −55 −100 −25 −100 −25 −100 mA Outputs high 2 2 2 VVCCCC == 55..55 VV,, IICCCC‡‡ IIOO == 00,, Outputs low 30 30 30 mmAA VVI == VVCC oorr GGNNDD Outputs disabled 2 2 2 VCC = 5.5 V, Outputs enabled 50 50 50 OOnnee iinnppuutt aatt 33..44 VV,, DDaattaa iinnppuuttss Other inputs at ∆ICCCC§ VCC or GND Outputs disabled 50 50 50 µA VCC = 5.5 V, One input at 3.4 V, Control inputs 50 50 50 Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V 3 pF Co VO = 2.5 V or 0.5 V 8 pF *On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡Not more than one output should be tested at a time, and the duration of the test should not exceed one second. §This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4) (cid:8)(cid:9)(cid:13)(cid:6)(cid:14)(cid:7) (cid:6)(cid:15)(cid:16)(cid:16)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:14)(cid:21)(cid:17)(cid:18)(cid:1) (cid:22)(cid:14)(cid:7)(cid:23) (cid:24)(cid:13)(cid:1)(cid:7)(cid:5)(cid:7)(cid:17) (cid:25)(cid:15)(cid:7)(cid:26)(cid:15)(cid:7)(cid:1) SCBS238E − JUNE 1992 − REVISED JUNE 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN54ABT162244 FROM TO VCC = 5 V, PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C MMIINN MMAAXX UNIT MIN TYP MAX tPLH 1 2.5 3.6 1 4.1 AA YY nnss tPHL 1 3.1 4.7 1 5.3 tPZH 1 3.2 4.8 1 5.6 OOEE YY nnss tPZL 1 3.2 4.7 1 5.5 tPHZ 1 3.2 5.3 1 6.3 OOEE YY nnss tPLZ 1 3.1 4.6 1 4.9 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN74ABT162244 FROM TO VCC = 5 V, PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C MMIINN MMAAXX UNIT MIN TYP MAX tPLH 1 2.5 3.2 1 3.9 AA YY nnss tPHL 1 3.1 4 1 4.8 tPZH 1 3.2 4.2 1 5.4 OOEE YY nnss tPZL 1 3.2 4.1 1 5.1 tPHZ 1 3.2 4 1 4.6 OOEE YY nnss tPLZ 1 3.1 3.9 1 4.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:4) (cid:8)(cid:9)(cid:13)(cid:6)(cid:14)(cid:7) (cid:6)(cid:15)(cid:16)(cid:16)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:14)(cid:21)(cid:17)(cid:18)(cid:1) (cid:22)(cid:14)(cid:7)(cid:23) (cid:24)(cid:13)(cid:1)(cid:7)(cid:5)(cid:7)(cid:17) (cid:25)(cid:15)(cid:7)(cid:26)(cid:15)(cid:7)(cid:1) SCBS238E − JUNE 1992 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 Ω S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL VOH Output tPLZ 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oart m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHZ tPHL tPLH tPZH Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH − 0.3 V VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9458701QXA ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9458701QX A SNJ54ABT162244 WD 74ABT162244DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT162244 & no Sb/Br) SN74ABT162244DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT162244 & no Sb/Br) SN74ABT162244DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AH2244 & no Sb/Br) SN74ABT162244DL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT162244 & no Sb/Br) SN74ABT162244DLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT162244 & no Sb/Br) SNJ54ABT162244WD ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9458701QX A SNJ54ABT162244 WD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT162244, SN74ABT162244 : •Catalog: SN74ABT162244 •Military: SN54ABT162244 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT162244DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74ABT162244DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74ABT162244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT162244DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ABT162244DGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74ABT162244DLR SSOP DL 48 1000 367.0 367.0 55.0 PackMaterials-Page2

MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.009 (0,23) 0.075 (1,91) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.390 (9,91) 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 1 48 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 24 25 NO. OF 48 56 LEADS** 0.640 0.740 A MAX (16,26) (18,80) 0.610 0.710 A MIN (15,49) (18,03) 4040176/D 10/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA GDFP1-F56 and JEDEC MO-146AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated