SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 (cid:2) (cid:2) Typical V (Output Ground Bounce) I and Power-Up 3-State Support Hot OLP off <1 V at V = 5 V, T = 25°C Insertion CC A (cid:2) (cid:2) High-Impedance State During Power Up Latch-Up Performance Exceeds 500 mA Per and Power Down JESD 17 (cid:2) (cid:2) High-Drive Outputs (−32-mA I , 64-mA I ) ESD Protection Exceeds JESD 22 OH OL − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN54ABT126...J PACKAGE SN74ABT126...RGY PACKAGE SN54ABT126...FK PACKAGE SN74ABT126...D, DB, N, NS, (TOP VIEW) (TOP VIEW) OR PW PACKAGE (TOP VIEW) 1OE VCC 1A 1OE NCVCC4OE 1OE 1 14 VCC 1 14 3 2 1 20 19 1A 2 13 4OE 1A 2 13 4OE 1Y 4 18 4A 1Y 3 12 4A 1Y 3 12 4A NC 5 17 NC 2OE 4 11 4Y 2OE 4 11 4Y 2OE 6 16 4Y 2A 5 10 3OE 2A 5 10 3OE NC 7 15 NC 2Y 6 9 3A 2Y 6 9 3A 2A 8 14 3OE 9 10 11 12 13 GND 7 8 3Y 7 8 D Y Y D CY A N 3 2 N N3 3 G G NC − No internal connection description/ordering information The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When V is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. CC However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Tape and reel SN74ABT126RGYR AB126 PDIP − N Tube SN74ABT126N SN74ABT126N Tube SN74ABT126D SSOOIICC − DD AABBTT112266 Tape and reel SN74ABT126DR −4400°°CC ttoo 8855°°CC SOP − NS Tape and reel SN74ABT126NSR ABT126 SSOP − DB Tape and reel SN74ABT126DBR AB126 Tube SN74ABT126PW TTSSSSOOPP − PPWW AABB112266 Tape and reel SN74ABT126PWR CDIP − J Tube SNJ54ABT126J SNJ54ABT126J −5555°°CC ttoo 112255°°CC LCCC − FK Tube SNJ54ABT126FK SNJ54ABT126FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright © 2003, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 FUNCTION TABLE (each buffer) INPUTS OOUUTTPPUUTT OE A Y H H H H L L L X Z logic diagram (positive logic) 1 10 1OE 3OE 2 3 9 8 1A 1Y 3A 3Y 4 13 2OE 4OE 5 6 12 11 2A 2Y 4A 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, and RGY packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 recommended operating conditions (see Note 4) SN54ABT126 SN74ABT126 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current −24 −32 mA IOL Low-level output current 48 64 mA Δt/Δv Input transition rise or fall rate 10 10 ns/V Δt/ΔVCC Power-up ramp rate 200 200 μs/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT126 SN74ABT126 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 −1.2 V VCC = 4.5 V, IOH = −3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = −3 mA 3 3 3 VVOH IOH = −24 mA 2 2 VV VVCC = 44.55 VV IOH = −32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOL VVCC = 44.55 VV IOL = 64 mA 0.55* 0.55 VV Vhys 100 mV II VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 μA IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X‡ ±50 ±50 ±50 μA IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X‡ ±50 ±50 ±50 μA IOZH VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≤ 0.8 V 10 10 10 μA IOZL VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≤0.8 V −10 −10 −10 μA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 μA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 μA IO§ VCC = 5.5 V, VO = 2.5 V −50 −100 −200 −50 −200 −50 −200 mA Outputs high 1 250 250 250 μA IICCCC VVVVCII ==C VV=CC 55CC.55 oo VVrr ,GG IIONN DD= 00, Outputs low 24 30 30 30 mA Outputs disabled 0.5 250 250 250 μA VCC = 5.5 V, Outputs enabled 1.5 1.5 1.5 mA ΔΔIICC¶¶ OOOnntheee iirnn ippnuupttu aatstt 33a.t44 V VVC,C or GND Outputs disabled 50 50 50 μA Ci VI = 2.5 V or 0.5 V 3 pF Co VO = 2.5 V or 0.5 V 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state. §Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 5 and Figure 1) PPAARRAAMMEETTEERR FROM TO VTAC C= =2 55° VC, SN54ABT126 SN74ABT126 UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX MIN MAX tPLH 1 2.9 4.9 1 7.3 1 6.3 AA YY nnss tPHL 1 2.5 5.1 1 5.9 1 5.7 tPZH 1 4.4 5.8 1 5.3 1 6.5 OOEE YY nnss tPZL 1 4.4 5.9 1 6.4 1 6.5 tPHZ 1 3 5.7 1 6.9 1 6.8 OOEE YY nnss tPLZ 1 3 5.8 1 7.2 1 6.7 NOTE 5: Limits may vary among suppliers. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 Ω S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oart m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHL tPLH tPZH tPHZ Output Output 1.5 V 1.5 V VOH WSa1v aetf oOrpme n2 1.5 V VOH − 0.3 V VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74ABT126D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT126 & no Sb/Br) SN74ABT126DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB126 & no Sb/Br) SN74ABT126DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT126 & no Sb/Br) SN74ABT126N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74ABT126N & no Sb/Br) SN74ABT126NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT126 & no Sb/Br) SN74ABT126PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB126 & no Sb/Br) SN74ABT126PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB126 & no Sb/Br) SN74ABT126RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 AB126 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT126DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ABT126NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74ABT126PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74ABT126RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT126DR SOIC D 14 2500 367.0 367.0 38.0 SN74ABT126NSR SO NS 14 2000 367.0 367.0 38.0 SN74ABT126PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74ABT126RGYR VQFN RGY 14 3000 367.0 367.0 35.0 PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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