Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 SN65LVDxx High-Speed Differential Line Drivers and Receivers 1 Features 2 Applications • MeetsorExceedstheANSITIA/EIA-644Standard • WirelessInfrastructure 1 • DesignedforSignalingRates (1)upto: • TelecomInfrastructure – 630MbpsforDrivers • Printer – 400MbpsforReceivers 3 Description • OperatesFroma2.4-Vto3.6-VSupply The SN65LVDS1, SN65LVDS2, and SN65LVDT2 • AvailableinSOT-23andSOICPackages devices are single, low-voltage, differential line • Bus-TerminalESDExceeds9kV drivers and receivers in the small-outline transistor • Low-VoltageDifferentialSignalingWithTypical package. The outputs comply with the TIA/EIA-644 OutputVoltagesof350mVIntoa100-ΩLoad standard and provide a minimum differential output voltage magnitude of 247 mV into a 100-Ω load at • PropagationDelayTimes signaling rates up to 630 Mbps for drivers and 400 – 1.7-nsTypicalDriver Mbpsforreceivers. – 2.5-nsTypicalReceiver When the SN65LVDS1 device is used with an LVDS • PowerDissipationat200MHz receiver (such as the SN65LVDT2) in a point-to-point – 25mWTypicalDriver connection, data or clocking signals can be transmitted over printed-circuit board traces or cables – 60mWTypicalReceiver at very high rates with very low electromagnetic • LVDTReceiverIncludesLineTermination emissions and power consumption. The packaging, • LowVoltageTTL(LVTTL)LevelDriverInputIs5- low power, low EMI, high ESD tolerance, and wide VTolerant supply voltage range make the device ideal for battery-poweredapplications. • DriverIsOutputHigh-Impedancewith V <1.5V The SN65LVDS1, SN65LVDS2, and SN65LVDT2 CC devices are characterized for operation from –40°C to • ReceiverOutputandInputsareHigh-Impedance 85°C. WithV <1.5V CC • ReceiverOpen-CircuitFailSafe DeviceInformation(1) • DifferentialInputVoltageThresholdLessThan PARTNUMBER PACKAGE BODYSIZE(NOM) 100mV SOIC(8) 4.90mm×3.91mm SN65LVDS1 SOT(5) 2.90mm×1.60mm SOIC(8) 4.90mm×3.91mm SN65LVDS2 SOT(5) 2.90mm×1.60mm SOIC(8) 4.90mm×3.91mm SN65LVDT2 SOT(5) 2.90mm×1.60mm (1) Thesignalingrateofalineisthenumberofvoltage transitionsthataremadepersecondexpressedintheunits (1) For all available packages, see the orderable addendum at bps(bitpersecond) theendofthedatasheet. SimplifiedSchematic V V SUPPLY CC SN65LVDS1 SN65LVDT2 V V Z B V V CC CC CC CC 100WTrace D Y A R LVTTL LVTTL Out In NC NC NC NC GND GND NC NC GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9.2 FunctionalBlockDiagram.......................................14 2 Applications........................................................... 1 9.3 FeatureDescription.................................................14 3 Description............................................................. 1 9.4 DeviceFunctionalModes........................................17 4 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 19 10.1 ApplicationInformation..........................................19 5 DeviceOptions....................................................... 3 10.2 TypicalApplications..............................................19 6 PinConfigurationandFunctions......................... 3 11 PowerSupplyRecommendations..................... 26 7 Specifications......................................................... 4 12 Layout................................................................... 26 7.1 AbsoluteMaximumRatings......................................4 12.1 LayoutGuidelines.................................................26 7.2 ESDRatings..............................................................4 12.2 LayoutExample....................................................30 7.3 RecommendedOperatingConditions.......................4 13 DeviceandDocumentationSupport................. 32 7.4 ThermalInformation..................................................5 7.5 DriverElectricalCharacteristics................................5 13.1 DeviceSupport......................................................32 7.6 ReceiverElectricalCharacteristics...........................6 13.2 DocumentationSupport .......................................32 7.7 DriverSwitchingCharacteristics...............................6 13.3 RelatedLinks........................................................32 7.8 ReceiverSwitchingCharacteristics...........................7 13.4 Trademarks...........................................................32 7.9 TypicalCharacteristics..............................................8 13.5 ElectrostaticDischargeCaution............................32 13.6 Glossary................................................................32 8 ParameterMeasurementInformation................10 14 Mechanical,Packaging,andOrderable 9 DetailedDescription............................................ 14 Information........................................................... 32 9.1 Overview.................................................................14 4 Revision History ChangesfromRevisionK(November2008)toRevisionL Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 2 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 5 Device Options PARTNUMBER INTEGRATEDTERMINATION PACKAGE SN65LVDS1DBV SOT-23(5) SN65LVDS1D SOIC(8) SN65LVDS2DBV SOT-23(5) SN65LVDS2D SOIC(8) SN65LVDT2DBV √ SOT-23(5) SN65LVDT2D √ SOIC(8) 6 Pin Configuration and Functions SN65LVDS1 SN65LVDS2 and SN65LVDT2 DBV Package DBV Package (TOPVIEW) (TOPVIEW) VCC 1 5 D VCC 1 5 R GND 2 GND 2 Z 3 4 Y A 3 4 B 110-WResistor for LVDT Only SN65LVDS1 D Package (TOPVIEW) V 1 8 Z CC D 2 7 Y NC 3 6 NC GND 4 5 NC SN65LVDS2 and SN65LVDT2 D Package (TOPVIEW) B 1 8 VCC A 2 7 R NC 3 6 NC NC 4 5 GND 110-WResistor for LVDT Only PinFunctions:SN65LVDS1 PIN I/O DESCRIPTION NAME DBV D V 1 1 -- Supplyvoltage CC GND 2 4 -- Ground D 5 2 I LVTTLinputsignal Y 4 7 O Differential(LVDS)non-invertingoutput Z 3 8 O Differential(LVDS)invertingoutput NC -- 3,5,6 -- Noconnect Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com PinFunctions:SN65LVDS2,SN65LVDT2 PIN I/O DESCRIPTION NAME DBV D V 1 8 -- Supplyvoltage CC GND 2 5 -- Ground A 3 2 I Differential(LVDS)non-invertingoutput B 4 1 I Differential(LVDS)invertingoutput R 5 7 O LVTTLoutputsignal NC -- 3,4,6 -- Noconnect 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) PARAMETER MIN MAX UNIT Supplyvoltagerange,V (2) –0.5 4 V CC (AorB) –0.5 4 V Inputvoltagerange,V I (D) –0.5 V +2 V CC Outputvoltage,V (YorZ) –0.5 4 V O Differentialinputvoltagemagnitude,|V | SN65LVDT2only 1 V ID Receiveroutputcurrent,I –12 12 mA O Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltagesarewithrespecttonetworkgroundterminal. 7.2 ESD Ratings VALUE UNIT Human-bodymodelelectrostaticdischarge,HBM Allpins ±4000 ESD(1) Electrostatic Buspins(A,B,Y,Z) ±9000 V V (ESD) discharge Machine-modelelectrostaticdischarge,MMESD(2) ±400 Field-induced-chargedevicemodelelectrostaticdischarge,FCDMESD(3) ±1500 (1) TestmethodbaseduponJEDECStandard22,TestMethodA114-A.BuspinsstressedwithrespecttoGNDandV separately. CC (2) TestmethodbaseduponJEDECStandard22,TestMethodA114-A. (3) TestmethodbaseduponEIA-JEDECJESD22-C101C. 7.3 Recommended Operating Conditions PARAMETER MIN NOM MAX UNIT V Supplyvoltage 2.4 3.3 3.6 V CC V High-levelinputvoltage 2 5 V IH V Low-levelinputvoltage 0 0.8 V IL T Operatingfree-airtemperature –40 85 °C A |V | Magnitudeofdifferentialinputvoltage 0.1 0.6 V ID Inputvoltage(anycombinationofinputorcommon-modevoltage) 0 V –0.8 V CC 4 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 7.4 Thermal Information SN65LVDS1,SN65LVDS2, SN65LVDT2 THERMALMETRIC(1) UNIT D DBV 8PINS 5PINS R Junction-to-ambientthermalresistance 172.4 322.6 °C/W θJA Power TA≤25°C 725 385 mW rating T ≤85°C 402 200 A (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 7.5 Driver Electrical Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN(1) TYP(2) MAX UNIT R =100Ω,2.4≤V <3V 200 350 454 L CC |V | Differentialoutputvoltagemagnitude OD R =100Ω,3≤V <3.6V 247 350 454 L CC mV Changeindifferentialoutputvoltage Δ|V | SeeFigure10 –50 50 OD magnitudebetweenlogicstates V Steady-statecommon-modeoutputvoltage 1.125 1.375 V OC(SS) Changeinsteady-statecommon-mode ΔV –50 50 mV OC(SS) outputvoltagebetweenlogicstates SeeFigure10 Peak-to-peakcommon-modeoutput V 25 100 mV OC(PP) voltage V =0VorV ,Noload 2 4 I CC I Supplycurrent mA CC V =0VorV ,R =100Ω 5.5 8 I CC L I High-levelinputcurrent V =5V 2 20 μA IH IH I Low-levelinputcurrent V =0.8V 2 10 μA IL IL V orV =0V 3 10 OY OZ I Short-circuitoutputcurrent mA OS V =0V 10 OD I Power-offoutputcurrent V =1.5V,V =3.6V –1 1 μA O(OFF) CC O C Inputcapacitance V =0.4sin(4E6πt)+0.5V 3 pF i I (1) Thealgebraicconvention,inwhichtheleastpositive(mostnegative)limitisdesignatedasaminimum,isusedinthisdatasheet. (2) Alltypicalvaluesareat25°Candwitha3.3-Vsupply. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 7.6 Receiver Electrical Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN(1) TYP(2) MAX UNIT Positive-goingdifferentialinputvoltage V 100 ITH+ threshold SeeFigure11 mV Negative-goingdifferentialinputvoltage V –100 ITH– threshold I =–8mA,V =2.4V 1.9 OH CC V High-leveloutputvoltage V OH I =–8mA,V =3V 2.4 OH CC V Low-leveloutputvoltage I =8mA 0.25 0.4 V OL OL I Supplycurrent Noload,Steadystate 4 7 mA CC V =0V,otherinput=1.2V –20 –2 I LVDS2 V =2.2V,otherinput=1.2V, I –3 –1.2 V =3.0V CC I Inputcurrent(AorBinputs) μA I V =0V,otherinputopen –40 -4 I LVDT2 V =2.2V,otherinputopen, I –6 –2.4 V =3.0V CC Differentialinputcurrent I LVDS2 V =2.4V,V =2.3V –2 2 μA ID (I –I ) IA IB IA IB Power-offinputcurrent(AorB LVDS2 VCC=0V,VIA=VIB=2.4V 20 I μA I(OFF) inputs) LVDT2 V =0V,V =V =2.4V 40 CC IA IB R Differentialinputresistance LVDT2 V =2.4V,V =2.2V 90 111 132 Ω T IA IB C Inputcapacitance V =0.4sin(4E6πt)+0.5V 5.8 pF I I C Outputcapacitance V =0.4sin(4E6πt)+0.5V 3.4 pF O I (1) Thealgebraicconvention,inwhichtheleastpositive(mostnegative)limitisdesignatedasaminimum,isusedinthisdatasheet. (2) Alltypicalvaluesareat25°Candwitha2.7-Vsupply. 7.7 Driver Switching Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT t Propagationdelaytime,low-to-high-leveloutput 1.5 3.1 ns PLH t Propagationdelaytime,high-to-low-leveloutput 1.8 3.1 ns PHL R =100Ω,C =10pF, t Differentialoutputsignalrisetime L L 0.6 1 ns r SeeFigure13 t Differentialoutputsignalfalltime 0.7 1 ns f t Pulseskew(|t –t |)(2) 0.3 ns sk(p) PHL PLH (1) Alltypicalvaluesareat25°Candwitha3.3-Vsupply. (2) t isthemagnitudeofthetimedifferencebetweenthehigh-to-lowandlow-to-highpropagationdelaytimesatanoutput. sk(p) 6 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 7.8 Receiver Switching Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT Propagationdelaytime,low-to-high- t 1.4 2.6 3.6 ns PLH leveloutput Propagationdelaytime,high-to-low- tPHL leveloutput CL=10pF,SeeFigure14 1.4 2.5 3.6 ns t Pulseskew(|t –t |)(2) 0.1 0.6 ns sk(p) pHL pLH t Outputsignalrisetime 0.8 1.4 ns r t Outputsignalfalltime 0.8 1.4 ns f V =3.0V–3.6V 2.2 3 5.5 V/ns CC t Outputslewrate(rising) r(slew) V =2.4V–2.7V 1.5 1.9 2.9 V/ns CC C =10pF L V =3.0V–3.6V 2.7 3.8 6 V/ns CC t Outputslewrate(falling) f(slew) V =2.4V–2.7V 2.1 2.3 3.9 V/ns CC (1) Alltypicalvaluesareat25°Candwitha2.7-Vsupply. (2) t isthemagnitudeofthetimedifferencebetweenthehigh-to-lowandlow-to-highpropagationdelaytimesatanoutput. sk(p) Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 7.9 Typical Characteristics 2.6 1.9 VCC = 2.4 V VCC = 2.4 V − Driver High-to-Low PropagationDelay Times − ns 11212.....284264 VCVCVC =CCV C2C= .C =73 = 3VV .33. 6V V − Driver High-to-Low PropagationDelay Times − ns 1111111.......4265378 VVCCCC = = 3 3.6 V V VCCV =C C2 .=7 3V.3 V tPHL 1.2 tPLH 1.1 1 1 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure1.DriverHigh-to-LowLevelPropagationDelayTimes Figure2.DriverLow-to-HighLevelPropagationDelayTimes vsFree-AirTemperature vsFree-AirTemperature 4 4 er High-Level Output Voltage − V 213...55325 VCC = 3.3 V VCC = 2.7 V ver Low-Level Output Voltage − V 213...32555 VCC = 2.7 V VCC = 3.3 V eiv 1 cei 1 c e e R − RH 0.5 − OL 0.5 O V V 0 0 −70 −60 −50 −40 −30 −20 −10 0 0 10 20 30 40 50 60 70 IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure3.ReceiverHigh-LevelOutputVoltagevsHigh-Level Figure4.ReceiverLow-LevelOutputVoltagevsLow-Level OutputCurrent OutputCurrent 2.9 3 n n o gatio 2.85 VCC = 2.4 V agati 2.9 VCC = 2.4 V pa 2.8 op − Receiver High-to-Low level ProPHLDelay Times − ns2222222....6547...6575555 VCC =V 3C.C3 =V 3.6 V VCC = 2V.7C CV = 3 V − Receiver Low-to-High Level PrPLHDelay time s − ns 222222......648753 VVCCC C= =2 .37. V6V CVC = 3.3V CVC = 3 V t 2.4 t 2.2 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure5.ReceiverHigh-to-LowLevelPropagationDelay Figure6.ReceiverLow-to-HighLevelPropagationDelay TimesvsFree-AirTemperature TimesvsFree-AirTemperature 8 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Typical Characteristics (continued) 1400 1200 VCC = 2.5 V VCC = 3.3 V 1200 1000 ps 1000 Rise Time ps Rise Time − − 800 e e m m Ti 800 Ti Fall Fall Time Fall 600 Fall Time se/ 600 se/ Ri Ri − − 400 t, t rf 400 t, t rf 200 200 0 0 0 5 10 15 20 25 0 5 10 15 20 25 CL − Capacitive Load − pF CL − Capacitive Load − pF Figure7.RiseorFallTimevsCapacitiveLoad Figure8.RiseorFallTimevsCapacitiveLoad Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 8 Parameter Measurement Information IOY II Y D VOD V (cid:1)V Z IOZ VOY OY 2 OZ VI VOC VOZ Figure9. DriverVoltageandCurrentDefinitions 49.9 W , ±1% (2 Places) Y VI 1.4 V Input VI 1 V Z 50 pF VOC VOC(PP) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=0.5Mpps,pulsewidth=500±10ns.C includesinstrumentationandfixturecapacitancewithin0.06mmof L thedeviceundertest.ThemeasurementofV ismadeontestequipmentwitha–3dBbandwidthofatleast300 OC(PP) MHz. Figure10. DriverTestCircuitandDefinitionsfortheDriverCommon-ModeOutputVoltage IIA A VIA(cid:1)VIB R IO 2 IIB VID VIA VIC B VO VIB Figure11. ReceiverVoltageandCurrentDefinitions 10 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Parameter Measurement Information (continued) 1000 W 100 W 100 W † VID + 1000 W 10 pF, VO VIC − 2 Places 15 pF †Remove for testing LVDT device. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of < 1 ns. VIT+ 0 V VID −100 mV VO 100 mV VID 0 V VIT− VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. Figure12. V andV InputVoltageThresholdTestCircuitandDefinitions IT+ IT– Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Parameter Measurement Information (continued) Y 100 W Input VOD ±1% Z CL = 10 pF (2 Places) 2 V Input 1.4 V or 1.2 V (see Note B) 0.8 V tPLH tPHL 100% 80% Output VOD(H) 0 V VOD(L) 20% 0% tf tr A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=50Mpps,pulsewidth=10±0.2ns.C includesinstrumentationandfixturecapacitancewithin0.06mmof L thedeviceundertest. B. Thispointis1.4VwithV =3.3Vor1.2VwithV =2.7V. CC CC Figure13. DriverTestCircuit,Timing,andVoltageDefinitionsfortheDifferentialOutputSignal 12 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Parameter Measurement Information (continued) VID VIA CL VO VIB 10 pF VIA 1.4 V VIB 1 V VID 0.4 V 0 V −0.4 V tPHL tPLH VO VOH 80% 0.45 VCC 20% VOL tf tr A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=50Mpps,pulsewidth=10±0.2ns.C includesinstrumentationandfixturecapacitancewithin0.06mofthe L deviceundertest. Figure14. ReceiverTimingTestCircuitandWaveforms Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 9 Detailed Description 9.1 Overview The SN65LVDS1 device is a single-channel, low-voltage differential signaling (LVDS) line driver. It operates from a single supply that is nominally 3.3 V, but can be as low as 2.4 V and as high as 3.6 V. The input signal to the SN65LVDS1 is an LVTTL signal. The output of the device is a differential signal complying with the LVDS standard (TIA/EIA-644). The differential output signal operates with a signal level of 340 mV, nominally, at a common-mode voltage of 1.2 V. This low differential output voltage results in a low emitted radiated energy, which is dependent on the signal slew rate. The differential nature of the output provides immunity to common- modecoupledsignalsthatthedrivensignalmayexperience. The SN65LVDS1 device is intended to drive a 100-Ω transmission line. This transmission line may be a printed- circuit board (PCB) or cabled interconnect. With transmission lines, the optimum signal quality and power delivery is reached when the transmission line is terminated with a load equal to the characteristic impedance of theinterconnect.Likewise,thedriven100-Ωtransmissionlineshouldbeterminatedwithamatchedresistance. The SN65LVDS2 device is a single-channel LVDS line receiver. It also operates from a single supply that is nominally 3.3 V, but can be as low as 2.4 V and as high as 3.6 V. The input signal to the SN65LVDS2 is a differentialLVDSsignal.TheoutputofthedeviceisaLVTTLdigitalsignal.ThisLVDSreceiverrequires ±100mV of input signal to determine the correct state of the received signal compliant LVDS receivers can accept input signals with a common-mode range between 0.05 V and 2.35 V. As the common-mode output voltage of an LVDS driver is 1.2 V, the SN65LVDS2 correctly determines the line state when operated with a 1-V ground shift betweendriverandreceiver. The SN65LVDT2 device is also a single-channel LVDS receiver. This device differs from the SN65LVDS2 in that it incorporates an integrated termination resistor along with the receiver. This termination would take the place of the matched load line termination mentioned above. The SN65LVDT2 can be used in a point-to-point system or in a multidrop system when it is the last receiver on the multidrop bus. The SN65LVDT2 device should not be used at every node in a multidrop system as this would change the loaded bus impedance throughout the bus resultinginmultiplereflectionsandsignaldistortion. 9.2 Functional Block Diagram Y A D R B Z SN65LVDS1 SN65LVDS2 & SN65LVDT2 (110 (cid:13)(cid:3)UHVLVWRU(cid:3)IRU(cid:3)µ/9'7(cid:3)RQO\) 9.3 Feature Description 9.3.1 SN65LVDS1Features 9.3.1.1 DriverOutputVoltageandPower-OnReset The SN65LVDS1 driver operates and meets all the specified performance requirements for supply voltages in therangeof2.6Vto3.6V.Whenthesupplyvoltagedropsbelow1.5V(oristurningonandhasnotyetreached 1.5V),power-onresetcircuitrysetthedriveroutputtoahigh-impedancestate. 9.3.1.2 DriverOffset An LVDS-compliant driver is required to maintain the common-mode output voltage at 1.2 V (±75 mV). The SN65LVDS1 incorporates sense circuitry and a control loop to source common-mode current and keep the output signal within specified values. Further, the device maintains the output common-mode voltage at this set pointoverthefull2.6-Vto3.6-Vsupplyrange. 14 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Feature Description (continued) 9.3.1.3 5-VInputTolerance 5-V and 3.3-V TTL logic standards share the same input high-voltage and input low-voltage thresholds, namely 2.0 V and 0.8 V, respectively. Although the maximum supply voltage for the SN65LVDS1 is 3.6 V, the driver can operate and meet all performance requirements when the input signals are as high as 5 V. This allows operation with 3.3-V TTL as well as 5-V TTL logic. 3.3-V CMOS and 5-V CMOS inputs are also allowable, although one should ensure that the duty-cycle distortion that will result from the TTL (ground-referenced) thresholds are acceptable. 9.3.1.4 NCPins NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimumthermalperformance,agoodruleofthumbistogroundtheNCpinsattheboardlevel. 9.3.1.5 DriverEquivalentSchematics The SN65LVDS1 equivalent input and output schematic diagrams are shown in Figure 15. The driver input is represented by a CMOS inverter stage with a 7-V Zener diode. The input stage is high-impedance, and includes an internal pulldown to ground. If the driver input is left open, the driver input provides a low-level signal to the rest of the driver circuitry, resulting in a low-level signal at the driver output pins. The Zener diode provides ESD protection. The driver output stage is a differential pair, one half of which is shown in Figure 15. Like the input stage, the driver output includes a Zener diode for ESD protection. The schematic shows an output stage that includes a set of current sources (nominally 3.5 mA) that are connected to the output load circuit based upon the inputstagesignal.Tothefirstorder,theSN65LVDS2outputstageactsaconstant-currentsource. V CC V CC 50W 5W D Input 10 kW Yor Z Output 7 V 300 kW 7 V S0313-02 Figure15. DriverEquivalentInputandOutputSchematicDiagrams 9.3.2 SN65LVDS2andSN65LVDT2Features 9.3.2.1 ReceiverOpenCircuitFail-Safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. However, the TI LVDS receiver is different in howithandlestheopen-inputcircuitsituation. Open circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal to V through 300-kΩ resistors as shown in Figure 16. The fail-safe feature uses an CC ANDgatewithinputvoltagethresholdsatabout2.3Vtodetectthisconditionandforcetheoutputtoahighlevel. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Feature Description (continued) VCC 300 kW 300 kW A Rt = 100 W (Typ) Y B VIT ≈ 2.3 V Figure16. Open-CircuitFail-SafeoftheLVDSReceiver It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt does not affect the fail-safe function as long as it isconnectedasshowninFigure16.Otherterminationcircuitsmayallowadc-currenttogroundthatcoulddefeat thepullupcurrentsfromthereceiverandthefail-safefeature. 9.3.2.2 ReceiverOutputVoltageandPower-OnReset The receiver high level outputs are a function of the device supply voltage. Both receivers support supply voltages in the range of 2.6 V to 3.6 V. The receiver high level output voltage has a minimum output voltage of 2.4 V (TTL logic compliant), when the supply voltage is above 3 V. For supply voltages in the range of 2.6 V to 3.0 V, the receiver high level has a minimum output voltage of 1.9 V. The SN65LVDS2 and the SN65LVDT2 receivers include power-on reset circuitry similar to the SN65LVDS1 circuitry. When the supply voltage drops below 1.5 V (or is turning on and has not yet reached 1.5 V), power-on reset circuitry sets the receiver input and outputpinstoahigh-impedancestate. 9.3.2.3 Common-ModeRangevsSupplyVoltage Theinputcommon-moderangeoverwhichthereceiversmeetallrequirementsisafunctionofthesupplyvoltage as well. For all supply voltages, the valid input signal is from ground to 0.8 V below the supply rail. Hence, if the device is operating with a 3.3 V supply, and a minimum differential voltage of 100 mV, common-mode values in the range of 0.05 V to 2.45 V are supported. If the supply rail is set to 2.5 V, the common-mode range is limited to0.05Vto1.65V. 9.3.2.4 GeneralPurposeComparator While the SN65LVDS2 and SN65LVDT2 are LVDS standard-compliant receivers, their utility and applications extend to a wider range of signals. As long as the input signals are within the required differential and common- modevoltagerangesmentionedabove,thereceiveroutputwillbeafaithfulrepresentationoftheinputsignal. 9.3.2.5 ReceiverEquivalentSchematics The SN65LVDS2 and SN65LVDT2 equivalent input and output schematic diagrams are shown in Figure 17. The receiver input is a high-impedance differential pair in the case of the SN65LVDS2. The SN65LVDT2 includes an internal termination resistor of 110 Ω across the input port. 7-V Zener diodes are included on each input to provide ESD protection. The receiver output structure shown is a CMOS inverter with an additional Zener diode, againforESDprotection. 16 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Feature Description (continued) VCC VCC 300 kW 300 kW 5 W R Output A Input B Input 7 V 7 V 7 V 110-W LVDT Only Figure17. ReceiverEquivalentInputandOutputSchematicDiagrams 9.3.2.6 NCPins NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimumthermalperformance,agoodruleofthumbistogroundtheNCpinsattheboardlevel. 9.4 Device Functional Modes 9.4.1 OperationWithV <1.5V CC When the SN65LVDS1 is operated with its supply voltage less than 1.5 V, the driver output pins are high- impedance. When the SN65LVDS2 or the SN65LVDT2 is operated with its supply voltage less than 1.5 V, both thereceiverinputandthereceiveroutputpinsarehigh-impedance. 9.4.2 OperationWith1.5V ≤ V <2.4V CC Operation with supply voltages in the range of 1.5 V ≤ V < 2.4 V is undefined, and no specific device CC performanceisguaranteedinthisrange. 9.4.3 OperationWith2.4V ≤ V <3.6V CC Operation with the supply voltages greater than or equal to 2.4 and less than or equal to 3.6 V is normal operation. Some device specifications apply across the full supply range of 2.4 V ≤ V ≤ 3.6 V, while some CC specifications are dependent upon the supply voltage. These dependencies are clearly described in the parametrictablesabove,aswellasshownintheTypicalCharacteristicssection. 9.4.4 SN65LVDS1TruthTable Ascanbeseenfromthetruthtable,whenthedriverinputisleftopen,thedifferentialoutputwillbedrivenlow. Table1.DriverFunction(1) INPUT OUTPUTS D Y Z H H L L L H Open L H (1) H=Highlevel,L=lowlevel,?=indeterminate Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Table2.ReceiverFunction(1) INPUTS OUTPUT V =V –V R ID A B V ≥100mV H ID –100mV<V <100mV ? ID V ≤–100mV L ID Open H (1) H=Highlevel,L=lowlevel,?=indeterminate 9.4.5 SN65LVDS2andSN65LVDT2TruthTable As can be seen from the truth table, when the receiver differential input signal is greater than 100 mV, the receiver output is high, and when the differential input voltage is below –100 mV, the receiver output is low. When the input voltage is between these thresholds (that is, between –100 mV and 100 mV), the receiver output isindeterminate.Itmaybehighorlow.Aspecialcaseoccurswhentheinputtothereceiverisopen-circuited. Table3.DriverFunction(1) INPUT OUTPUTS D Y Z H H L L L H Open L H (1) H=Highlevel,L=lowlevel,?=indeterminate Table4.ReceiverFunction(1) INPUTS OUTPUT V =V –V R ID A B V ≥100mV H ID –100mV<V <100mV ? ID V ≤–100mV L ID Open H (1) H=Highlevel,L=lowlevel,?=indeterminate 18 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single-channel LVDS buffers. The functionality of thesedevicesissimple,yetextremelyflexible,leadingtotheiruseindesignsrangingfromwirelessbasestations to desktop computers. The varied class of potential applications share features and applications discussed in the paragraphsbelow. 10.2 Typical Applications 10.2.1 Point-to-PointCommunications The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of digitaldata,asshowninFigure18. Figure18. Point-to-PointTopology A point-to-point communications channel has a single transmitter (driver) and a single receiver. This communications topology is often referred to as simplex. In Figure 18 the driver receives a single-ended input signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended input to a differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while translating to a signal whose features are more appropriate for communication over extended distances or in a noisyenvironment. 10.2.1.1 DesignRequirements DESIGNPARAMETERS EXAMPLEVALUE DriverSupplyVoltage(V ) 2.4to3.6V CCD DriverInputVoltage 0.8to5.0V DriverSignalingRate DCto400Mbps InterconnectCharacteristicImpedance 100Ω TerminationResistance 100Ω NumberofReceiverNodes 1 ReceiverSupplyVoltage(V ) 2.4to3.6V CCR ReceiverInputVoltage 0toV –0.8V CCR ReceiverSignalingRate DCto400Mbps Groundshiftbetweendriverandreceiver ±1V Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 10.2.1.2 DetailedDesignProcedure 10.2.1.2.1 DriverSupplyVoltage The SN65LVDS1 driver is operated from a single supply. The device can support operation with a supply as low as2.4Vandashighas3.6V.Thedriveroutputvoltageisdependentuponthechosensupplyvoltage.Asshown in Driver Electrical Characteristics, the differential output voltage is nominally 350 mV over the complete output range. The minimum output voltage stays within the specified LVDS limits (247 mV to 454 mV) for a 3.3-V supply. If the supply range is between 2.4 V and 3 V, the minimum output voltage may be as low as 200 mV. If a communication link is designed to operate with a supply within this lower range, the channel noise margin will needtobelookedatcarefullytoensureerror-freeoperation. 10.2.1.2.2 DriverBypassCapacitance Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths between power and ground. At low frequencies, a good digital power supply offers very low-impedance paths between its terminals. However, as higher frequency currents propagate through power traces, the source is quiteoftenincapableofmaintainingalow-impedancepathtoground.Bypasscapacitorsareusedtoaddressthis shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board-level do a good job up into the kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. To solve this problem, one must resort to the use of smaller capacitors (nFtoμFrange)installedlocallynexttotheintegratedcircuit. Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes, atypicalcapacitorwithleadshasaleadinductancearound5nH. The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula according to Johnson, equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in supplycurrentof1AcoversthewholerangeofLVDSdevicesofferedbyTexasInstruments.Inthisexample,the maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget availableinyourdesign. (1) æDI ö Cchip=ç MaximumStepChangeSupplyCurrent÷´TRiseTime è DVMaximumPowerSupplyNoise ø (1) æ 1A ö CLVDS=ç ÷´200ps=0.001mF è0.2Vø (2) The following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of capacitanceascloseaspossibletothechip. Figure19. RecommendedLVDSBypassCapacitorLayout (1) HowardJohnson&MartinGraham.1993.HighSpeedDigitalDesign–AHandbookofBlackMagic.PrenticeHallPRT.ISBNnumber 013395724. 20 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 10.2.1.2.3 DriverInputVoltage The SN65LVDS1 input is designed to support a wide input voltage range. The input stage can accept signals as high as 5 V, independent of the supply voltage being used on the driver. This wide input range allows operation with 3.3-V and 5-V sources. While the input stage does support this wide input range, the driver will operate with a decision threshold of ~1.4 V. For LVTTL input signals, this threshold is well-matched to the voltages representing HI and LO logic levels. For 5-V TTL input signals and CMOS input signals, this fixed threshold at 1.4 V will result in some duty-cycle distortion. The level of the distortion is easily calculated based upon the input slew rate, as well as the signaling rate of the input data. Quite often this distortion is insignificant, although the designer should consider this effect where the device is operated at higher speeds, or when duty-cycle is a criticalfeature. 10.2.1.2.4 DriverOutputVoltage The SN65LVDS1 driver output is a 1.2-V common-mode voltage, with a nominal differential output signal of 350 mV. This 350 mV is the absolute value of the differential swing (V = |V+– V–|). The peak-to-peak differential OD voltage is twice this value, or 700 mV. As mentioned previously, the minimum differential output voltage is 200 mV when the supply voltage is between 2.4 V and 3 V. While 200 mV does not meet the minimum specified voltage for an LVDS-compliant driver, the designer may choose to employ this driver with a lower supply voltage, aslongasattentionispaidtothechannelnoisemargin. Aswewillseeshortly,LVDSreceiverthresholdsare ±100mV.Withthesereceiverdecisionthresholds,itisclear that the disadvantage of operating the driver with a lower supply will be noise margin. With fully compliant LVDS drivers and receivers, we would expect a minimum of ~150 mV of noise margin (247-mV minimum output voltage – 100-mV maximum input requirement). If we operate the SN65LVDS1 with a supply in the range of 2.4 Vto3V,theminimumnoisemarginwilldropto100mV(200mV – 100mV). 10.2.1.2.5 InterconnectingMedia The physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the LVDS standard, the key points which will be included here. This mediamaybeatwistedpair,twinax,flatribboncable,orPCBtraces. The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with variation no morethan10%(90 Ωto132 Ω). 10.2.1.2.6 PCBTransmissionLines As per SNLA187, Figure 20 depicts several transmission line structures commonly used in printed-circuit boards (PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. The dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmissionline). When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 20 shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by differentialsignals,thecoupledtransmissionlineisreferredtoasadifferentialpair.Thecharacteristicimpedance of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. When the two lines are immediately adjacent; for example, S is less than 2W, the differential pair is called a tightly- coupled differential pair. To maintain constant differential impedance along the length, it is important to keep the tracewidthandspacinguniformalongthelength,aswellasmaintaingoodsymmetrybetweenthetwolines. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Figure20. Controlled-ImpedanceTransmissionLines 10.2.1.2.7 TerminationResistor As shown earlier, an LVDS communication channel employs a current source driving a transmission line which is terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The designer should ensure that the termination resistance is within 10% of the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistance should be between90Ω and110Ω. The line termination resistance should be located as close as possible to the receiver, thereby minimizing the stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor into the receiver, which is exactly what is offered with the SN65LVDT2. The SN65LVDT2 provides all the functionality and performance of the SN65LVDS2 receiver, with the added feature of an integrated termination load. While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the transmission line. In such an environment, SN65LVDS2 receivers could be used for loads branching off the main bus,withanSN65LVDT2usedonlyatthebusend. 10.2.1.2.8 DriverNCPins NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimumthermalperformance,agoodruleofthumbistogroundtheNCpinsattheboardlevel. 22 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 10.2.1.2.9 ReceiverSupplyVoltage The SN65LVDS2 and SN65LVDT2 receivers are operated from a single supply. Like the SN65LVDS1, these devicescansupportoperationwithasupplyaslowas2.4Vandashighas3.6V.Themaineffectsoflowsupply voltage for these LVDS receivers will be seen in the receiver input common-mode range and the receiver output voltage.Wewilladdresstheseinturnbelow. 10.2.1.2.10 ReceiverBypassCapacitance BypasscapacitorsrecommendationshavebeendiscussedaboveinDriverBypassCapacitance. 10.2.1.2.11 ReceiverInputCommon-ModeRange The SN65LVDS2 and SN65LVDT2 support operation over an input common-mode range that is dependent upon the device supply voltage. Per the recommended conditions table, we see that operation is supported between 0 Vand0.8Vbelowthesupplyrail. For a supply voltage of 3.3 V, operation is available when the input common-mode voltage is between GND and 2.5V.Thereceiversarerequiredtomeetsensitivityrequirementsoverthewholecommon-modeinputrange. If we return to the transmitter discussions, we recall that the SN65LVDS1 has an output common-mode range of 1.2V.Usingoneofthereceiversdiscussedhere,weseethatvalidoperationofthecommunicationlinkwilloccur when the ground difference between transmitter and receiver is within ~±1 V . The use of differential signaling in LVDS allows operation in an environment where the combination of ground difference and common-mode noise result in a common-mode difference between transmitter and receiver of 1 V. This 1-V potential difference hints attheintendedapplicationofLVDScircuits. Standards such as RS-485 support potential differences of almost 10 V, allowing for communication over distances of greater than 1 km. The intended applications of LVDS devices is more moderate distances, such as those from chip to chip on a board, board to board in a rack, or from rack to nearby rack. When the 1-V potential difference is not adequate, yet the high-speed and low voltage features of LVDS are still needed, the designer can choose from either M-LVDS devices available from TI, or from LVDS devices with extended common-mode ranges,suchastheSN65LVDS33. 10.2.1.2.12 ReceiverInputSignal The LVDS receivers herein comply with the LVDS standard and correctly determine the bus state when the differential input voltage is greater than 100 mV (HI output) or less than –100 mV (LO output). In addition, the receiversoperatewithdifferentialinputvoltagesofupto600mV. 10.2.1.2.13 ReceiverOutputSignal Receiver outputs comply with LVTTL output voltage standards when the supply voltage is within the range of 3 V to3.6V.Whenthesupplyvoltageiswithinthelowerrangeof2.4Vto3V,thehighoutputvoltagecanbeaslow as 1.9 V. If a design intends to operate the receivers with a supply voltage in this lower range, care should be takentoensurethatthedevicebeingdrivenbythesedeviceswillbeabletooperatewithouterrorswiththelower outputvoltage. 10.2.1.2.14 ReceiverNCPins NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimumthermalperformance,agoodruleofthumbistogroundtheNCpinsattheboardlevel. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 10.2.2 ApplicationCurve Figure21. TypicalDriverOutputEyePatterninPoint-to-PointSystem 10.2.3 MultidropCommunications A second common application of LVDS buffers is a multidrop topology. In a multidrop configuration, a single driver and a shared bus are present, along with two or more receivers (with a maximum permissible number of 32receivers).Figure22belowshowsanexampleofamultidropsystem. Figure22. MultidropTopology 10.2.3.1 DesignRequirements DESIGNPARAMETERS EXAMPLEVALUE DriverSupplyVoltage(V ) 2.4to3.6V CCD DriverInputVoltage 0.8to5.0V DriverSignalingRate DCto400Mbps InterconnectCharacteristicImpedance 100Ω TerminationResistance 100Ω NumberofReceiverNodes 2to32 ReceiverSupplyVoltage(V ) 2.4to3.6V CCR ReceiverInputVoltage 0toV –0.8V CCR ReceiverSignalingRate DCto400Mbps Groundshiftbetweendriverandreceiver ±1V 24 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 10.2.3.2 DetailedDesignProcedure 10.2.3.2.1 InterconnectingMedia The interconnect in a multidrop system differs considerably from a point-to-point system. While point-to-point interconnects are straightforward, and well understood, the bus type architecture encountered with multidrop systemsrequiresmorecarefulattention.WewilluseFigure22abovetoexplorethesedetails. The most basic multidrop system would include a single driver, located at a bus origin, with multiple receiver nodes branching off the main line, and a final receiver at the end of the transmission line, co-located with a bus termination resistor. While this would be the most basic multidrop system, it has several considerations not yet explored. The location of the transmitter at one bus end allows the design concerns to be simplified, but this comes at the cost of flexibility. With a transmitter located at the origin, a single bus termination at the far-end is required. The far-end termination absorbs the incident traveling wave. The flexibility lost with this arrangement is thus: if the single transmitter needed to be relocated on the bus, at any location other than the origin, we would be faced with a bus with one open-circuited end, and one properly terminated end. Locating the transmitter say in the middleofthebusmaybedesiredtoreduce(by ½)themaximumflighttimefromthetransmittertoreceiver. Another new feature in Figure 22 is clear in that every node branching off the main line results in stubs. The stubs should be minimized in any case, but have the unintended effect of locally changing the loaded impedance ofthebus. To a good approximation, the characteristic transmission line impedance seen into any cut point in the unloaded multipoint or multidrop bus is defined by √L/C, where L is the inductance per unit length and C is the capacitance per unit length. As capacitance is added to the bus in the form of devices and interconnections, the bus characteristic impedance is lowered. This may result in signal reflections from the impedance mismatch between theunloadedandloadedsegmentsofthebus. If the number of loads is constant and can be distributed evenly along the line, reflections can be reduced by changing the bus termination resistors to match the loaded characteristic impedance. Normally, the number of loads are not constant or distributed evenly and the reflections resulting from any mismatching must be accountedforinthenoisebudget. 10.2.3.3 ApplicationCurve Figure23. TypicalDriverOutputEyePatterninMultidropSystem Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 11 Power Supply Recommendations The LVDS driver and receivers in this data sheet are designed to operate from a single power supply. Both drivers and receivers operate with supply voltages in the range of 2.4 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies would be used at each location. The expected ground potential difference between the driver power supply and the receiver power supply would be less than |±1 V|. Board level and local device level bypass capacitance shouldbeusedandarecoveredinDriverBypassCapacitanceandReceiverBypassCapacitance. 12 Layout 12.1 Layout Guidelines 12.1.1 Microstripvs.StriplineTopologies As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and stripline.MicrostripsaretracesontheouterlayerofaPCB,asshowninFigure24. Figure24. MicrostripTopology On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the necessary tolerances for Z based on the overall noise budget and reflection allowances. Footnotes 1, 2, and 3 O provideformulasforZ andt fordifferentialandsingle-endedtraces. (1) (2) (3) O PD Figure25. StriplineTopology (1) HowardJohnson&MartinGraham.1993.HighSpeedDigitalDesign–AHandbookofBlackMagic.PrenticeHallPRT.ISBNnumber 013395724. (2) MarkI.Montrose.1996.PrintedCircuitBoardDesignTechniquesforEMCCompliance.IEEEPress.ISBNnumber0780311310. (3) ClydeF.Coombs,Jr.Ed,PrintedCircuitsHandbook,McGrawHill,ISBNnumber0070127549. 26 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Layout Guidelines (continued) 12.1.2 DielectricTypeandBoardConstruction The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentallythroughseveraldesignsinvolvingLVDSdevices: • Copperweight:15gor1/2ozstart,platedto30gor1oz • Allexposedcircuitryshouldbesolder-plated(60/40)to7.62 μmor0.0003in(minimum). • Copperplatingshouldbe25.4μmor0.001in(minimum)inplated-through-holes. • Soldermaskoverbarecopperwithsolderhot-airleveling 12.1.3 RecommendedStackLayout Following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal planesasshowninFigure26. Figure26. Four-LayerPCBBoard NOTE The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. Oneofthemostcommonstackconfigurationsisthesix-layerboard,asshowninFigure27. Figure27. Six-LayerPCBBoard In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layersandreferencedplanes,inadditiontoensuringreferencetoagroundplaneforsignallayers1and6. 12.1.4 SeparationBetweenTraces The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the differentialpairofanLVDSlinktobenefitfromtheelectromagneticfieldcancellation.Thetracesshouldbe100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Layout Guidelines (continued) In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether the traces are edge-coupledorbroad-side-coupled. Figure28. 3-WRuleforSingle-EndedandDifferentialTraces(TopView) Youshouldexercisecautionwhenusingautorouters,becausetheydonotalwaysaccountforallfactorsaffecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signalpath.Usingsuccessive45° turnstendstominimizereflections. 12.1.5 CrosstalkandGroundBounceMinimization Toreducecrosstalk,itisimportanttoprovideareturnpathtohigh-frequencycurrentsthatisascloseaspossible to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic fieldstrength.Discontinuitiesinthegroundplaneincreasethereturnpathinductanceandshouldbeavoided. 28 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Layout Guidelines (continued) 12.1.6 Decoupling Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer tothetopoftheboardreducestheeffectivevialengthanditsassociatedinductance. Figure29. LowInductance,High-CapacitancePowerConnection Bypass capacitors should be placed close to V pins. They can be placed conveniently near the corners or DD underneath the package to minimize the loop area. This extends the useful frequency range of the added capacitance. Small-physical-size capacitors, such as 0402 or even 0201, or X7R surface-mount capacitors shouldbeusedtominimizebodyinductanceofcapacitors.Eachbypasscapacitorisconnectedtothepowerand groundplanethroughviastangenttothepadsofthecapacitorasshowninFigure30(a). An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30 MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB. Refer back to Figure 5-1 for some examples. Many high-speed devices provide a low-inductance GND connection on the backside of the package. This center dap must be connected to a ground plane through an array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of the small Surface Mount Technology (SMT) package. Placing vias around the perimeter of the dap connection ensures proper heat spreading and the lowest possible die temperature. Placing high-performance devices on opposing sides of the PCB using two GND planes (as shown in Figure 20) creates multiple paths for heat transfer. Often thermal PCB issues are the result of one device adding heat to another, resulting in a very high localtemperature.Multiplepathsforheattransferminimizethispossibility.InmanycasestheGNDdapthatisso important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad- to-dap spacing as shown in Figure 30(b). When this occurs, placing the decoupling capacitor on the backside of theboardkeepstheextrainductancetoaminimum.ItisimportanttoplacetheV viaasclosetothedevicepin DD aspossiblewhilestillallowingforsufficientsoldermaskcoverage.Iftheviaisleftopen,soldermayflowfromthe padandintotheviabarrel.Thiswillresultinapoorsolderconnection. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com Layout Guidelines (continued) Figure30. TypicalDecouplingCapacitorLayouts 12.2 Layout Example At least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as showninFigure31. Figure31. StaggeredTraceLayout This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 32. Note that vias create additionalcapacitance.Forexample,atypicalviahasalumpedcapacitanceeffectof1/2pFto1pFinFR4. Figure32. GroundViaLocation(SideView) 30 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 www.ti.com SLLS373L–JULY1999–REVISEDDECEMBER2014 Layout Example (continued) Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuitiesthatincreasereturningcurrentloopareas. To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the samearea,asopposedtomixingthemtogether,helpsreducesusceptibilityissues. Copyright©1999–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

SN65LVDS1,SN65LVDS2,SN65LVDT2 SLLS373L–JULY1999–REVISEDDECEMBER2014 www.ti.com 13 Device and Documentation Support 13.1 Device Support 13.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 13.1.2 OtherLVDSProducts For other products and application notes in the LVDS and LVDM product families visit our Web site at http://www.ti.com/sc/datatran. 13.2 Documentation Support 13.2.1 RelatedInformation IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for moreinformation. Formoreapplicationguidelines,seethefollowingdocuments: • ICPackageThermalMetrics (SPRA953) • Control-ImpedanceTransmissionLines(SNLA187) • MicrostripvsStriplineTopologies(SLLD009) 13.3 Related Links Table 5 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table5.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN65LVDS1 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDS2 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDT2 Clickhere Clickhere Clickhere Clickhere Clickhere 13.4 Trademarks RogersisatrademarkofRogersCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 32 SubmitDocumentationFeedback Copyright©1999–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS1 SN65LVDS2 SN65LVDT2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVDS1D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS1 & no Sb/Br) SN65LVDS1DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SAAI & no Sb/Br) SN65LVDS1DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SAAI & no Sb/Br) SN65LVDS1DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SAAI & no Sb/Br) SN65LVDS1DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SAAI & no Sb/Br) SN65LVDS1DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS1 & no Sb/Br) SN65LVDS2D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM LVDS2 & no Sb/Br) SN65LVDS2DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SABI & no Sb/Br) SN65LVDS2DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SABI & no Sb/Br) SN65LVDS2DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SABI & no Sb/Br) SN65LVDS2DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SABI & no Sb/Br) SN65LVDS2DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS2 & no Sb/Br) SN65LVDT2D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM LVDT2 & no Sb/Br) SN65LVDT2DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SACI & no Sb/Br) SN65LVDT2DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SACI & no Sb/Br) SN65LVDT2DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SACI & no Sb/Br) SN65LVDT2DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SACI & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVDT2DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM LVDT2 & no Sb/Br) SN65LVDT2DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT2 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LVDS1DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN65LVDS1DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN65LVDS1DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDS2DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN65LVDS2DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN65LVDS2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDT2DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 SN65LVDT2DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 SN65LVDT2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LVDS1DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN65LVDS1DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN65LVDS1DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDS2DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN65LVDS2DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN65LVDS2DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDT2DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 SN65LVDT2DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 SN65LVDT2DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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