Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 SNx5LVDS3xxxx High-Speed Differential Line Receivers 1 Features 3 Description • MeetorExceedtheRequirementsofANSI The SN55LVDS32, SN65LVDS32, SN65LVDS3486, 1 and SN65LVDS9637 devices are differential line TIA/EIA-644Standard receivers that implement the electrical characteristics • OperateWithaSingle3.3-VSupply of low-voltage differential signaling (LVDS). This • DesignedforSignalingRatesofupto150Mbps signaling technique lowers the output voltage levels (See) of 5-V differential standard levels (such as EIA/TIA- 422B) to reduce the power, increase the switching • DifferentialInputThresholds±100mVMax speeds, and allow operation with a 3.3-V supply rail. • TypicalPropagationDelayTimeof2.1ns Any of the differential receivers provides a valid • PowerDissipation60mWTypicalPerReceiverat logical output state with a ±100-mV differential input MaximumDataRate voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of • Bus-TerminalESDProtectionExceeds8kV ground potential difference between two LVDS • Low-VoltageTTL(LVTTL)LogicOutputLevels nodes. • PinCompatibleWithAM26LS32,MC3486,and μA9637 DeviceInformation(1) • Open-CircuitFail-Safe PARTNUMBER PACKAGE BODYSIZE(NOM) • ColdSparingforSpaceandHigh-Reliability LCCC(20) 8.89mm×8.89mm ApplicationsRequiringRedundancy SN55LVDS32 CDIP(16) 19.56mm×6.92mm CFP(16) 10.30mm×6.73mm 2 Applications SOIC(16) 9.90mm×3.91mm • WirelessInfrastructure SN65LVDS32 SOP(16) 10.30mm×5.30mm • TelecomInfrastructure TSSOP(16) 5.50mm×4.40mm • Printer SOIC(16) 9.90mm×3.91mm SN65LVDS3486 TSSOP(16) 5.50mm×4.40mm SOIC(8) 4.90mm×3.91mm SN65LVDS9637 VSSOP(8) 3.00mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. EquivalentInputandOutputSchematicDiagrams EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF G, G, 1,2EN OR TYPICAL OF ALL OUTPUTS 3,4EN INPUTS VCC VCC VCC 300 kW 300 kW 50 W 5 W Input Y Output A Input B Input 7 V 7 V 7 V 7 V 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 10.1 Overview...............................................................15 2 Applications........................................................... 1 10.2 FunctionalBlockDiagram.....................................15 3 Description............................................................. 1 10.3 FeatureDescription...............................................15 10.4 DeviceFunctionalModes......................................17 4 RevisionHistory..................................................... 2 11 ApplicationandImplementation........................ 18 5 Description(Continued)........................................ 3 11.1 ApplicationInformation..........................................18 6 DeviceOptions....................................................... 3 11.2 TypicalApplication................................................18 7 PinConfigurationandFunctions......................... 4 12 PowerSupplyRecommendations..................... 23 8 Specifications......................................................... 7 13 Layout................................................................... 23 8.1 AbsoluteMaximumRatings......................................7 13.1 LayoutGuidelines.................................................23 8.2 ESDRatings..............................................................7 13.2 LayoutExample....................................................25 8.3 RecommendedOperatingConditions.......................7 14 DeviceandDocumentationSupport................. 27 8.4 ThermalInformation..................................................8 14.1 DeviceSupport......................................................27 8.5 ElectricalCharacteristics:SN55LVDS32..................9 14.2 DocumentationSupport........................................27 8.6 ElectricalCharacteristics:SN65LVDSxxxx...............9 14.3 RelatedLinks........................................................27 8.7 SwitchingCharacteristics:SN55LVDS32...............10 14.4 Trademarks...........................................................27 8.8 SwitchingCharacteristics:SN65LVDSxxxx............10 14.5 ElectrostaticDischargeCaution............................27 8.9 TypicalCharacteristics............................................11 14.6 Glossary................................................................27 9 ParameterMeasurementInformation................12 15 Mechanical,Packaging,andOrderable 10 DetailedDescription........................................... 15 Information........................................................... 28 4 Revision History ChangesfromRevisionQ(July2007)toRevisionR Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 2 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 5 Description (Continued) The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of datatransferdependsontheattenuationcharacteristicsofthemediaandthenoisecouplingtotheenvironment. The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are characterized for operation from –40°C to 85°C.TheSN55LVDS32deviceischaracterizedforoperationfrom –55°Cto125°C. 6 Device Options MaximumRecommendedOperatingSpeeds PARTNUMBER ALLRxACTIVE SN65LVDS32 100Mbps SN65LVDS3486 100Mbps SN65LVDS9637 150Mbps Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 7 Pin Configuration and Functions SN55LVDS32...J OR W SN65LVDS32...D OR PW (Marked as LVDS32 or 65LVDS32) (TOP VIEW) 1B 1 16 VCC 1A 2 15 4B 1Y 3 14 4A G 4 13 4Y 2Y 5 12 G 2A 6 11 3Y 2B 7 10 3A GND 8 9 3B SN55LVDS32FK (TOP VIEW) C A B C CB 1 1 N V 4 3 2 1 20 19 1Y 4 18 4A G 5 17 4Y NC 6 16 NC 2Y 7 15 G 2A 8 14 3Y 9 10 11 12 13 B D C B A 2 N N 3 3 G SN65LVDS3486D (Marked as LVDS3486) (TOP VIEW) 1B 1 16 VCC 1A 2 15 4B 1Y 3 14 4A 1,2EN 4 13 4Y 2Y 5 12 3,4EN 2A 6 11 3Y 2B 7 10 3A GND 8 9 3B SN65LVDS9637D (Marked as DK637 or LVDS37) SN65LVDS9637DGN (Marked as L37) SN65LVDS9637DGK (Marked as AXF) (TOP VIEW) VCC 1 8 1A 1Y 2 7 1B 2Y 3 6 2A GND 4 5 2B 4 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 PinFunctions:SNx5LVDS32xx PIN I/O DESCRIPTION NAME NUMBER V 16 – Supplyvoltage CC GND 8 – Ground 1A 2 I Differential(LVDS)non-invertinginput 1B 1 I Differential(LVDS)invertinginput 1Y 3 O LVTTLoutputsignal 2A 6 I Differential(LVDS)non-invertinginput 2B 7 I Differential(LVDS)invertinginput 2Y 5 O LVTTLoutputsignal 3A 10 I Differential(LVDS)non-invertinginput 3B 9 I Differential(LVDS)invertinginput 3Y 11 O LVTTLoutputsignal 4A 14 I Differential(LVDS)non-invertinginput 4B 15 I Differential(LVDS)invertinginput 4Y 13 O LVTTLoutputsignal G 4 I Enable(HI=ENABLE) G/ 12 I Enable(LO=ENABLE) PinFunctions:SN55LVDS32FK PIN I/O DESCRIPTION NAME NUMBER V 20 – Supplyvoltage CC GND 10 – Ground 1A 3 I Differential(LVDS)non-invertinginput 1B 2 I Differential(LVDS)invertinginput 1Y 4 O LVTTLoutputsignal 2A 8 I Differential(LVDS)non-invertinginput 2B 9 I Differential(LVDS)invertinginput 2Y 7 O LVTTLoutputsignal 3A 13 I Differential(LVDS)non-invertinginput 3B 12 I Differential(LVDS)invertinginput 3Y 14 O LVTTLoutputsignal 4A 18 I Differential(LVDS)non-invertinginput 4B 19 I Differential(LVDS)invertinginput 4Y 17 O LVTTLoutputsignal G 5 I Enable(HI=ENABLE) G/ 15 I Enable(LO=ENABLE) NC 1,6,11,16 – Noconnection Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com PinFunctions:SN65LVDS3486D PIN I/O DESCRIPTION NAME NUMBER V 16 – Supplyvoltage CC GND 8 – Ground 1A 2 I Differential(LVDS)non-invertinginput 1B 1 I Differential(LVDS)invertinginput 1Y 3 O LVTTLoutputsignal 2A 6 I Differential(LVDS)non-invertinginput 2B 7 I Differential(LVDS)invertinginput 2Y 5 O LVTTLoutputsignal 3A 10 I Differential(LVDS)non-invertinginput 3B 9 I Differential(LVDS)invertinginput 3Y 11 O LVTTLoutputsignal 4A 14 I Differential(LVDS)non-invertinginput 4B 15 I Differential(LVDS)invertinginput 4Y 13 O LVTTLoutputsignal 1,2EN 4 I Enableforchannels1and2 3,4EN 12 I Enableforchannels3and4 PinFunctions:SN65LVDS9637Dxx PIN I/O DESCRIPTION NAME NUMBER V 1 – Supplyvoltage CC GND 4 – Ground 1A 8 I Differential(LVDS)non-invertinginput 1B 7 I Differential(LVDS)invertinginput 1Y 2 O LVTTLoutputsignal 2A 6 I Differential(LVDS)non-invertinginput 2B 5 I Differential(LVDS)invertinginput 2Y 3 O LVTTLoutputsignal 6 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 8 Specifications 8.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange(2) –0.5 4 V CC Enablesandoutput –0.5 V +0.5 V CC V Inputvoltagerange I AorB –0.5 4 V SeeThermal Continuoustotalpowerdissipation Information T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltages,exceptdifferentialI/Obusvoltages,arewithrespecttothenetworkgroundterminal. 8.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,bus (ESD) pins(1) ±8000 V Leadtemperature1.6mm(1/16inch)fromcasefor10seconds 260 °C (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 8.3 Recommended Operating Conditions MIN NOM MAX UNIT V Supplyvoltage 3 3.3 3.6 CC V High-levelinputvoltage G,G,1,2EN,or3,4EN 2 IH V Low-levelinputvoltage G,G,1,2EN,or3,4EN 0.8 IL |V | Magnitudeofdifferentialinputvoltage 0.1 0.6 ID V V Common-modeinputvoltage(seeFigure1) |VID| 2.4(cid:1)|VID| IC 2 2 V –0.8 CC SN65prefix –40 85 T Operatingfree-airtemperature °C A SN55prefix –55 125 Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 2.5 V e - g an 2 Max at VCC> 3.15 V R e ag Max at VCC= 3 V olt 1.5 V ut p n e I od 1 M n- o m m o 0.5 C - Min C VI 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VID- Differential Input Voltage - V Figure1. V vsV andV IC ID CC 8.4 Thermal Information SN55LVDS32 SN65LVDS32, SN65LVDS9637 SN65LVDS3486 THERMALMETRIC(1) UNIT FK J W D NS PW D DGK 20PINS 16PINS 16PINS 8PINS R Junction-to-ambientthermal θJA 76.4 88.7 111.5 177.5 resistance R Junction-to-case(top)thermal θJC(top) 38.0 46.8 46.4 65.6 resistance R Junction-to-boardthermal θJB 33.7 49.1 56.6 97.3 °C/W resistance ψ Junction-to-topcharacterization JT 7.6 12.5 5.5 8.9 parameter ψ Junction-to-boardcharacterization JB 33.5 48.8 56.1 95.8 parameter DeratingFactorAboveT =25°C 11.0 11.0 8.0 7.6 – 6.2 5.8 3.4 mW/°C A T ≤25°C 1375 1375 1000 950 – 774 725 425 A Power TA≤70°C 880 880 640 608 – 496 464 272 mW Rating T ≤85°C 715 715 520 494 – 402 377 221 A T ≤125°C 275 275 200 – – – – – A (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 8 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 8.5 Electrical Characteristics: SN55LVDS32 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT V Positive-goingdifferentialinputvoltage SeeFigure7,Table1,and (2) 100 mV ITH+ threshold VITH– Ntheregsahtiovled-(g3o)ingdifferentialinputvoltage SeeFigure7,Table1,and (2) –100 mV V High-leveloutputvoltage I =–8mA 2.4 V OH OH V Low-leveloutputvoltage I =8mA 0.4 V OL OL Enabled,Noload 10 18 I Supplycurrent mA CC Disabled 0.25 0.5 V =0 –2 –10 –20 I I Inputcurrent(AorBinput) μA I V =2.4V –1.2 –3 I I Power-offinputcurrent(AorBinput) V =0,V =2.4V 6 20 μA I(OFF) CC I I High-levelinputcurrent(EN,G,orGinput) V =2V 10 μA IH IH I Low-levelinputcurrent(EN,G,orGinput) V =0.8V 10 μA IL IL I High-impedanceoutputcurrent V =0orV ±12 μA OZ O CC (1) AlltypicalvaluesareatT =25°CandwithV =3.3V. A CC (2) |V |=200mVforoperationat–55°C ITH (3) Thealgebraicconvention,inwhichtheless-positive(more-negative)limitisdesignatedminimum,isusedinthisdatasheetforthe negative-goingdifferentialinputvoltagethresholdonly. 8.6 Electrical Characteristics: SN65LVDSxxxx overrecommendedoperatingconditions(unlessotherwisenoted) SN65LVDS32 SN65LVDS3486 PARAMETER TESTCONDITIONS SN65LVDS9637 UNIT MIN TYP(1) MAX Positive-goingdifferentialinputvoltage V SeeFigure7andTable1 100 mV IT+ threshold Negative-goingdifferentialinputvoltage VIT– threshold(2) SeeFigure7andTable1 –100 mV I =–8mA 2.4 OH V High-leveloutputvoltage V OH I =–4mA 2.8 OH V Low-leveloutputvoltage I =8mA 0.4 V OL OL SN65LVDS32, Enabled,Noload 10 18 I Supplycurrent SN65LVDS3486 Disabled 0.25 0.5 mA CC SN65LVDS9637 Noload 5.5 10 V =0 –2 –10 –20 I I Inputcurrent(AorBinputs) μA I V =2.4V –1.2 –3 I I Power-offinputcurrent(AorBinput) V =0,V =3.6V 6 20 μA I(OFF) CC I I High-levelinputcurrent(EN,G,orGinput) V =2V 10 μA IH IH I Low-levelinputcurrent(EN,G,orGinput) V =0.8V 10 μA IL IL I High-impedanceoutputcurrent V =0orV ±10 μA OZ O CC (1) AlltypicalvaluesareatT =25°CandwithV =3.3V. A CC (2) Thealgebraicconvention,inwhichtheless-positive(more-negative)limitisdesignatedminimum,isusedinthisdatasheetforthe negative-goingdifferentialinputvoltagethresholdonly. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 8.7 Switching Characteristics: SN55LVDS32 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Propagationdelaytime,low-to-high-leveloutput 1.3 2.3 6 ns PLH t Propagationdelaytime,high-to-low-leveloutput 1.4 2.2 6.1 ns PHL t Channel-to-channeloutputskew(1) CL=10pF, 0.1 ns sk(o) SeeFigure8 t Outputsignalrisetime,20%to80% 0.6 ns r t Outputsignalfalltime,80%to20% 0.7 ns f t Propagationdelaytime,high-level-to-high- 6.5 12 ns PHZ impedanceoutput t Propagationdelaytime,low-level-to-high- 5.5 12 ns PLZ impedanceoutput SeeFigure9 t Propagationdelaytime,high-impedance-to-high- 8 14 ns PZH leveloutput t Propagationdelaytime,high-impedance-to-low- 3 12 ns PZL leveloutput (1) t isthemaximumdelaytimedifferencebetweendriversonthesamedevice. sk(o) 8.8 Switching Characteristics: SN65LVDSxxxx overrecommendedoperatingconditions(unlessotherwisenoted) SN65LVDS32 SN65LVDS3486 PARAMETER TESTCONDITIONS SN65LVDS9637 UNIT MIN TYP MAX t Propagationdelaytime,low-to-high-leveloutput 1.5 2.1 3 ns PLH t Propagationdelaytime,high-to-low-leveloutput 1.5 2.1 3 ns PHL t Pulseskew(|t –t |) 0 0.4 ns sk(p) PHL PLH t Channel-to-channeloutputskew(1) CL=10pF, 0.1 0.3 ns sk(o) SeeFigure8 t Part-to-partskew(2) 1 ns sk(pp) t Outputsignalrisetime,20%to80% 0.6 ns r t Outputsignalfalltime,80%to20% 0.7 ns f t Propagationdelaytime,high-level-to-high- 6.5 12 ns PHZ impedanceoutput t Propagationdelaytime,low-level-to-high- 5.5 12 ns PLZ impedanceoutput SeeFigure9 t Propagationdelaytime,high-impedance-to-high- 8 12 ns PZH leveloutput t Propagationdelaytime,high-impedance-to-low- 3 12 ns PZL leveloutput (1) t istheskewbetweenspecifiedoutputsofasingledevicewithalldrivinginputsconnectedtogetherandtheoutputsswitchinginthe sk(o) samedirectionwhiledrivingidenticalspecifiedloads. (2) t isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsoftwodeviceswhenbothdevices sk(pp) operatewiththesamesupplyvoltages,sametemperature,andhaveidenticalpackagesandtestcircuits. 10 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 8.9 Typical Characteristics 85 s 2.7 FPoeur rF Rigeucreei v3e, rSsw, Litochadinegd VCC = 3.6 V e − n ms) 75 Simultaneously VCC = 3.3 V ay Tim 2.5 VCC = 3 V y Current − mA (r 546555 VCC = 3 V h Propagation Del 22..13 VCC =V 3C.C6 =V 3.3 V − Suppl 35 w-to-Hig 1.9 C o C L I 25 − D) 1.7 H( L 15 P 1.5 50 100 150 200 t −50 0 50 100 f − Frequency − MHz TA − Free-Air Temperature − °C Figure2.SN55LVDS32,SN65LVDS32SupplyCurrentvs Figure3.Low-to-HighPropagationDelayTimevsFree-Air Frequency Temperature s 2.7 3.5 n − e w Propagation Delay Tim 222...135 VCC = 3 V vel Output Voltage − V 1223....5050 − High-to-LoD) 11..97 VCC = 3.6 V VCC = 3.3 V V− High-LeOH 01..50 L( H P 1.5 0.0 t −50 0 50 100 −60 −50 −40 −30 −20 −10 0 TA − Free-Air Temperature − °C IOH − High-Level Output Current − mA Figure4.High-to-LowPropagationDelayTimevsFree-Air Figure5.High-LevelOutputVoltagevsHigh-LevelOutput Temperature Current 5.0 4.5 V − 4.0 e g a 3.5 olt V ut 3.0 p Out 2.5 el ev 2.0 L ow- 1.5 L − L 1.0 O V 0.5 0.0 0 10 20 30 40 50 60 70 80 IOL − Low-Level Output Current − mA Figure6.High-LevelOutputVoltagevsLow-LevelOutputCurrent Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 9 Parameter Measurement Information A Y VID B VIA (VIA + VIB)/2 VIC VIB VO Figure7. VoltageDefinitions Table1.ReceiverMinimumandMaximumInputThresholdTestVoltages RESULTINGDIFFERENTIAL RESULTINGCOMMON-MODE APPLIEDVOLTAGES INPUTVOLTAGE INPUTVOLTAGE V (V) V (V) V (mV) V (V) IA IB ID IC 1.25 1.15 100 1.2 1.15 1.25 –100 1.2 2.4 2.3 100 2.35 2.3 2.4 –100 2.35 0.1 0 100 0.05 0 0.1 –100 0.05 1.5 0.9 600 1.2 0.9 1.5 –600 1.2 2.4 1.8 600 2.1 1.8 2.4 –600 2.1 0.6 0 600 0.3 0 0.6 –600 0.3 12 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 VID VIA VIB CL = 10 pF VO VIA 1.4 V VIB 1 V 0.4 V VID 0 -0.4 V tPHL tPLH 80% 80% VOH VO 20% 1.4 V 20% VOL tf tr A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=50Mpps,pulsewidth=10±0.2ns. B. C includesinstrumentationandfixturecapacitancewithin6mmofthedeviceundertest. L Figure8. TimingTestCircuitandWaveforms Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com B 1.2 V 500 W A 10 pF ± G (see Note B) VO Inputs (see Note A) G VTEST 1,2EN or 3,4EN 2.5 V VTEST A 1 V 2 V G, 1,2EN, 1.4 V or 3,4EN 0.8 V 2 V 1.4 V G 0.8 V tPLZ tPLZ tPZL tPZL 2.5 V 1.4 V Y VOL + 0.5 V VOL VTEST 0 1.4 V A 2 V G, 1,2EN, 1.4 V or 3,4EN 0.8 V 2 V 1.4 V G 0.8 V tPHZ tPHZ tPZH tPZH VOH VOH - 0.5 V Y 1.4 V 0 A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=0.5Mpps,pulsewidth=500±10ns. B. C includesinstrumentationandfixturecapacitancewithin6mmofthedeviceundertest. L Figure9. EnableorDisableTimeTestCircuitandWaveforms 14 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 10 Detailed Description 10.1 Overview The SNx5LVDSxx devices are LVDS line receivers. They operate from a single supply that is nominally 3.3 V, but can be as low as 3.0 V and as high as 3.6 V. The input signals to the SNx5LVDSxx device are differential LVDS signals. The output of the device is an LVTTL digital signal. This LVDS receiver requires a ±100-mV input signal to determine the correct state of the received signal. Compliant LVDS receivers can accept input signals with a common-mode range between 0.05 V and 2.35 V. As the common-mode output voltage of an LVDS driver is 1.2 V, the SNx5LVDSxx correctly determines the line state when operated with a 1-V ground shift between driverandreceiver. 10.2 Functional Block Diagram ’LVDS32 logic diagram SN65LVDS3486D logic diagram SN65LVDS9637D logic diagram (positive logic) (positive logic) (positive logic) G 4 1A 2 3 1A 8 2 12 1 1Y 7 1Y G 1B 1B 4 2 1,2EN 6 1A 3 2A 3 1 1Y 6 5 2Y 1B 2A 5 2B 7 2Y 6 2B 2A 5 7 2Y 2B 10 3A 11 10 3Y 3A 11 9 3Y 3B 9 3B 12 3,4EN 14 4A 13 14 15 4Y 4A 13 4B 15 4Y 4B 10.3 Feature Description 10.3.1 ReceiverOutputStates When the receiver differential input signal is greater than 100 mV, the receiver output is high; and when the differential input voltage is below –100 mV, the receiver output is low. When the input voltage is between these thresholds (for example, between –100 mV and 100 mV), the receiver output is indeterminate. It may be high or low. A special case occurs when the input to the receiver is open-circuited, which is covered in Receiver Open- CircuitFail-Safe.Whenthereceiverisdisabled,thereceiveroutputswillbehigh-impedance. 10.3.2 ReceiverOpen-CircuitFail-Safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. However, the SNx5LVDSxx receiver is different inhowithandlestheopen-inputcircuitsituation. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal to V through a 300-kΩ resistor as shown in Figure 10. The fail-safe feature uses CC an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high levelregardlessofthedifferentialinputvoltage. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com Feature Description (continued) VCC 300 kW 300 kW A Rt = 100 W (Typ) Y B VIT ≈ 2.3 V Figure10. Open-CircuitFailSafeoftheLVDSReceiver It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt does not affect the fail-safe function as long as it isconnectedasshowninFigure10.Otherterminationcircuitsmayallowadc-currenttogroundthatcoulddefeat thepullupcurrentsfromthereceiverandthefail-safefeature. 10.3.3 Common-ModeRangevsSupplyVoltage The SNx5LVDSxx receivers operate over an input common-mode range of ½ × V V to 2.4 – ½ × V V. If the ID ID input signal is anywhere within this range and has a differential magnitude greater than or equal to 100 mV, the receiverscorrectlyoutputtheLVDSbusstate. 10.3.4 GeneralPurposeComparator While the SNx5LVDSxx receivers are LVDS standard-compliant receivers, their utility and applications extend to a wider range of signals. As long as the input signals are within the required differential and common-mode voltagerangesmentionedabove,thereceiveroutputwillbeafaithfulrepresentationoftheinputsignal. 10.3.5 ReceiverEquivalentSchematics The receiver equivalent input and output schematic diagrams are shown in Figure 11. The receiver input is a high-impedance differential pair. 7-V Zener diodes are included on each input to provide ESD protection. The receiveroutputstructureshownisaCMOSinverterwithanadditionalZenerdiode,againforESDprotection. EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF G, G, 1,2EN OR TYPICAL OF ALL OUTPUTS 3,4EN INPUTS VCC VCC VCC 300 kW 300 kW 50 W 5 W Input Y Output A Input B Input 7 V 7 V 7 V 7 V Figure11. EquivalentInputandOutputSchematicDiagrams 16 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 10.4 Device Functional Modes SN55LVDS32,SN65LVDS32(1) SN65LVDS3486(1) DIFFERENTIALINPUT ENABLES OUTPUT DIFFERENTIALINPUT ENABLE OUTPUT A,B G G Y A,B EN Y H X H V ≥100mV V ≥100mV H H ID X L H ID H X ? –100mV<V <100mV –100mV<V <100mV H ? ID X L ? ID H X L V ≤–100mV V ≤–100mV H L ID X L L ID X L H Z X L Z H X H Open Open H H X L H (1) H=highlevel,L=lowlevel,X=irrelevant,Z=high-impedance(off),?=indeterminate SN55LVDS32, SN65LVDS32 SN65LVDS3486 4 G 4 ≥1 1, 2EN EN 12 EN 2 G 1A 3 1 1Y 1B 6 2A 5 1A 2 3 7 2Y 2B 1 1Y 1B 12 6 5 3, 4EN EN 2A 2Y 7 10 2B 3A 11 10 11 9 3Y 3A 3Y 3B 9 14 3B 4A 13 4A 1145 13 4Y 4B 15 4Y 4B This symbol is in accordance withANSI/IEEE Std 91-1984 and IEC Publication 617-12. Figure12. SN55LVDS32,SN65LVDS32,andSN65LVDS3486LogicSymbols Table2.FunctionTableSN65LVDS9637(1) DIFFERENTIALINPUT OUTPUT A,B Y V ≥100mV H ID –100mV<V <100mV ? ID V ≤–100mV L ID Open H (1) H=highlevel,L=lowlevel,?=indeterminate SN65LVDS9637 8 1A 2 7 1Y 1B 6 2A 3 5 2Y 2B Thissymbol is in accordance withANSI/IEEE Std 91-1984 and IEC Publication617-12. Figure13. SN65LVDS9637LogicSymbol Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 11.1 Application Information The SNx5LVDSxx devices are LVDS receivers. These devices are generally used as building blocks for high- speed, point-to-point, data transmission where ground differences are less than 1 V. LVDS drivers and receivers provide high-speed signaling rates that are often implemented with ECL class devices without the ECL power anddual-supplyrequirements. 11.2 Typical Application 11.2.1 Point-to-PointCommunications The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of digitaldata,asshowninFigure14. Figure14. Point-to-PointTopology A point-to-point communications channel has a single transmitter (driver) and a single receiver. This communications topology is often referred to as simplex. In Figure 14 the driver receives a single-ended input signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended input to a differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while translating to a signal whose features are more appropriate for communication over extended distances or in a noisyenvironment. 11.2.1.1 DesignRequirements DESIGNPARAMETERS EXAMPLEVALUE DriverSupplyVoltage(V ) 3.0to3.6V CCD DriverInputVoltage 0.8to3.3V DriverSignalingRate DCto100Mbps InterconnectCharacteristicImpedance 100Ω TerminationResistance 100Ω NumberofReceiverNodes 1 ReceiverSupplyVoltage(V ) 3.0to3.6V CCR ReceiverInputVoltage 0to24V ReceiverSignalingRate DCto100Mbps Groundshiftbetweendriverandreceiver ±1V 18 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 11.2.1.2 DetailedDesignProcedure 11.2.1.2.1 Equipment • HewlettPackardHP6624ADCpowersupply • TektronixTDS7404RealTimeScope • AgilentParBERTE4832A Hewlett Packard HP6624A DC Power Supply Agilent ParBERT (E4832A) Tektronix TDS7404 Bench Test Board Real Time Scope Figure15. EquipmentSetup 11.2.1.2.2 DriverSupplyVoltage An LVDS driver is operated from a single supply. The device can support operation with a supply as low as 3 V and as high as 3.6 V. The differential output voltage is nominally 340 mV over the complete output range. The minimumoutputvoltagestayswithinthespecifiedLVDSlimits(247mVto454mV)fora3.3-Vsupply. 11.2.1.2.3 DriverBypassCapacitance Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths between power and ground. At low frequencies, a good digital power supply offers very-low-impedance paths between its terminals. However, as higher frequency currents propagate through power traces, the source is quiteoftenincapableofmaintainingalow-impedancepathtoground.Bypasscapacitorsareusedtoaddressthis shortcoming. Usually, large bypass capacitors (10 µF to 1000 μF) at the board-level do a good job up into the kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. To solve this problem, one should resort to the use of smaller capacitors (nFtoμFrange)installedlocallynexttotheintegratedcircuit. Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes, atypicalcapacitorwithleadshasaleadinductancearound5nH. The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula according to Johnson, equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in supplycurrentof1AcoversthewholerangeofLVDSdevicesofferedbyTexasInstruments.Inthisexample,the maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget availableinyourdesign. (1) æDI ö Cchip=ç MaximumStepChangeSupplyCurrent÷´TRiseTime è DVMaximumPowerSupplyNoise ø (1) (1) HowardJohnson&MartinGraham.1993.HighSpeedDigitalDesign–AHandbookofBlackMagic.PrenticeHallPRT.ISBNnumber 013395724. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com æ 1A ö CLVDS=ç ÷´200ps=0.001mF è0.2Vø (2) The following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of capacitanceascloseaspossibletothechip. Figure16. RecommendedLVDSBypassCapacitorLayout 11.2.1.2.4 DriverOutputVoltage A standard-compliant LVDS driver output is a 1.2-V common-mode voltage, with a nominal differential output signal of 340 mV. This 340 mV is the absolute value of the differential swing (V = |V+ – V–|). The peak-to-peak OD differentialvoltageistwicethisvalue,or680mV. 11.2.1.2.5 InterconnectingMedia The physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the LVDS standard, the key points which will be included here. This media may be a twisted pair, twinax, flat ribbon cable, or PCB traces. The nominal characteristic impedance of theinterconnectshouldbebetween100 Ω and120Ω withavariationofnomorethan10%(90 Ω to132Ω). 11.2.1.2.6 PCBTransmissionLines As per SNLA187, Figure 17 depicts several transmission line structures commonly used in printed-circuit boards (PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. The dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmissionline). When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 17 shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by differentialsignals,thecoupledtransmissionlineisreferredtoasadifferentialpair.Thecharacteristicimpedance of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. When the two lines are immediately adjacent; for example, S is less than 2W, the differential pair is called a tightly- coupled differential pair. To maintain constant differential impedance along the length, it is important to keep the tracewidthandspacinguniformalongthelength,aswellasmaintaingoodsymmetrybetweenthetwolines. 20 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 Figure17. Controlled-ImpedanceTransmissionLines 11.2.1.2.7 TerminationResistor AnLVDScommunicationchannelemploysacurrentsourcedrivingatransmissionlinewhichisterminatedwitha resistive load. This load serves to convert the transmitted current into a voltage at the receiver input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The designer should ensure that the termination resistance is within 10% of the nominal media characteristic impedance. If the transmissionlineistargetedfor100-Ω impedance,theterminationresistanceshouldbebetween90and110 Ω. The line termination resistance should be located as close as possible to the receiver, thereby minimizing the stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor intothereceiver,whichisexactlywhatisofferedwithadeviceliketheSN65LVDT386. While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the transmission line. In such an environment, LVDS receivers could be used for loads branching off the main bus withanLVDTreceiverusedonlyatthebusend. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 11.2.1.3 ApplicationCurves AllRxrunningat100Mbps; T=25°C AllRxrunningat100Mbps; T=25°C Channel1:1Y VCC=3.6V Channel1:1Y VCC=3.6V Channel2:2Y PRBS=223–1 Channel2:2Y PRBS=223–1 Channel3:3Y Channel3:3Y Channel4:4Y Channel4:4Y Figure18.TypicalEyePatternsSN65LVDS32 Figure19.TypicalEyePatternsSN65LVDS3486 AllRxrunningat150Mbps; T=25°C Channel1:1Y V =3.6V CC Channel2:2Y PRBS=223–1 Figure20.TypicalEyePatternsSN65LVDS9637 22 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 12 Power Supply Recommendations The LVDS driver and receivers in this data sheet are designed to operate from a single power supply. Both drivers and receivers operate with supply voltages in the range of 2.4 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies would be used at each location. The expected ground potential difference between the driver power supply and the receiver power supply would be less than |±1 V|. Board-level and local device-level bypass capacitance shouldbeusedandarecoveredinDriverBypassCapacitance. 13 Layout 13.1 Layout Guidelines 13.1.1 Microstripvs.StriplineTopologies As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and stripline.MicrostripsaretracesontheouterlayerofaPCB,asshowninFigure21. Figure21. MicrostripTopology On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the necessary tolerances for Z based on the overall noise budget and reflection allowances. Footnotes 2, 3, and 4 O provideformulasforZ andt fordifferentialandsingle-endedtraces. (1) (2) (3) O PD Figure22. StriplineTopology (1) HowardJohnson&MartinGraham.1993.HighSpeedDigitalDesign–AHandbookofBlackMagic.PrenticeHallPRT.ISBNnumber 013395724. (2) MarkI.Montrose.1996.PrintedCircuitBoardDesignTechniquesforEMCCompliance.IEEEPress.ISBNnumber0780311310. (3) ClydeF.Coombs,Jr.Ed,PrintedCircuitsHandbook,McGrawHill,ISBNnumber0070127549. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com Layout Guidelines (continued) 13.1.2 DielectricTypeandBoardConstruction The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentallythroughseveraldesignsinvolvingLVDSdevices: • Copperweight:15gor1/2ozstart,platedto30gor1oz. • Allexposedcircuitryshouldbesolder-plated(60/40)to7.62 μmor0.0003in(minimum). • Copperplatingshouldbe25.4μmor0.001in(minimum)inplated-through-holes. • Soldermaskoverbarecopperwithsolderhot-airleveling 13.1.3 RecommendedStackLayout Following the choice of dielectrics and design specifications, you should decide how many levels to use in the stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal planesasshowninFigure23. Figure23. Four-LayerPCBBoard NOTE The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. Oneofthemostcommonstackconfigurationsisthesix-layerboard,asshowninFigure24. Figure24. Six-LayerPCBBoard In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layersandreferencedplanes,inadditiontoensuringreferencetoagroundplaneforsignallayers1and6. 24 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 Layout Guidelines (continued) 13.1.4 SeparationBetweenTraces The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low-noise coupling requires close coupling between the differentialpairofanLVDSlinktobenefitfromtheelectromagneticfieldcancellation.Thetracesshouldbe100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance between two traces should be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether thetracesareedge-coupledorbroad-side-coupled. Figure25. 3-WRuleforSingle-EndedandDifferentialTraces(TopView) Youshouldexercisecautionwhenusingautorouters,becausetheydonotalwaysaccountforallfactorsaffecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signalpath.Usingsuccessive45° turnstendstominimizereflections. 13.1.5 CrosstalkandGroundBounceMinimization Toreducecrosstalk,itisimportanttoprovideareturnpathtohigh-frequencycurrentsthatisascloseaspossible to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic fieldstrength.Discontinuitiesinthegroundplaneincreasethereturnpathinductanceandshouldbeavoided. 13.2 Layout Example At least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as showninFigure26. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com Layout Example (continued) Figure26. StaggeredTraceLayout This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 27. Note that vias create additionalcapacitance.Forexample,atypicalviahasalumpedcapacitanceeffectof1/2pFto1pFinFR4. Figure27. GroundViaLocation(SideView) Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuitiesthatincreasereturningcurrentloopareas. To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the samearea,asopposedtomixingthemtogether,helpsreducesusceptibilityissues. 26 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 www.ti.com SLLS262R–JULY1997–REVISEDDECEMBER2014 14 Device and Documentation Support 14.1 Device Support 14.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 14.1.2 OtherLVDSProducts For other products and application notes in the LVDS and LVDM product families visit our Web site at http://www.ti.com/sc/datatran. 14.2 Documentation Support 14.2.1 RelatedInformation IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for moreinformation. Formoreapplicationguidelines,seethefollowingdocuments: • Low-VoltageDifferentialSignalingDesignNotes (SLLA014) • InterfaceCircuitsforTIA/EIA-644 (LVDS)(SLLA038) • ReducingEMIWithLVDS (SLLA030) • SlewRateControlofLVDSCircuits (SLLA034) • UsinganLVDSReceiverWithRS-422Data(SLLA031) • EvaluatingtheLVDSEVM(SLLA033) 14.3 Related Links Table 3 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN55LVDS32 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDS32 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDS3486 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDS9637 Clickhere Clickhere Clickhere Clickhere Clickhere 14.4 Trademarks RogersisatrademarkofRogersCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. 14.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 14.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©1997–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

SN55LVDS32,SN65LVDS32,SN65LVDS3486,SN65LVDS9637 SLLS262R–JULY1997–REVISEDDECEMBER2014 www.ti.com 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 28 SubmitDocumentationFeedback Copyright©1997–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9762201Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9762201Q2A SNJ55 LVDS32FK 5962-9762201QEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9762201QE A SNJ55LVDS32J 5962-9762201QFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9762201QF A SNJ55LVDS32W SN55LVDS32W ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 SN55LVDS32W SN65LVDS32D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS32PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32 & no Sb/Br) SN65LVDS3486D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS3486 & no Sb/Br) SN65LVDS3486DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS3486 & no Sb/Br) SN65LVDS3486DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS3486 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVDS3486DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS3486 & no Sb/Br) SN65LVDS9637D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 DK637 & no Sb/Br) SN65LVDS9637DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AXF & no Sb/Br) SN65LVDS9637DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AXF & no Sb/Br) SN65LVDS9637DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AXF & no Sb/Br) SN65LVDS9637DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AXF & no Sb/Br) SN65LVDS9637DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 L37 & no Sb/Br) SN65LVDS9637DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 L37 & no Sb/Br) SN65LVDS9637DGNRG4 ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 L37 & no Sb/Br) SN65LVDS9637DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 DK637 & no Sb/Br) SN65LVDS9637DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 DK637 & no Sb/Br) SNJ55LVDS32FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9762201Q2A SNJ55 LVDS32FK SNJ55LVDS32J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9762201QE A SNJ55LVDS32J SNJ55LVDS32W ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9762201QF A SNJ55LVDS32W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN55LVDS32 : •Catalog: SN75LVDS32 •Space: SN55LVDS32-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LVDS32DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS32NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN65LVDS32PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS3486DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS9637DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVDS9637DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVDS9637DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LVDS32DR SOIC D 16 2500 333.2 345.9 28.6 SN65LVDS32NSR SO NS 16 2000 367.0 367.0 38.0 SN65LVDS32PWR TSSOP PW 16 2000 350.0 350.0 43.0 SN65LVDS3486DR SOIC D 16 2500 350.0 350.0 43.0 SN65LVDS9637DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65LVDS9637DGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 SN65LVDS9637DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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