Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 SNx5LVDS3xx High-Speed Differential Line Drivers 1 Features 3 Description • Four('391),Eight('389),orSixteen('387)Line This family of 4, 8, and 16 differential line drivers 1 implements the electrical characteristics of low- DriversMeetorExceedtheRequirementsofANSI voltage differential signaling (LVDS). This signaling EIA/TIA-644Standard technique lowers the output voltage levels of 5-V • DesignedforSignalingRatesUpto630Mbps differential standard levels (such as EIA/TIA-422B) to WithVeryLowRadiation(EMI) reducethepower,increasetheswitchingspeeds,and • Low-VoltageDifferentialSignalingWithTypical allow operation with a 3.3-V supply rail. Any of the 16 OutputVoltageof350mVanda100-ΩLoad current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a • PropagationDelayTimesLessThan2.9ns 100-Ωloadwhenenabled. • OutputSkewIsLessThan150ps • Part-to-PartSkewIsLessThan1.5ns DeviceInformation(1) • 35-mWTotalPowerDissipationinEachDriver PARTNUMBER PACKAGE BODYSIZE(NOM) Operatingat200MHz SN65LVDS387 TSSOP(64) 17.00mm×6.10mm • DriverIsHigh-ImpedanceWhenDisabledorWith SN75LVDS387 TSSOP(38) 9.70mm×4.40mm V <1.5V SOIC(16) 9.90mm×3.91mm CC SN65LVDS389 • SN65'VersionBus-PinESDProtectionExceeds TSSOP(16) 5.00mm×4.40mm 15kV SN75LVDS389 TSSOP(64) 17.00mm×6.10mm • PackagedinThinShrinkSmall-OutlinePackage SN65LVDS391 TSSOP(38) 9.70mm×4.40mm With20-milPinPitch SOIC(16) 9.90mm×3.91mm SN75LVDS391 • Low-VoltageTTL(LVTTL)LogicInputsAre5-V TSSOP(16) 5.00mm×4.40mm Tolerant (1) For all available packages, see the orderable addendum at theendofthedatasheet. 2 Applications • WirelessInfrastructure • TelecomInfrastructure • Printer TypicalApplicationSchematic Host Balanced Interconnect Target Power Power T Host Target DBn DBn Controller Controller T DBn–1 DBn–1 T DBn–2 DBn–2 T DBn–3 DBn–3 T DB2 DB2 T DB1 DB1 T DB0 DB0 T TX Clock RX Clock SN65LVDS387 or 389 LVDS Receiver(s) Indicates twisting of the Indicates the line termination conductors. T circuit. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 10.2 FunctionalBlockDiagram.....................................13 2 Applications........................................................... 1 10.3 FeatureDescription...............................................13 3 Description............................................................. 1 10.4 DeviceFunctionalModes......................................14 4 RevisionHistory..................................................... 2 11 ApplicationandImplementation........................ 15 11.1 ApplicationInformation..........................................15 5 Description(Continued)........................................ 3 11.2 TypicalApplication................................................16 6 DeviceOptions....................................................... 3 12 PowerSupplyRecommendations..................... 22 7 PinConfigurationandFunctions......................... 3 13 Layout................................................................... 22 8 Specifications......................................................... 6 13.1 LayoutGuidelines.................................................22 8.1 AbsoluteMaximumRatings......................................6 13.2 LayoutExample....................................................24 8.2 ESDRatings..............................................................6 14 DeviceandDocumentationSupport................. 25 8.3 RecommendedOperatingConditions.......................7 14.1 DeviceSupport......................................................25 8.4 ThermalInformation..................................................7 14.2 DocumentationSupport........................................25 8.5 ElectricalCharacteristics..........................................7 14.3 RelatedLinks........................................................25 8.6 SwitchingCharacteristics..........................................8 14.4 Trademarks...........................................................25 8.7 TypicalCharacteristics..............................................9 14.5 ElectrostaticDischargeCaution............................25 9 ParameterMeasurementInformation................11 14.6 Glossary................................................................26 10 DetailedDescription........................................... 13 15 Mechanical,Packaging,andOrderable 10.1 Overview...............................................................13 Information........................................................... 26 4 Revision History ChangesfromRevisionF(December2014)toRevisionG Page • ChangedC3AFrom:pin20To:pin21inthePinFunctions:SNx5LVDS387table ............................................................. 5 ChangesfromRevisionE(November2004)toRevisionF Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 2 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 5 Description (Continued) When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldownthatwilldrivetheinputtoalowlevelwhenopen-circuited. The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to70°C. 6 Device Options PARTNUMBER(1) TEMPERATURERANGE NUMBEROFDRIVERS BUS-PINESD SN65LVDS387DGG –40°Cto85°C 16 15kV SN75LVDS387DGG 0°Cto70°C 16 4kV SN65LVDS389DBT –40°Cto85°C 8 15kV SN75LVDS389DBT 0°Cto70°C 8 4kV SN65LVDS391D –40°Cto85°C 4 15kV SN75LVDS391D 0°Cto70°C 4 4kV SN65LVDS391PW –40°Cto85°C 4 15kV SN75LVDS391PW 0°Cto70°C 4 4kV (1) Thispackageisavailabletapedandreeled.Toorderthispackagingoption,addanRsuffixtothepart number(forexample,SN65LVDS387DGGR). 7 Pin Configuration and Functions ’LVDS389 ’LVDS387 DBT PACKAGE DGG PACKAGE (TOP VIEW) (TOP VIEW) GND 1 38 A1Y GND 1 64 A1Y VCC 2 37 A1Z VCC 2 63 A1Z GND 3 36 A2Y VCC 3 62 A2Y ENA 4 35 A2Z GND 4 61 A2Z A1A 5 34 A3Y ENA 5 60 A3Y A2A 6 33 A3Z A1A 6 59 A3Z A3A 7 32 A4Y A2A 7 58 A4Y A4A 8 31 A4Z A3A 8 57 A4Z GND 9 30 NC A4A 9 56 B1Y VCC 10 29 NC ENB 10 55 B1Z GND 11 28 NC B1A 11 54 B2Y B1A 12 27 B1Y B2A 12 53 B2Z B2A 13 26 B1Z B3A 13 52 B3Y B3A 14 25 B2Y B4A 14 51 B3Z B4A 15 24 B2Z GND 15 50 B4Y ENB 16 23 B3Y VCC 16 49 B4Z GND 17 22 B3Z VCC 17 48 C1Y VCC 18 21 B4Y GND 18 47 C1Z GND 19 20 B4Z C1A 19 46 C2Y C2A 20 45 C2Z C3A 21 44 C3Y ’LVDS391 D OR PW PACKAGE C4A 22 43 C3Z (TOP VIEW) ENC 23 42 C4Y D1A 24 41 C4Z EN1,2 1 16 1Y D2A 25 40 D1Y 1A 2 15 1Z D3A 26 39 D1Z 2A 3 14 2Y D4A 27 38 D2Y VCC 4 13 2Z END 28 37 D2Z GND 5 12 3Y GND 29 36 D3Y 3A 6 11 3Z VCC 30 35 D3Z 4A 7 10 4Y VCC 31 34 D4Y EN3,4 8 9 4Z GND 32 33 D4Z Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com PinFunctions:SNx5LVDS391 PIN I/O DESCRIPTION NAME NUMBER V 4 – Supplyvoltage CC GND 5 – Ground 1A 2 I LVTTLinputsignal 1Y 16 O Differential(LVDS)non-invertingoutput 1Z 15 O Differential(LVDS)invertingoutput 2A 3 I LVTTLinputsignal 2Y 14 O Differential(LVDS)non-invertingoutput 2Z 13 O Differential(LVDS)invertingoutput 3A 6 I LVTTLinputsignal 3Y 12 O Differential(LVDS)non-invertingoutput 3Z 11 O Differential(LVDS)invertingoutput 4A 7 I LVTTLinputsignal 4Y 10 O Differential(LVDS)non-invertingoutput 4Z 9 O Differential(LVDS)invertingoutput EN1,2 1 I Enableforchannels1and2 EN3,4 8 I Enableforchannels3and4 PinFunctions:SNx5LVDS389 PIN I/O DESCRIPTION NAME NUMBER V 2,10,18 – Supplyvoltage CC 1,3,9,11, GND – Ground 17,19 A1A 5 I LVTTLinputsignal A1Y 38 O Differential(LVDS)non-invertingoutput A1Z 37 O Differential(LVDS)invertingoutput A2A 6 I LVTTLinputsignal A2Y 36 O Differential(LVDS)non-invertingoutput A2Z 35 O Differential(LVDS)invertingoutput A3A 7 I LVTTLinputsignal A3Y 34 O Differential(LVDS)non-invertingoutput A3Z 33 O Differential(LVDS)invertingoutput A4A 8 I LVTTLinputsignal A4Y 32 O Differential(LVDS)non-invertingoutput A4Z 31 O Differential(LVDS)invertingoutput B1A 12 I LVTTLinputsignal B1Y 27 O Differential(LVDS)non-invertingoutput B1Z 26 O Differential(LVDS)invertingoutput B2A 13 I LVTTLinputsignal B2Y 25 O Differential(LVDS)non-invertingoutput B2Z 24 O Differential(LVDS)invertingoutput B3A 14 I LVTTLinputsignal B3Y 23 O Differential(LVDS)non-invertingoutput B3Z 22 O Differential(LVDS)invertingoutput B4A 15 I LVTTLinputsignal B4Y 21 O Differential(LVDS)non-invertingoutput B4B 20 O Differential(LVDS)invertingoutput 4 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 PinFunctions:SNx5LVDS389(continued) PIN I/O DESCRIPTION NAME NUMBER ENA 4 I EnableforchannelA ENB 16 I EnableforchannelB NC 28,29,30 – Noconnection PinFunctions:SNx5LVDS387 PIN I/O DESCRIPTION NAME NUMBER 2,3,16,17, V – Supplyvoltage CC 30,31 1,4,15,18, GND – Ground 29,32 A1A 6 I LVTTLinputsignal A1Y 64 O Differential(LVDS)non-invertingoutput A1Z 73 O Differential(LVDS)invertingoutput A2A 7 I LVTTLinputsignal A2Y 62 O Differential(LVDS)non-invertingoutput A2Z 61 O Differential(LVDS)invertingoutput A3A 8 I LVTTLinputsignal A3Y 60 O Differential(LVDS)non-invertingoutput A3Z 59 O Differential(LVDS)invertingoutput A4A 9 I LVTTLinputsignal A4Y 58 O Differential(LVDS)non-invertingoutput A4Z 57 O Differential(LVDS)invertingoutput B1A 11 I LVTTLinputsignal B1Y 56 O Differential(LVDS)non-invertingoutput B1Z 55 O Differential(LVDS)invertingoutput B2A 12 I LVTTLinputsignal B2Y 54 O Differential(LVDS)non-invertingoutput B2Z 53 O Differential(LVDS)invertingoutput B3A 13 I LVTTLinputsignal B3Y 52 O Differential(LVDS)non-invertingoutput B3Z 51 O Differential(LVDS)invertingoutput B4A 14 I LVTTLinputsignal B4Y 50 O Differential(LVDS)non-invertingoutput B4B 49 O Differential(LVDS)invertingoutput C1A 19 I LVTTLinputsignal C1Y 48 O Differential(LVDS)non-invertingoutput C1Z 47 O Differential(LVDS)invertingoutput C2A 20 I LVTTLinputsignal C2Y 46 O Differential(LVDS)non-invertingoutput C2Z 45 O Differential(LVDS)invertingoutput C3A 21 I LVTTLinputsignal C3Y 44 O Differential(LVDS)non-invertingoutput C3Z 43 O Differential(LVDS)invertingoutput C4A 22 I LVTTLinputsignal C4Y 42 O Differential(LVDS)non-invertingoutput C4Z 41 O Differential(LVDS)invertingoutput Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com PinFunctions:SNx5LVDS387(continued) PIN I/O DESCRIPTION NAME NUMBER D1A 24 I LVTTLinputsignal D1Y 40 O Differential(LVDS)non-invertingoutput D1Z 39 O Differential(LVDS)invertingoutput D2A 25 I LVTTLinputsignal D2Y 38 O Differential(LVDS)non-invertingoutput D2Z 37 O Differential(LVDS)invertingoutput D3A 26 I LVTTLinputsignal D3Y 36 O Differential(LVDS)non-invertingoutput D3Z 35 O Differential(LVDS)invertingoutput D4A 27 I LVTTLinputsignal D4Y 34 O Differential(LVDS)non-invertingoutput B4B 33 O Differential(LVDS)invertingoutput ENA 5 I EnableforchannelA ENB 10 I EnableforchannelB ENC 23 I EnableforchannelC END 26 I EnableforchannelD 8 Specifications 8.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Supplyvoltagerange,V (2) –0.5 4 V CC Inputs –0.5 6 V Inputvoltagerange YorZ –0.5 4 V Continuouspowerdissipation SeeThermal Information Leadtemperature1.6mm(1/16in)fromcasefor10seconds 260 °C Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundpin. 8.2 ESD Ratings VALUE UNIT Class3,A ±15000 V SN65'(Y,Z,andGND) Class3,B ±400 V V Electrostaticdischarge (ESD) Class3,A ±4000 V SN75'(Y,Z,andGND) Class3,B ±400 V Leadtemperature1.6mm(1/16in)fromcasefor10seconds 260 °C 6 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 8.3 Recommended Operating Conditions MIN NOM MAX UNIT V Supplyvoltage 3 3.3 3.6 V CC V High-levelinputvoltage 2 V IH V Low-levelinputvoltage 0.8 V IL Operatingfree-air SN75' 0 70 °C T A temperature SN65' –40 85 °C 8.4 Thermal Information SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 THERMALMETRIC(1) UNIT DGG DBT D PW 64PINS 38PINS 16PINS 16PINS DeratingFactorAboveT =25°C(2) 16.7 8.5 7.6 6.2 mW/°C A PowerRating:T ≤25°C 2094 1071 950 774 A PowerRating:T =70°C 1342 688 608 496 mW A PowerRating:T =85°C 1089 556 494 402 A (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mounted(low-k)andwithnoairflow. 8.5 Electrical Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT |V | Differentialoutputvoltagemagnitude 247 340 454 OD R =100Ω, Δ|V | Changeindifferentialoutputvoltage SeLeFigure9andFigure10 –50 50 mV OD magnitudebetweenlogicstates Steady-statecommon-modeoutput V 1.125 1.375 V OC(SS) voltage Changeinsteady-statecommon- ΔV modeoutputvoltagebetweenlogic SeeFigure11 –50 50 mV OC(SS) states Peak-to-peakcommon-modeoutput V 50 150 mV OC(PP) voltage 'LVDS387 85 95 Enabled,R =100Ω, 'LVDS389 L 50 70 V =0.8Vor2V IN 'LVDS391 20 26 I Supplycurrent mA CC 'LVDS387 0.5 1.5 Disabled, 'LVDS389 0.5 1.5 V =0VorV IN CC 'LVDS391 0.5 1.3 I High-levelinputcurrent V =2V 3 20 µA IH IH I Low-levelinputcurrent V =0.8V 2 10 µA IL IL V orV =0V ±24 mA OY OZ I Short-circuitoutputcurrent OS V =0V ±12 mA OD I High-impedanceoutputcurrent V =0VorV ±1 µA OZ O CC I Power-offoutputcurrent V =1.5V,V =2.4V ±1 µA O(OFF) CC O C Inputcapacitance V =0.4sin(4E6πt)+0.5V 5 pF IN I C Outputcapacitance V =0.4sin(4E6πt)+0.5V,Disabled 9.4 pF O I (1) Alltypicalvaluesareat25°Candwitha3.3-Vsupply. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com 8.6 Switching Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT t Propagationdelaytime,low-to-high-leveloutput 0.9 1.7 2.9 ns PLH t Propagationdelaytime,high-to-low-leveloutput 0.9 1.6 2.9 ns PHL t Differentialoutputsignalrisetime 0.4 0.8 1 ns r R =100Ω, L t Differentialoutputsignalfalltime C =10pF, 0.4 0.8 1 ns f L SeeFigure12 t Pulseskew(|t –t |) 150 500 ps sk(p) PHL PLH t Outputskew(2) 80 150 ps sk(o) t Part-to-partskew(3) 1.5 ns sk(pp) Propagationdelaytime,high-impedance-to-high- t 6.4 15 ns PZH leveloutput Propagationdelaytime,high-impedance-to-low- t 5.9 15 ns PZL leveloutput SeeFigure13 Propagationdelaytime,high-level-to-high- t 3.5 15 ns PHZ impedanceoutput Propagationdelaytime,low-level-to-high- t 4.5 15 ns PLZ impedanceoutput (1) Alltypicalvaluesareat25°Candwitha3.3-Vsupply. (2) t isthemagnitudeofthetimedifferencebetweenthet ort ofalldriversofasingledevicewithalloftheirinputsconnected sk(o) PLH PHL together. (3) t isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsofanytwodevicescharacterizedin sk(pp) thisdatasheetwhenbothdevicesoperatewiththesamesupplyvoltage,atthesametemperature,andhavethesametestcircuits. 8 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 8.7 Typical Characteristics 60 240 All outputs loaded and enabled. 220 50 mA mA 200 ent − 40 VCC = 3.6 V ent − 180 VCC = 3.6 V urr urr C C y 30 y 160 − Suppl 20 VCC = 3 V VCC = 3.3 V − Suppl 140 VCC = 3.3 V C C C C 120 VCC = 3 V I I 10 100 All outputs loaded and enabled. 0 80 0 50 100 150 200 250 300 0 50 100 150 200 250 300 350 f − Frequency − MHz f − Frequency − MHz Figure1.'LVDS391SupplyCurrentvs(RMS)Switching Figure2.'LVDS387SupplyCurrent(RMS)vsSwitching Frequency Frequency 110 2.1 s n − 100 me 2.0 Ti VCC = 3.6 V − mA 90 Delay 1.9 ent on 1.8 urr 80 ati y C VCC = 3.6 V pag 1.7 I− SupplCC 6700 VCC = 3 V VCC = 3.3 V w-To-High Pro 11..56 VCC = 3.3 VVCC = 3 V o 50 − L 1.4 H All outputs loaded and enabled. PL 40 t 1.3 0 50 100 150 200 250 300 −40 −20 0 20 40 60 80 100 f − Frequency − MHz TA − Free-Air Temperature − °C Figure3.'LVDS389SupplyCurrent(RMS)vsSwitching Figure4.Low-to-HighPropagationDelayTimevsFree-Air Frequency Temperature 2.2 4 s gation Delay Time − n 12..80 VCC = 3 V utput Voltage − V 3 VTAC C= =2 53°.C3 V opa 1.6 VCC = 3.3 V el O 2 h-To-Low Pr 1.4 VCC = 3.6 V − Low-LevL 1 Hig 1.2 VO − L H P t 1.0 0 −40 −20 0 20 40 60 80 100 0 2 4 6 Ta − Free-Air Temperature − °C IOL − Low-Level Output Current − mA Figure5.High-to-LowPropagationDelayTimevsFree-Air Figure6.Low-LevelOutputVoltagevsLow-LevelOutput Temperature Current Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com Typical Characteristics (continued) 3.5 VCC = 3.3 V 3 TA = 25°C VOY V e − VOZ ag 2.5 V utput Volt 2 Voltage − VOD Level O 1.5 Output h- − Hig 1 VO − H O V 0.5 0 −4 −3 −2 −1 0 IOH − High-Level Output Current − mA t − Time − ns Figure7.High-LevelOutputVoltagevsHigh-LevelOutput Figure8.OutputVoltagevsTime Current 10 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 9 Parameter Measurement Information IOY Y II A VOD Z IOZ GND VOY VI VOC (VOY + VOZ)/2 VOZ Figure9. VoltageandCurrentDefinitions 3.75 kW Y Input VOD 100 W Z 3.75 kW ± 0 V ≤ VTEST ≤ 2.4 V Figure10. V TestCircuit OD 49.9 W ± 1% (2 Places) 3 V Y Input VI 0 V Z 50 pF VOC VOC(PP) VOC(SS) VO NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR) =0.5Mpps, pulsewidth=500 ±10 ns.C includesinstrumentationandfixture capacitancewithin0.06mof L thedeviceundertest.ThemeasurementofV ismadeontestequipmentwitha–3dBbandwidthofatleast300 OC(PP) MHz. Figure11. TestCircuitandDefinitionsfortheDriverCommon-ModeOutputVoltage Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com Parameter Measurement Information (continued) 2 V Input 1.4 V 0.8 V Y tPLH tPHL Input VOD 100 W ± 1 % 100% Z 80% Output VOD(H) CL = 10 pF 0 V (2 Places) VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=50Mpps,pulsewidth=10±0.2ns.C includesinstrumentationandfixturecapacitancewithin0.06mofthe L deviceundertest. Figure12. TestCircuit,Timing,andVoltageDefinitionsfortheDifferentialOutputSignal 49.9 W ± 1% (2 Places) Y 0.8 V or 2 V Z + 1.2 V Input CL = 10 pF VOY VOZ – (2 Places) 2 V 1.4 V Input 0.8 V tPZH tPHZ VOY @ 1.4 V or 1.3 V VOZ 1.2 V tPZL tPLZ 1.2 V VOZ 1.1 V or VOY @ 1 V NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR) =0.5Mpps, pulsewidth=500 ±10 ns.C includesinstrumentationandfixture capacitancewithin0.06mof L thedeviceundertest. Figure13. EnableandDisableTimeCircuitandDefinitions 12 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 10 Detailed Description 10.1 Overview The SNx5LVDSxx devices are quad-, eight-, and 16-channel LVDS line drivers. They operate from a single supply that is nominally 3.3 V, but can be as low as 3 V and as high as 3.6 V. The input signals to the SNx5LVDSxx device are LVTTL signals. The outputs of the device are differential signals complying with the LVDS standard (TIA/EIA-644A). The differential output signal operates with a signal level of 340 mV, nominally, at a common-mode voltage of 1.2 V. This low differential output voltage results in a low emitted radiated energy, which is dependent on the signal slew rate. The differential nature of the output provides immunity to common- modecoupledsignals. The SNx5LVDSxx device is intended to drive a 100-Ω transmission line. This transmission line may be a printed- circuit board (PCB) or cabled interconnect. With transmission lines, the optimum signal quality and power delivery is reached when the transmission line is terminated with a load equal to the characteristic impedance of theinterconnect.Likewise,thedriven100-Ωtransmissionlineshouldbeterminatedwithamatchedresistance. 10.2 Functional Block Diagram 1Y 1Y 1A 1A 1Z 1Z EN 2Y 2Y 2A 2A 2Z 2Z EN 3Y 3Y 3A 3A 3Z 3Z EN 4Y 4Y 4A 4A 4Z 4Z (1/4 of ’LVDS387 or 1/2 of ’LVDS389 shown) (’LVDS391 shown) Figure14. LogicDiagram(PositiveLogic) 10.3 Feature Description 10.3.1 DriverOutputVoltageandPower-OnReset The SNx5LVDSxx driver operates and meets all the specified performance requirements for supply voltages in therangeof3.0Vto3.6V.Whenthesupplyvoltagedropsbelow1.5V(oristurningonandhasnotyetreached 1.5V),power-onresetcircuitrysetsthedriveroutputtoahigh-impedancestate. 10.3.2 5-VInputTolerance 5-V and 3.3-V TTL logic standards share the same input high-voltage and input low-voltage thresholds, namely 2.0Vand0.8V,respectively.AlthoughthemaximumsupplyvoltagefortheSNx5LVDSxxis3.6V,thedrivercan operate and meet all performance requirements when the input signals are as high as 5 V. This allows operation with 3.3-V TTL as well as 5-V TTL logic. 3.3-V CMOS and 5-V CMOS inputs are also allowable, although one should ensure that the duty-cycle distortion that will result from the TTL (ground-referenced) thresholds are acceptable. 10.3.3 NCPins NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimumthermalperformance,agoodruleofthumbistogroundtheNCpinsattheboardlevel. 10.3.4 UnusedEnablePins UnusedenablepinsshouldbetiedtoV orGNDasappropriate. CC Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com Feature Description (continued) 10.3.5 DriverEquivalentSchematics The SNx5LVDSxx equivalent output schematic diagrams are shown in Figure 15. The driver input is represented by a CMOS inverter stage with a 7-V Zener diode. The input stage is high-impedance, and includes an internal pulldown to ground. If the driver input is left open, the driver input provides a low-level signal to the rest of the driver circuitry, resulting in a low-level signal at the driver output pins. The Zener diode provides ESD protection. The driver output stage is a differential pair, one half of which is shown in Figure 15. Like the input stage, the driver output includes Zener diodes for ESD protection. The schematic shows an output stage that includes a set of current sources (nominally 3.5 mA) that are connected to the output load circuit based upon the input stage signal.Tothefirstorder,theSNx5LVDSxxoutputstageactsaconstant-currentsource. EQUIVALENT OF EACH A OR EN INPUT TYPICAL OF ALL OUTPUTS VCC VCC 50 W A or EN Input 10 kW 5 W Y or Z 7 V Output 300 kW 7 V Figure15. EquivalentInputandOutputSchematicDiagrams 10.4 Device Functional Modes Table1providesthetruthtablefortheSNx5LVDSxxdevices. Table1.DriverFunctionTable(1) INPUT ENABLE OUTPUTS A EN Y Z H H H L L H L H X L Z Z OPEN H L H (1) H=high-level,L=low-level,X=irrelevant,Z=high-impedance(off) 14 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 11.1 Application Information The intended application of this device and signaling technique is for point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media can be printed- circuitboardtraces,backplanes,orcables.Thelargenumberofdriversintegratedintothesamesubstrate,along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel receivers, the SN65LVDS386orSN65LVDS388,over200milliondatatransferspersecondinsingle-edgeclockedsystemsare possiblewithverylittlepower. NOTE The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics. 11.1.1 SignalingRatevsDistance The ultimate data transfer rate over a given cable or trace length involves many variables. Starting with the capabilitiesofthisLVDSdrivertoreproduceadatapulseasshortas1.6ns(a630-Mbpssignalingrate)withless than 500 ps of pulse distortion, any degradation of this pulse by the transmission media will necessarily reduce thetimingmarginatthereceivingendofthedatalink. The timing uncertainty induced by the transmission media is commonly referred to as jitter and comes from numerous sources. The characteristics of a particular transmission media can be quantified by using an eye pattern measurement such as shown in Figure 16, which shows about 340 ps of jitter or 20% of the data pulse width. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com Application Information (continued) height abs. jitter width unit interval Figure16. TypicalLVDSEyePattern A generally accepted range of jitter at the receiver inputs that allows data recovery is 5% to 20% of the unit interval (data pulse width). Table 2 shows the signaling rate achieved on various cables and lengths at a 5% eye patternjitterwithatypicalLVDSdriver. Table2.SignalingRatesforVariousCablesfor5%EyePatternJitter CABLE LENGTH (m) A(1) B(2) C(3) D(4) E(5) F(6) (Mbps) (Mbps) (Mbps) (Mbps) (Mbps) (Mbps) 1 240 200 240 270 180 230 5 205 210 230 250 215 230 10 180 150 195 200 145 180 (1) CableA:CAT3,specifiedupto16MHz,noshield,outsideconductordiameter(ø)0.52mm (2) CableB:CAT5,specifiedupto100MHz,noshield,ø0.52mm (3) CableC:CAT5,specifiedupto100MHz,tapedoverallshield,ø0.52mm (4) CableD:CAT5(exceedingCAT5),specifiedupto300MHz,braidedoverallshieldplustapedindividualshieldforanypair,ø0.64mm (AWG22) (5) CableE:CAT5(exceedingCAT5),specifiedupto350MHz,ø0.64mm(AWG22),noshield (6) CableF:CAT5(exceedingCAT5),specifiedupto350MHz,self-shielded,ø0.64mm(AWG22) During synchronous parallel transfers, skew between the data and clock lines will also reduce the timing margin. This should be accounted for in the system timing budget. Fortunately, the low output skew of this LVDS driver willgenerallybeasmallportionofthisbudget. 11.2 Typical Application 11.2.1 Point-to-PointCommunications The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of digitaldata,asshowninFigure17. 16 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 Typical Application (continued) OUT+ IN+ Driver 100 (cid:13) Receiver OUT- IN- Figure17. Point-to-PointTopology A point-to-point communications channel has a single transmitter (driver) and a single receiver. This communications topology is often referred to as simplex. In Figure 17 the driver receives a single-ended input signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended input to a differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while translating to a signal whose features are more appropriate for communication over extended distances or in a noisyenvironment. 11.2.1.1 DesignRequirements DESIGNPARAMETERS EXAMPLEVALUE DriverSupplyVoltage(V ) 3.0to3.6V CCD DriverInputVoltage 0.8to3.3V DriverSignalingRate DCto200Mbps InterconnectCharacteristicImpedance 100Ω TerminationResistance 100Ω NumberofReceiverNodes 1 ReceiverSupplyVoltage(V ) 3.0to3.6V CCR ReceiverInputVoltage 0to2.4V ReceiverSignalingRate DCto200Mbps Groundshiftbetweendriverandreceiver ±1V 11.2.1.2 DetailedDesignProcedure 11.2.1.2.1 DriverSupplyVoltage The SNx5LVDSxx driver is operated from a single supply. The device can support operation with a supply as low as 3 V and as high as 3.6 V. The differential output voltage is nominally 340 mV over the complete output range. The minimum output voltage stays within the specified LVDS limits (247 mV to 454 mV) for the complete 3-V to 3.6-Vsupplyrange. 11.2.1.2.2 DriverBypassCapacitance Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths between power and ground. At low frequencies, a good digital power supply offers very-low-impedance paths between its terminals. However, as higher frequency currents propagate through power traces, the source is quiteoftenincapableofmaintainingalow-impedancepathtoground.Bypasscapacitorsareusedtoaddressthis shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board-level do a good job up into the kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. To solve this problem, one should resort to the use of smaller capacitors (nFtoμFrange)installedlocallynexttotheintegratedcircuit. Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes, atypicalcapacitorwithleadshasaleadinductancearound5nH. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula according to Johnson(1), equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in supplycurrentof1AcoversthewholerangeofLVDSdevicesofferedbyTexasInstruments.Inthisexample,the maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget availableinyourdesign. (1) æDI ö Cchip=ç MaximumStepChangeSupplyCurrent÷´TRiseTime è DVMaximumPowerSupplyNoise ø (1) æ 1A ö CLVDS=ç ÷´200ps=0.001mF è0.2Vø (2) The following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of capacitanceascloseaspossibletothechip. 3.3 V 0.1 µF 0.001 µF Figure18. RecommendedLVDSBypassCapacitorLayout 11.2.1.2.3 DriverOutputVoltage The SNx5LVDSxx driver output is a 1.2-V common-mode voltage, with a nominal differential output signal of 340 mV. This 340 mV is the absolute value of the differential swing (V = |V+– V–|). The peak-to-peak differential OD voltageistwicethisvalue,or680mV. 11.2.1.2.4 InterconnectingMedia The physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the LVDS standard, the key points which will be included here. This mediamaybeatwistedpair,twinax,flatribboncable,orPCBtraces. The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with variation no morethan10%(90 Ωto132 Ω). 11.2.1.2.5 PCBTransmissionLines As per SNLA187, Figure 19 depicts several transmission line structures commonly used in printed-circuit boards (PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. The dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmissionline). When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 19 shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by differentialsignals,thecoupledtransmissionlineisreferredtoasadifferentialpair.Thecharacteristicimpedance of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. When the two lines are immediately adjacent; for example, S is less than 2 W, the differential pair is called a tightly- coupled differential pair. To maintain constant differential impedance along the length, it is important to keep the tracewidthandspacinguniformalongthelength,aswellasmaintaingoodsymmetrybetweenthetwolines. (1) HowardJohnson&MartinGraham.1993.HighSpeedDigitalDesign–AHandbookofBlackMagic.PrenticeHallPRT.ISBNnumber 013395724. 18 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 Single-Ended Microstrip Single-Ended Stripline W W T H H HT Z0 Hr8(cid:14)71.41ln§¤'0.58.9W8H(cid:14)T•‚„ Z0 6H0rln§¤¤'1>0.9.8>2WH(cid:14)(cid:14)TT@@•‚‚„ Edge-Coupled Edge-Coupled S S H H Differential Microstrip Differential Stripline Zdiff 2uZ0u§¤¤'1(cid:16)0.48ue(cid:16)0.96uHs•‚‚„ Zdiff 2uZ0u§¤¤'1(cid:16)0.347e(cid:16)2.9uHs•‚‚„ Co-Planar Coupled Broad-Side Coupled Microstrips Striplines W W W G S G S H H Figure19. Controlled-ImpedanceTransmissionLines 11.2.1.2.6 TerminationResistor As shown earlier, an LVDS communication channel employs a current source driving a transmission line which is terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The designer should ensure that the termination resistance is within 10% of the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistance should be between90Ω and110Ω. The line termination resistance should be located as close as possible to the receiver, thereby minimizing the stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor intothereceiver,whichisexactlywhatisofferedwiththeTI ‘LVDTreceivers. While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the transmission line. In such an environment, LVDS receivers could be used for loads branching off the main bus withanLVDTreceiverusedonlyatthebusend. 11.2.1.2.7 DriverNCPins NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimumthermalperformance,agoodruleofthumbistogroundtheNCpinsattheboardlevel. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com 11.2.1.3 ApplicationCurve Figure20. TypicalDriverOutputEyePatterninPoint-to-PointSystem 11.2.2 MultidropCommunications A second common application of LVDS buffers is a multidrop topology. In a multidrop configuration, a single driverandasharedbusarepresentalongwithtwoormorereceivers(withamaximumpermissiblenumberof32 receivers).Figure21showsanexampleofamultidropsystem. Minimize Minimize Stub Stub + Driver Lengths Lengths |(cid:13)100 –Receiver – Receiver+ – Receiver+ Figure21. MultidropTopology 11.2.2.1 DesignRequirements DESIGNPARAMETERS EXAMPLEVALUE DriverSupplyVoltage(V ) 3.0to3.6V CCD DriverInputVoltage 0.8to3.3V DriverSignalingRate DCto200Mbps InterconnectCharacteristicImpedance 100Ω TerminationResistance 100Ω NumberofReceiverNodes 2to32 ReceiverSupplyVoltage(V ) 3.0to3.6V CCR ReceiverInputVoltage 0to2.4V ReceiverSignalingRate DCto200Mbps Groundshiftbetweendriverandreceiver ±1V 11.2.2.2 DetailedDesignProcedure 11.2.2.2.1 InterconnectingMedia The interconnect in a multidrop system differs considerably from a point-to-point system. While point-to-point interconnects are straightforward and well understood, the bus type architecture encountered with multidrop systemsrequiresmorecarefulattention.WewilluseFigure21abovetoexplorethesedetails. 20 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 The most basic multidrop system would include a single driver, located at a bus origin, with multiple receiver nodes branching off the main line, and a final receiver at the end of the transmission line, co-located with a bus termination resistor. While this would be the most basic multidrop system, it has several considerations not yet explored. The location of the transmitter at one bus end allows the design concerns to be simplified, but this comes at the cost of flexibility. With a transmitter located at the origin, a single bus termination at the far-end is required. The far-end termination absorbs the incident traveling wave. The flexibility lost with this arrangement is thus: if the single transmitter needed to be relocated on the bus, at any location other than the origin, we would be faced with a bus with one open-circuited end, and one properly terminated end. Locating the transmitter say in the middleofthebusmaybedesiredtoreduce(by ½)themaximumflighttimefromthetransmittertoreceiver. Another new feature in Figure 21 is clear in that every node branching off the main line results in stubs. The stubs should be minimized in any case, but have the unintended effect of locally changing the loaded impedance ofthebus. To a good approximation, the characteristic transmission line impedance seen into any cut point in the unloaded multipoint or multidrop bus is defined by √L/C, where L is the inductance per unit length and C is the capacitance per unit length. As capacitance is added to the bus in the form of devices and interconnections, the bus characteristic impedance is lowered. This may result in signal reflections from the impedance mismatch between theunloadedandloadedsegmentsofthebus. If the number of loads is constant and can be distributed evenly along the line, reflections can be reduced by changing the bus termination resistors to match the loaded characteristic impedance. Normally, the number of loads are not constant or distributed evenly and the reflections resulting from any mismatching should be accountedforinthenoisebudget. 11.2.2.3 ApplicationCurve Figure22. TypicalDriverOutputEyePatterninMultidropSystem Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com 12 Power Supply Recommendations The LVDS driver and receivers in this data sheet are designed to operate from a single power supply. Both drivers and receivers operate with supply voltages in the range of 2.4 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies would be used at each location. The expected ground potential difference between the driver power supply and the receiver power supply would be less than |±1 V|. Board-level and local device-level bypass capacitance shouldbeusedandarecoveredinDriverBypassCapacitance. 13 Layout 13.1 Layout Guidelines 13.1.1 MicrostripvsStriplineTopologies As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and stripline.MicrostripsaretracesontheouterlayerofaPCB,asshowninFigure23. Figure23. MicrostripTopology On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the necessary tolerances for Z based on the overall noise budget and reflection allowances. Footnotes 1(1), 2(2), O and3(3)provideformulasforZ andt fordifferentialandsingle-endedtraces. (1) (2) (3) O PD Figure24. StriplineTopology 13.1.2 DielectricTypeandBoardConstruction The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentallythroughseveraldesignsinvolvingLVDSdevices: • Copperweight:15gor1/2ozstart,platedto30gor1oz • Allexposedcircuitryshouldbesolder-plated(60/40)to7.62 μmor0.0003in(minimum). • Copperplatingshouldbe25.4μmor0.001in(minimum)inplated-through-holes. • Soldermaskoverbarecopperwithsolderhot-airleveling (1) HowardJohnson&MartinGraham.1993.HighSpeedDigitalDesign–AHandbookofBlackMagic.PrenticeHallPRT.ISBNnumber 013395724. (2) MarkI.Montrose.1996.PrintedCircuitBoardDesignTechniquesforEMCCompliance.IEEEPress.ISBNnumber0780311310. (3) ClydeF.Coombs,Jr.Ed,PrintedCircuitsHandbook,McGrawHill,ISBNnumber0070127549. 22 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 Layout Guidelines (continued) 13.1.3 RecommendedStackLayout Following the choice of dielectrics and design specifications, you should decide how many levels to use in the stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal planesasshowninFigure25. Layer 1: Routed Plane (LVDS Signals) Layer 2: Ground Plane Layer 3: Power Plane Layer 4: Routed Plane (TTL/CMOS Signals) Figure25. Four-LayerPCBBoard NOTE The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. Oneofthemostcommonstackconfigurationsisthesix-layerboard,asshowninFigure26. Layer 1: Routed Plane (LVDS Signals) Layer 2: Ground Plane Layer 3: Power Plane Layer 4: Ground Plane Layer 5: Ground Plane Layer 4: Routed Plane (TTL Signals) Figure26. Six-LayerPCBBoard In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layersandreferencedplanes,inadditiontoensuringreferencetoagroundplaneforsignallayers1and6. 13.1.4 SeparationBetweenTraces The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low-noise coupling requires close coupling between the differentialpairofanLVDSlinktobenefitfromtheelectromagneticfieldcancellation.Thetracesshouldbe100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance between two traces should be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether thetracesareedge-coupledorbroad-side-coupled. W Differential Traces LVDS S = Minimum spacing as Pair defined by PCB vendor W t(cid:3)2 W Single-Ended Traces TTL/CMOS Trace W Figure27. 3-WRuleforSingle-EndedandDifferentialTraces(TopView) Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com Layout Guidelines (continued) Youshouldexercisecautionwhenusingautorouters,becausetheydonotalwaysaccountforallfactorsaffecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signalpath.Usingsuccessive45° turnstendstominimizereflections. 13.1.5 CrosstalkandGroundBounceMinimization Toreducecrosstalk,itisimportanttoprovideareturnpathtohigh-frequencycurrentsthatisascloseaspossible to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic fieldstrength.Discontinuitiesinthegroundplaneincreasethereturnpathinductanceandshouldbeavoided. 13.2 Layout Example At least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as showninFigure28. Layer 1 Layer 6 Figure28. StaggeredTraceLayout This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 29. Note that vias create additionalcapacitance.Forexample,atypicalviahasalumpedcapacitanceeffectof1/2pFto1pFinFR4. Signal Via Signal Trace Uninterrupted Ground Plane Signal Trace Uninterrupted Ground Plane Ground Via Figure29. GroundViaLocation(SideView) Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuitiesthatincreasereturningcurrentloopareas. To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the samearea,asopposedtomixingthemtogether,helpsreducesusceptibilityissues. 24 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 www.ti.com SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 14 Device and Documentation Support 14.1 Device Support 14.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 14.1.2 OtherLVDSProducts For other products and application notes in the LVDS and LVDM product families visit our Web site at http://www.ti.com/sc/datatran. 14.2 Documentation Support 14.2.1 RelatedInformation IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for moreinformation. Formoreapplicationguidelines,seethefollowingdocuments: • Low-VoltageDifferentialSignalingDesignNotes (SLLA014) • InterfaceCircuitsforTIA/EIA-644 (LVDS)(SLLA038) • ReducingEMIWithLVDS (SLLA030) • SlewRateControlofLVDSCircuits (SLLA034) • UsinganLVDSReceiverWithRS-422Data(SLLA031) • EvaluatingtheLVDSEVM(SLLA033) 14.3 Related Links Table 3 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN65LVDS387 Clickhere Clickhere Clickhere Clickhere Clickhere SN75LVDS387 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDS389 Clickhere Clickhere Clickhere Clickhere Clickhere SN75LVDS389 Clickhere Clickhere Clickhere Clickhere Clickhere SN65LVDS391 Clickhere Clickhere Clickhere Clickhere Clickhere SN75LVDS391 Clickhere Clickhere Clickhere Clickhere Clickhere 14.4 Trademarks RogersisatrademarkofRogersCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. 14.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

SN65LVDS387,SN75LVDS387,SN65LVDS389 SN75LVDS389,SN65LVDS391,SN75LVDS391 SLLS362G–SEPTEMBER1999–REVISEDJANUARY2016 www.ti.com 14.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 26 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN65LVDS387 SN75LVDS387 SN65LVDS389SN75LVDS389 SN65LVDS391 SN75LVDS391

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVDS387DGG ACTIVE TSSOP DGG 64 25 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS387 & no Sb/Br) SN65LVDS387DGGG4 ACTIVE TSSOP DGG 64 25 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS387 & no Sb/Br) SN65LVDS387DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS387 & no Sb/Br) SN65LVDS387DGGRG4 ACTIVE TSSOP DGG 64 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS387 & no Sb/Br) SN65LVDS389DBT ACTIVE TSSOP DBT 38 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS389 & no Sb/Br) SN65LVDS389DBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS389 & no Sb/Br) SN65LVDS389DBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS389 & no Sb/Br) SN65LVDS391D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN65LVDS391DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN65LVDS391DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN65LVDS391DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN65LVDS391PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN65LVDS391PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN65LVDS391PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS391 & no Sb/Br) SN75LVDS387DGG ACTIVE TSSOP DGG 64 25 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS387 & no Sb/Br) SN75LVDS387DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS387 & no Sb/Br) SN75LVDS387DGGRG4 ACTIVE TSSOP DGG 64 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS387 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN75LVDS389DBT ACTIVE TSSOP DBT 38 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS389 & no Sb/Br) SN75LVDS389DBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS389 & no Sb/Br) SN75LVDS389DBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS389 & no Sb/Br) SN75LVDS389DBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 75LVDS389 & no Sb/Br) SN75LVDS391D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75LVDS391 & no Sb/Br) SN75LVDS391DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75LVDS391 & no Sb/Br) SN75LVDS391PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 DS391 & no Sb/Br) SN75LVDS391PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 DS391 & no Sb/Br) SN75LVDS391PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 DS391 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LVDS387DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1 SN65LVDS389DBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 SN65LVDS391DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS391PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN75LVDS387DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1 SN75LVDS389DBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 SN75LVDS391DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN75LVDS391PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LVDS387DGGR TSSOP DGG 64 2000 367.0 367.0 45.0 SN65LVDS389DBTR TSSOP DBT 38 2000 350.0 350.0 43.0 SN65LVDS391DR SOIC D 16 2500 350.0 350.0 43.0 SN65LVDS391PWR TSSOP PW 16 2000 350.0 350.0 43.0 SN75LVDS387DGGR TSSOP DGG 64 2000 367.0 367.0 45.0 SN75LVDS389DBTR TSSOP DBT 38 2000 350.0 350.0 43.0 SN75LVDS391DR SOIC D 16 2500 350.0 350.0 43.0 SN75LVDS391PWR TSSOP PW 16 2000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DBT0038A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE 6.55 SEATING 6.25 TYP C PLANE A 0.1 C PIN 1 INDEX AREA 38 X 0.5 38 1 2X 9 9.75 9.65 NOTE 3 19 20 0.23 38 X 0.17 B 4.45 0.1 C A B 1.2 MAX 4.35 NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220221/A 05/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT DBT0038A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 38 X (1.5) SYMM (R0.05) TYP 1 38 38 X (0.3) 38 X (0.5) SYMM 19 20 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220221/A 05/2020 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBT0038A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 38 X (1.5) SYMM (R0.05) TYP 1 38 38 X (0.3) 38 X (0.5) SYMM 19 20 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220221/A 05/2020 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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