SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 HIGH-SPEED DIFFERENTIAL RECEIVERS CheckforSamples:SN65LVDS33,SN65LVDT33,SN65LVDS34,SN65LVDT34 FEATURES The high-speed switching of LVDS signals usually 1 • 400-MbpsSignalingRate(1)and200-Mxfr/s necessitates the use of a line impedance matching resistor at the receiving-end of the cable or DataTransferRate transmission media. The SN65LVDT series of • OperatesWithaSingle3.3-VSupply receivers eliminates this external resistor by • -4Vto5VCommon-ModeInputVoltage integrating it with the receiver. The nonterminated Range SN65LVDS series is also available for multidrop or otherterminationcircuits. • DifferentialInputThresholds<±50mVWith50 mVofHysteresisOverEntireCommon-Mode SN65LVDS33D, SN65LVDT33D InputVoltageRange SN65LVDS33PW, SN65LVDT33PW • Integrated110-Ω LineTerminationResistors OnLVDTProducts D OR PW PACKAGE logic diagram (positive logic) (TOP VIEW) • TSSOPPackaging(33Only) G • CompliesWithTIA/EIA-644(LVDS) 1B 1 16 VCC G • ActiveFailsafeAssuresaHigh-LevelOutput 1A 2 15 4B SN65LVDT33 ONLY WithNoInput 1Y 3 14 4A 1A G 4 13 4Y 1Y • Bus-PinESDProtectionExceeds15kVHBM 1B 2Y 5 12 G • InputRemainsHigh-ImpedanceonPower 2A 6 11 3Y Down 2A 2B 7 10 3A 2Y • TTLInputsAre5VTolerant GND 8 9 3B 2B • Pin-CompatibleWiththeAM26LS32, 3A SN65LVDS32B,µA9637,SN65LVDS9637B 3Y 3B (1) Thesignallingrateofaline,isthenumberofvoltage transitionsthataremadepersecondexpressedintheunits 4A bps(bitspersecond). 4Y 4B DESCRIPTION SN65LVDS34D, SN65LVDT34D This family of four LVDS data line receivers offers the widest common-mode input voltage range in the D PACKAGE industry. These receivers provide an input voltage (TOP VIEW) logic diagram (positive logic) range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise VCC 1 8 1A tolerance. They are in industry standard footprints 1Y 2 7 1B 1A 1Y withintegratedterminationasanoption. 2Y 3 6 2A 1B Precise control of the differential input voltage GND 4 5 2B SN65LVDT34 ONLY thresholds allows for inclusion of 50 mV of input 2A 2Y voltage hysteresis to improve noise rejection on 2B slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-modevoltagerange. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2001–2004,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. AVAILABLEOPTIONS(1) PART NUMBEROF TERMINATION SYMBOLIZATION NUMBER(2) RECEIVERS RESISTOR SN65LVDS33D 4 No LVDS33 SN65LVDS33PW 4 No LVDS33 SN65LVDTS33D 4 Yes LVDT33 SN65LVDT33PW 4 Yes LVDT33 SN65LVDS34D 2 No LVDS34 SN65LVDT34D 2 Yes LVDT34 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) AddthesuffixRfortapedandreeledcarrier. DESCRIPTION (CONTINUED) The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled andotherconnectionswherepotentiallydamagingnoiseisalwaysathreat. The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of theSN65LVDS32Bapplicationnote. The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristicsofthemediaandthenoisecouplingtotheenvironment. The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C to85°C. Table1.FunctionTables(1) SN65LVDS33andSN65LVDT33 SN65LVDS34andSN65LVDT34 DIFFERENTIALINPUT ENABLES OUTPUT DIFFERENTIALINPUT OUTPUT V =V -V G G Y V =V –V Y ID A B ID A B H X H V ≥–32mV H ID V ≥–32mV ID X L H –100mV<V ≤–32mV ? ID H X ? V ≤–100mV L ID –100mV<V ≤–32mV ID X L ? Open H H X L V ≤–100mV ID X L L X L H Z H X H Open X L H (1) H=highlevel,L=lowlevel,X=irrelevant,Z=highimpedance(off),?=indeterminate 2 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC Attenuation Network VCC 6.5 kW 6.5 kW 1 pF n n 60 kW ok ok atior atior A Input uw uw B Input enet enet 200 kW 7 V AttN AttN 7 V 3 pF 250 kW 7 V 7 V LVDT Only 110 W VCC VCC 300 kW (G Only) 100 W Enable 37 W Inputs Y Output 7 V 7 V 300 kW (G Only) Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) UNIT Supplyvoltagerange,V (2) –0.5Vto4V CC EnablesorY –1Vto6V Voltagerange AorB –5Vto6V |V –V |(LVDT) 1V A B Electrostaticdischarge A,B,andGND (3) Class3,A:15kV,B:500V Charged-devicemode Allpins(4) ±500V Continuouspowerdissipation SeeDissipationRatingTable Storagetemperaturerange –65°Cto150°C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundterminal. (3) TestedinaccordancewithJEDECStandard22,TestMethodA114-A. (4) TestedinaccordancewithJEDECStandard22,TestMethodC101. DISSIPATION RATING TABLE T ≤25°C OPERATINGFACTOR(1) T =85°C PACKAGE A A POWERRATING ABOVET =25°C POWERRATING A D8 725mW 5.8mW/°C 377mW PW16 774mW 6.2mW/°C 402mW D16 950mW 7.6mW/°C 494mW (1) Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mountedandwithnoair flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT V Supplyvoltage 3 3.3 3.6 V CC V High-levelinputvoltage Enables 2 5 V IH V Low-levelinputvoltage Enables 0 0.8 V IL LVDS 0.1 3 |V | Magnitudeofdifferentialinputvoltage V ID LVDT 0.8 V orV Voltageatanybusterminal(separatelyorcommon-mode) –4 5 V I IC T Operatingfree-airtemperature –40 85 °C A 4 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 ELECTRICAL CHARACTERISTICS overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT V Positive-goingdifferentialinputvoltagethreshold 50 IT1 V =–4Vor5V, V Negative-goingdifferentialinputvoltage SIeBeFigure1andFigure2 –50 mV IT2 threshold V Differentialinputfailsafevoltagethreshold SeeTable2andFigure5 –32 –100 mV IT3 Differentialinputvoltagehysteresis, V 50 mV ID(HYS) V –V IT1 IT2 V High-leveloutputvoltage I =–4mA 2.4 V OH OH V Low-leveloutputvoltage I =4mA 0.4 V OL OL GatV ,Noload,Steady-state 16 23 CC SN65LVDx33 I Supplycurrent GatGND 1.1 5 mA CC SN65LVDx34 Noload,Steady-state 8 12 V =0V,Otherinputopen ±20 I V =2.4V,Otherinputopen ±20 I SN65LVDS µA V =–4V,Otherinputopen ±75 I Inputcurrent VI=5V,Otherinputopen ±40 I I (AorBinputs) V =0V,Otherinputopen ±40 I V =2.4V,Otherinputopen ±40 I SN65LVDT µA V =–4V,Otherinputopen ±150 I V =5V,Otherinputopen ±80 I Differentialinputcurrent SN65LVDS VID=100mV,VIC=–4Vor5V ±3 µA I ID (IIA–IIB) SN65LVDT VID=200mV,VIC=–4Vor5V 1.55 2.22 mA V orV =0Vor2.4V,V =0V ±20 A B CC SN65LVDS Power-offinputcurrent VAorVB=–4or5V,VCC=0V ±50 I µA I(OFF) (AorBinputs) V orV =0Vor2.4V,V =0V ±30 A B CC SN65LVDT V orV =–4Vor5V,V =0V ±100 A B CC I High-levelinputcurrent(enables) V =2V 10 µA IH IH I Low-levelinputcurrent(enables) V =0.8V 10 µA IL IL I High-impedanceoutputcurrent –10 10 µA OZ C Inputcapacitance,AorBinputtoGND V =0.4sin(4E6pt)+0.5V 5 pF I I (1) Alltypicalvaluesareat25°Candwitha3.3Vsupply. Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com SWITCHING CHARACTERISTICS overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT t Propagationdelaytime,low-to-high-leveloutput 2.5 4 6 ns PLH(1) SeeFigure3 t Propagationdelaytime,high-to-low-leveloutput 2.5 4 6 ns PHL(1) td1 Delaytime,failsafedeactivatetime CL=10pF,SeeFigure3 9 ns t Delaytime,failsafeactivatetime andFigure6 0.3 1.5 µs d2 t Pulseskew(|t -t |) 200 ps sk(p) PHL(1) PLH(1) t Outputskew(2) 150 ps sk(o) t Part-to-partskew(3) SeeFigure3 1 ns sk(pp) t Outputsignalrisetime 0.8 ns r t Outputsignalfalltime 0.8 ns f t Propagationdelaytime,high-level-to-high-impedanceoutput 5.5 9 ns PHZ t Propagationdelaytime,low-level-to-high-impedanceoutput 4.4 9 ns PLZ SeeFigure4 t Propagationdelaytime,high-impedance-to-high-leveloutput 3.8 9 ns PZH t Propagationdelaytime,high-impedance-to-low-leveloutput 7 9 ns PZL (1) Alltypicalvaluesareat25°Candwitha3.3-Vsupply. (2) t isthemagnitudeofthetimedifferencebetweenthet ort ofallreceiversofasingledevicewithalloftheirinputsdriven sk(o) PLH PHL together. (3) t isthemagnitudeofthetimedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsoftwodeviceswhenboth sk(pp) devicesoperatewiththesamesupplyvoltages,atthesametemperature,andhaveidenticalpackagesandtestcircuits. PARAMETER MEASUREMENT INFORMATION IIA A VO Y VID B VIA IIB (VIA + VIB)/2 VIC VIB VO Figure1. VoltageandCurrentDefinitions 6 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 PARAMETER MEASUREMENT INFORMATION (continued) 1000 W 100 W 100 W † VID + 1000 W 10 pF, VO VIC – 2 Places 10 pF †Remove for testing LVDT device. VIT1 0 V VID –100 mV VO 100 mV VID 0 V VIT2 VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. Figure2. V andV InputVoltageThresholdTestCircuitandDefinitions IT1 IT2 Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VID VIA VIB CL = 10 pF VO VIA 1.4 V VIB 1 V 0.4 V VID 0 V −0.4 V tPHL tPLH 80% 80% VOH VO 20% 1.4 V 20% VOL tf tr A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate r f (PRR)=50Mpps,pulsewidth=10±0.2ns.C includesinstrumentationandfixturecapacitancewithin0,06mmofthe L D.U.T. Figure3. TimingTestCircuitandWaveforms 8 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 PARAMETER MEASUREMENT INFORMATION (continued) B 1.2 V 500 W A 10 pF ± Inputs G VO VTEST G NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. 2.5 V VTEST A 1 V 2 V 1.4 V G 0.8 V 2 V 1.4 V G 0.8 V tPLZ tPLZ tPZL tPZL 2.5 V 1.4 V Y VOL +0.5 V VOL VTEST 0 1.4 V A 2 V G 1.4 V 0.8 V 2 V 1.4 V G 0.8 V tPHZ tPHZ tPZH tPZH VOH VOH –0.5 V Y 1.4 V 0 Figure4. Enable/DisableTimeTestCircuitandWaveforms Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com Table2.ReceiverMinimumandMaximumV IT3 InputThresholdTestVoltages APPLIEDVOLTAGES(1) RESULTANTINPUTS V (mV) V (mV) V (mV) V (mV) Output IA IB ID IC –4000 –3900 –100 –3950 L –4000 –3968 –32 –3984 H 4900 5000 –100 4950 L 4968 5000 –32 4984 H (1) Thesevoltagesareappliedforaminimumof1.5µs. VIA –100 mV @ 250 KHz VIB VO a) No Failsafe VIA –32 mV @ 250 KHz VIB VO Failsafe Asserted b) Failsafe Asserted Figure5. V FailsafeThresholdTest IT3 1.4 V 1 V 0.4 V >1.5 m s 0 V –0.2 V –0.4 V td1 td2 VOH 1.4 V VOL Figure6. WaveformsforFailsafeActivateandDeactivate 10 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 TYPICAL CHARACTERISTICS LOW-LEVELOUTPUTVOLTAGE HIGH-LEVELOUTPUTVOLTAGE vs vs LOW-LEVELOUTPUTCURRENT HIGH-LEVELOUTPUTCURRENT 5 4 VCC = 3.3 V VCC = 3.3 V TA = 25°C TA = 25°C V age − 4 ge − V 3 Volt olta put 3 ut V Out utp vel el O 2 e v − Low-LL 2 − High-Le 1 O 1 H V O V 0 0 0 10 20 30 40 −40 −30 −20 −10 0 IOL − Low-Level Output Current − mA IOH − High-Level Output Current − mA Figure7. Figure8. LOW-TO-HIGHPROPAGATIONDELAYTIME HIGH-TO-LOWPROPAGATIONDELAYTIME vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 5 5 s s n n − − e e m m Ti Ti y y a 4.5 a 4.5 el el D D on VCC = 3 V on VCC = 3 V ati ati g g VCC = 3.3 V a a op 4 VCC = 3.3 V op 4 Pr Pr h w g o Hi L To- VCC = 3.6 V To- VCC = 3.6 V w- 3.5 h- 3.5 Lo Hig − − H L L H P P t 3 t 3 −50 0 50 100 −50 0 50 100 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure9. Figure10. Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLYCURRENT vs FREQUENCY 140 120 100 VCC = 3.3 V A m − ent 80 VCC = 3.6 V r r u C y 60 pl VCC = 3 V p u S 40 − C C I 20 0 0 100 150 200 f − Switching Frequency − MHz Figure11. APPLICATION INFORMATION 0.01 m F ≈3.6 V 16 VCC 5 V 1 1B 0.1 m F 1N645 100 W (see Note A) (2 places) 2 1A 15 4B 3 1Y 100 W (see Note B) 14 VCC 4 G 4A 13 5 4Y 2Y 12 G 6 See Note C 2A 11 3Y 100 W 7 10 2B 3A 100 W 8 9 GND 3B A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V and the ground CC plane.Thecapacitorshouldbelocatedascloseaspossibletothedeviceterminals. B. Theterminationresistancevalueshouldmatchthenominalcharacteristicimpedanceofthetransmissionmediawith ±10%. C. UnusedenableinputsshouldbetiedtoV orGNDasappropriate. CC Figure12. OperationWith5-VSupply 12 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 RELATED INFORMATION IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for moreinformation. Formoreapplicationguidelines,seethefollowingdocuments: • Low-VoltageDifferentialSignallingDesignNotes(SLLA014) • InterfaceCircuitsforTIA/EIA-644(LVDS)(SLLA038) • ReducingEMIWithLVDS(SLLA030) • SlewRateControlofLVDSCircuits(SLLA034) • UsinganLVDSReceiverWithRS-422Data(SLLA031) • EvaluatingtheLVDSEVM(SLLA033) ACTIVE FAILSAFE FEATURE A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current LVDS failsafe solutions require either external components with subsequent reductions in signal quality or integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the limitations seen in present solutions. A detailed theory of operation is presented in application note The Active FailsafeFeatureoftheSN65LVDS32B,(SLLA082A). The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator outputs.Whenfailsafeisasserted,thefailsafelogicdrivesthemainreceiveroutputtologichigh. Output Main Receiver Buffer A + _ B R Failsafe Timer Reset A > B + 80 mV + _ Failsafe B > A + 80 mV + _ Window Comparator Figure13. ReceiverWithActiveFailsafe ECL/PECL-TO-LVTTL CONVERSION WITH TI's LVDS RECEIVER The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of choice for system designers. Designers know of the established technology and that it is capable of high-speed data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B–MARCH2001–REVISEDNOVEMBER2004 www.ti.com LVDSprovidedesignerswithanotheralternative.WhilethetotalexchangeofECLforLVDSmaynotbeadesign option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the termination bias voltagerequiredforECLtermination(V –2V). CC Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received by TI's wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible common-modecurrentreflections. VCC R1 = 50 W VCC ICC R2 = 50 W ICC 5 Meters VB LV/PECL LVDS of CAT-5 VB R3 R3 R1 R1 VEE R2 R3 = 240 W Figure14. LVPECLorPECLtoRemoteWideCommon-ModeLVDSReceiver Figure15. LV/PECLtoRemoteSN65LVDS33at500MbpsReceiverOutput(CH1) TEST CONDITIONS • V =3.3V CC • T =25°C(ambienttemperature) A • All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ data. 14 SubmitDocumentationFeedback Copyright©2001–2004,TexasInstrumentsIncorporated ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B–MARCH2001–REVISEDNOVEMBER2004 EQUIPMENT • TektronixPS25216programmablepowersupply • TektronixHFS9003stimulussystem • TektronixTDS784D4-channeldigitalphosphoroscilloscope–DPO Tektronix PS25216 Programmable Tektronix HFS 9003 Power Supply Stimulus System Trigger Tektronix TDS 784D 4-Channel Bench Test Board Digital Phosphor Oscilloscope – DPO Figure16. EquipmentSetup 100 Mbit/s 200 Mbit/s Figure17. TypicalEyePatternSN65LVDS33 Copyright©2001–2004,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):SN65LVDS33 SN65LVDT33SN65LVDS34 SN65LVDT34

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVDS33D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS33 & no Sb/Br) SN65LVDS33DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS33 & no Sb/Br) SN65LVDS33DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS33 & no Sb/Br) SN65LVDS33DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS33 & no Sb/Br) SN65LVDS33PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS33 & no Sb/Br) SN65LVDS33PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS33 & no Sb/Br) SN65LVDS34D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS34 & no Sb/Br) SN65LVDS34DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS34 & no Sb/Br) SN65LVDS34DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS34 & no Sb/Br) SN65LVDT33D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT33 & no Sb/Br) SN65LVDT33DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT33 & no Sb/Br) SN65LVDT33PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT33 & no Sb/Br) SN65LVDT33PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT33 & no Sb/Br) SN65LVDT33PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT33 & no Sb/Br) SN65LVDT34D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT34 & no Sb/Br) SN65LVDT34DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT34 & no Sb/Br) SN65LVDT34DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT34 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN65LVDS33 : •Enhanced Product: SN65LVDS33-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LVDS33DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDT33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDT34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LVDS33DR SOIC D 16 2500 333.2 345.9 28.6 SN65LVDS33PWR TSSOP PW 16 2000 350.0 350.0 43.0 SN65LVDS34DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDT33PWR TSSOP PW 16 2000 350.0 350.0 43.0 SN65LVDT34DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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