SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER FEATURES • 48-TerminalQFN(QuadFlatpack) • ReceiverEqualizationandSelectableDriver 7mm×7mm×1mm,0.5-mmTerminalPitch PreemphasistoCounteractHigh-Frequency • TemperatureRange:-40(cid:176) Cto85(cid:176) C TransmissionLineLosses • IntegrationofTwo-SerialPort APPLICATIONS • SelectableLoopback • BidirectionalLinkReplicator • TypicalPowerConsumption650mW • SignalConditioner • XAUI802.3aeProtocolBackplane • 30-psDeterministicJitter Redundancy • On-Chip100-W ReceiverandDriver • HostAdapter(ApplicationsWithInternaland DifferentialTerminationResistorsEliminate ExternalConnectiontoSERDES) ExternalComponentsandReflectionfrom • SignalingRatesDCto4GbpsIncludingXAUI, Stubs GbE,FC,HDTV • 3.3-VNominalPowerSupply DESCRIPTION The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy switching,signalbuffering,orperformanceimprovementsonlegacybackplanehardware. The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver witha2:1inputmultiplexer. The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil tracewidth. This device operates from a single 3.3-V supply. The device has integrated 100-W line termination and provides self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output impedance matches 100-W line impedance. The inputs and outputs may be ac coupled for best interconnectivity with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the lowest. FUNCTIONAL DIAGRAM Programmable Input Equalization Preemphasis Opens up Data Eye EQ out Input Data After Long Backplane Trace (cid:9)(cid:7)(cid:4)(cid:3)(cid:6)(cid:10)(cid:5)(cid:8)(cid:2)(cid:1) Output Data Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2004–2006,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. DESCRIPTION (CONTINUED) The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and ischaracterizedforoperationfrom-40°Cto85°C. AVAILABLEOPTIONS PACKAGEDDEVICE(1) T DESCRIPTION A RGZ(48pin) -40°Cto85°C Serialmultiplexer SN65LVCP40 (1) Thepackageisavailabletapedandreeled.AddanRsuffixtodevicetypes(e.g.,SN65LVCP40RGZR). ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) UNIT V Supplyvoltagerange(2) –0.5Vto6V CC Controlinputs,alloutputs –0.5Vto(V +0.5V) CC Voltagerange Receiverinputs –0.5Vto4V HumanBodyModel(3) Allpins 4kV ESD Charged-DeviceModel(4) Allpins 500V SeePackageThermalCharacteristics T Maximumjunctiontemperature J Table (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundterminal. (3) TestedinaccordancewithJEDECStandard22,TestMethodA114-A. (4) TestedinaccordancewithJEDECStandard22,TestMethodC101. PACKAGE THERMAL CHARACTERISTICS PACKAGETHERMALCHARACTERISTICS(1) NOM UNIT q (junction-to-ambient) 33 °C/W JA q (junction-to-board) 20 °C/W JB q (junction-to-case) 4-layerJEDECBoard(JESD51-7)usingeightGND-viasØ-0.2onthe 23.6 °C/W JC centerpadasshowninthesection:Recommendedpcbfootprintwith PSI-jt(junction-to-toppseudo) boundaryandenvironmentconditionsofJEDECBoard(JESD51-2) 0.6 °C/W PSI-jb(junction-to-boardpseudo) 19.4 °C/W q (junction-to-pad) 5.4 °C/W JP (1) SeeapplicationnoteSPRA953foradetailedexplanationofthermalparameters(http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). 2 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT dR Operatingdatarate 4 Gbps V Supplyvoltage 3.135 3.3 3.465 V CC V Supplyvoltagenoiseamplitude 10Hzto2GHz 20 mV CC(N) T Junctiontemperature 125 °C J T Operatingfree-airtemperature(1) -40 85 °C A DIFFERENTIALINPUTS dR £ 1.25Gbps 100 1750 mVpp (in) V Receiverpeak-to-peakdifferentialinput 1.25Gbps<dR £ 3.125Gbps 100 1560 mVpp ID voltage(2) (in) dR >3.125Gbps 100 1000 mVpp (in) |V | VICM Rinepcuetivvoelrtacgoemmon-mode Ncooutep:linfogribsersetcjoitmtemrpeenrdfoerdm.anceac 1.5 1.6 VCC(cid:1) 2ID V CONTROLINPUTS V High-levelinputvoltage 2 V +0.3 V IH CC V Low-levelinputvoltage –0.3 0.8 V IL DIFFERENTIALOUTPUTS R Differentialloadresistance 80 100 120 W L (1) Maximumfree-airtemperatureoperationisallowedaslongasthedevicemaximumjunctiontemperatureisnotexceeded. (2) DifferentialinputvoltageV isdefinedas|IN+–IN–|. ID ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT DIFFERENTIALINPUTS Positivegoingdifferential V 50 mV IT+ inputhighthreshold Negativegoingdifferential V –50 mV IT– inputlowthreshold A Equalizergain From375MHzto1.875GHz 5 dB (EQ) R Terminationresistance, 80 100 120 W T(D) differential Open-circuitInputvoltage V AC-coupledinputs 1.6 V BB (inputself-biasvoltage) R Biasingnetworkdc 30 kW (BBDC) impedance R Biasingnetworkac 375MHz 42 W (BBAC) impedance 1.875GHz 8.4 DIFFERENTIALOUTPUTS V High-leveloutputvoltage R =100W ±1%, 650 mVpp OH L PRES_1=PRES_0=0; V Low-leveloutputvoltage –650 mVpp OL PREL_1=PREL_0=0;4Gbpsalternating Outputdifferentialvoltage 1010-pattern; V 1000 1300 1500 mVpp ODB(PP) withoutpreemphasis(2) Figure1 V Outputcommonmodevoltage 1.65 V OCM Changeinsteady-state SeeFigure6 D V common-modeoutputvoltage 1 mV OC(SS) betweenlogicstates (1) AlltypicalvaluesareatT =25°CandV =3.3Vsupplyunlessotherwisenoted.Theyareforreferencepurposesandarenot A CC productiontested. (2) DifferentialoutputvoltageV isdefinedas|OUT+–OUT–|. (ODB) SubmitDocumentationFeedback 3

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT Outputpreemphasisvoltage PREx_1:PREx_0=00 0 ratio, RL=100W ±1%; PREx_1:PREx_0=01 3 V(PE) V x=LorS; PREx_1:PREx_0=10 6 dB ODB(PP) SeeFigure1 VODPE(PP) PREx_1:PREx_0=11 9 Outputpreemphasisissetto9dBduringtest Preemphasisduration PREx_x=1; t 175 ps (PRE) measurement Measuredwitha100-MHzclocksignal; R =100W ,±1%,SeeFigure2 L r Outputresistance Differentialon-chipterminationbetweenOUT+and 100 W o OUT– CONTROLINPUTS I High-levelInputcurrent VIN=VCC 5 µA IH I Low-levelInputcurrentn VIN=GND 90 125 µA IL R Pullupresistance 35 kW (PU) POWERCONSUMPTION P Devicepowerdissipation Alloutputsterminated100W 650 880 mW D Alloutputs ICC Devicecurrentconsumption terminated100W PRBS27-1patternat4Gbps 254 mA SWITCHING CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT MULTIPLEXER t Multiplexerswitchtime Multiplexerorloopbackcontroltovalidoutput 3 6 ns (SM) DIFFERENTIALOUTPUTS Low-to-highpropagation t 0.5 1 ns PLH delay Propagationdelayinputtooutput High-to-lowpropagation SeeFigure4 t 0.5 1 ns PHL delay tr Risetime 20%to80%ofVO(DB);TestPattern:100-MHzclocksignal; 80 ps t Falltime SeeFigure3andFigure7 80 ps f t Pulseskew,|t –t |(2) 20 ps sk(p) PHL PLH t Outputskew(3) Alloutputsterminatedwith100W 25 200 ps sk(o) t Part-to-partskew(4) 500 ps sk(pp) SeeFigure7fortestcircuit. RJ Devicerandomjitter,rms BERTsetting10–15 0.8 2 ps-rms Alternating10-pattern. (1) Alltypicalvaluesareat25°Candwith3.3Vsupplyunlessotherwisenoted. (2) t isthemagnitudeofthetimedifferencebetweenthet andt ofanyoutputofasingledevice. sk(p) PLH PHL (3) t isthemagnitudeofthetimedifferencebetweenthet andt ofanytwooutputsofasingledevice. sk(o) PLH PHL (4) t isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsoftwodeviceswhenbothdevices sk(pp) operatewiththesamesupplyvoltages,atthesametemperature,andhaveidenticalpackagesandtestcircuits. 4 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 SWITCHING CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT 0dBpreemphasis Intrinsicdeterministicdevice (PREx_x=0); PRBS27-1 4Gbps 30 ps jitter (5)(6),peak-to-peak SeeFigure7forthetest pattern circuit. 1.25Gbps Over20-inch 7 DJ 0dBpreemphasis FR4trace Absolutedeterministic (PREx_x=0); PRBS27-1 4Gbps ps outputjitter(7),peak-to-peak SeeFigure7forthetest pattern OverFR4 circuit. trace2-inch 20 to20inches long (5) Intrinsicdeterministicdevicejitterisameasurementofthedeterministicjittercontributionfromthedevice.Itisderivedbytheequation (DJ –DJ ),whereDJ isthetotalpeak-to-peakdeterministicjittermeasuredattheoutputofthedeviceinpspp.DJ isthe (OUT) (IN) (OUT) (IN) peak-to-peakdeterministicjitterofthepatterngeneratordrivingthedevice. (6) TheSN65LVCP40built-inpassiveinputequalizercompensatesforISI.Fora20-inchFR4transmissionlinewith8-miltracewidth,the LVCP40typicallyreducesjitterby60psfromthedeviceinputtothedeviceoutput. (7) AbsolutedeterministicoutputjitterreflectsthedeterministicjittermeasuredattheSN65LVCP40output.Thevalueisarealmeasured valuewithaBiterrortesterasdescribedinFigure7.TheabsoluteDJreflectsthesumofalldeterministicjittercomponentsaccumulated overthelink:DJ =DJ +DJ +DJ . (absolute) (Signalgenerator) (transmissionline) (intrinsic(LVCP40)) PIN ASSIGNMENTS P N 0 0 0 P N P N S B A _ _ 0 0 0 0 _ B0 B0 OA OA CC B_ B_ ND A_ A_ CC UX L L S S V SI SI G SI SI V M 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 PREL_1 1 36 PRES_0 −+ VCC 2 −+−+ 35 VCC SSOOBB__00NP 34 +−++−− −−++−+ 3343 LLOO__00NP GND 5 32 GND LI_0P 6 31 LI_1N LI_0N 7 30 LI_1P VCC 8 29 VCC LLOO__11NP 190 +−++−− −−++−+ 2278 SSOOBB__11PN GND 11 −+−+ 26 REXT −+ PREL_0 12 25 PRES_1 13 14 15 16 17 18 19 20 21 22 23 24 MUX_S1 VCC SIA_1N SIA_1P GND SIB_1N SIB_1P VCC SOA_1N SOA_1P LB1A LB1B SubmitDocumentationFeedback 5

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 Table1.SignalDescriptions SIGNAL PIN(S) TYPE SIGNALTYPE DESCRIPTION LINESIDEHIGH-SPEEDI/O LI_0P 6 I(w/50-W termination PECL/CML Differentialinput,port_0lineside LI_0N 7 toVBB) compatible LI_1P 30 I(w/50-W termination PECL/CML Differentialinput,port_1lineside LI_1N 31 toVBB) compatible LO_0P 33 O VML(1) Differentialoutput,port_0lineside LO_0N 34 LO_1P 9 O VML(1) Differentialoutput,port_1lineside LO_1N 10 SWITCHSIDEHIGH-SPEEDI/O SIA_0P 40 I(w/50-W termination CML/PECL Differentialinput,mux_0switch_A_side SIA_0N 39 toVBB) compatible SIB_0P 43 I(w/50-W termination CML/PECL Differentialinput,mux_0switch_B_side SIB_0N 42 toVBB) compatible SIA_1P 16 I(w/50-W termination CML/PECL Differentialinput,mux_1switch_A_side SIA_1N 15 toVBB) compatible SIB_1P 19 I(w/50-W termination CML/PECL Differentialinput,mux_1switch_B_side SIB_1N 18 toVBB) compatible SOA_0P 46 O VML(1) Differentialoutput,mux_0switch_A_side SOA_0N 45 SOB_0P 4 O VML(1) Differentialoutput,mux_0switch_B_side SOB_0N 3 SOA_1P 22 O VML(1) Differentialoutput,mux_1switch_A_side SOA_1N 21 SOB_1P 28 O VML(1) Differentialoutput,mux_1switch_B_side SOB_1N 27 CONTROLSIGNALS Outputpreemphasiscontrol,linesideport_0andport_1.Hasinternal PREL_0 12 I(w/35-kW pullup) LVTTL pull-up.SeePreemphasisControlsPREL_0,PREL_1,PRES_0and PREL_1 1 PRESforfunctiondefinition. Outputpreemphasiscontrol,switchsideport_0andport_1.See PRES_0 36 I(w/35-kW pullup) LVTTL PreemphasisControlsPREL_0,PREL_1,PRES_0andPRESfor PRES_1 25 functiondefinition. LB0A 47 I(w/35-kW pullup) LVTTL Loopbackcontrolformux_0switchside.SeeLoopbackControlsLB0A, LB0B 48 LB0B,LB1AandLB1Bforfunctiondefinition.n LB1A 23 I(w/35-kW pullup) LVTTL Loopbackcontrolformux_1switchside.SeeLoopbackControlsLB0A, LB1B 24 LB0B,LB1AandLB1Bforfunctiondefinition.n MUX_S0 37 I(w/35-kW pullup) LVTTL PortAandBmultiplexcontrolofmux_0andmux_1.SeeMultiplex MUX_S1 13 ControlsMUX_S0andMUX_S1forfunctiondefinition. Noconnect.ThispinisunusedandcanbeleftopenortiedtoGNDwith REXT 26 N/A anyresistor. POWERSUPPLY 2,8,14, 20,29, VCC PWR Powersupply3.3V±5% 35,38, 44 5,11,17, GND PWR Powersupplyreturn 32,41 Thegroundcenterpadisthemetalcontactatthebottomofthe48-pin GND package.ItmustbeconnectedtotheGNDplane.Atleast4viasare PWR CenterPad recommendedtominimizeinductanceandprovideasolidground.See thepackagedrawingfortheviaplacement. (1) VMLstandsforVoltageModelogic;VMLprovidesadifferentialoutputimpedanceof100-W .VMLoffersthebenefitsofCMLand consumeslesspower. 6 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 FUNCTIONALBLOCKDIAGRAM VBB RT SIA_0P RT EQ SIA_0N LO_0P + +− RT − + LO_0N − SIB_0P EQ RT SIB_0N MUX_S0 VBB +− + SOA_0P RRTT +− − SOA_0N LI_0P RRTT EQ LI_0N + SOB_0P − + − + − SOB_0N LB0A LB0B PREL_0 Line Side Outputs Preemphasis Control VBB PREL_1 RT SIA_1P EQ RT SIA_1N LO_1P + +− RT − + LO_1N − SIB_1P EQ RT SIB_1N MUX_S1 VBB +− + SOA_1P RT +− − SOA_1N LI_1P RT EQ LI_1N + SOB_1P − + − + − SOB_1N LB1A LB1B PRES_0 Switch Side Outputs PRES_1 Preemphasis Control Note: 30 K VBB: Receiver input internal biasing voltage (allows ac coupling) VBB EQ: Input Equalizer (compensates for frequency dependent transmission line loss of backplanes) 1.6 V RT: Internal 50−Ohm receiver termination (100−Ohm differential) Preemphasis: Output precompensation for transmission line losses SubmitDocumentationFeedback 7

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 FUNCTIONAL DEFINITIONS Table2.MultiplexControlsMUX_S0andMUX_S1 MUX_Sn(1) MUXFUNCTION 0 MUX_nselectinputB 1 MUX_nselectinputA (1) n=0or1 Table3.LoopbackControlsLB0A,LB0B,LB1Aand LB1B LBnx(1) LOOPBACKFUNCTION 0 EnableloopbackofSIxinputtoSOxoutput 1 DisableloopbackofSIxinputtoSOxoutput (1) n=0or1,x=AorB Table4.MultiplexerandLoopbackControls INPUTS/OUTPUTS SOA_0 SOB_0 SOA_1 SOB_1 LO_0 LO_1 SIA_0 LB0A=0 x x x MUX_S0=1 x SIB_0 x LB0B=0 x x MUX_S0=0 x SIA_1 x x LB1A=0 x x MUX_S1=1 SIB_1 x x x LB1B=0 x MUX_S1=0 LI_0 LB0A=1 LB0B=1 x x x x LI_1 x x LB1A=1 LB1B=1 x x Table5.PreemphasisControlsPREL_0,PREL_1,PRES_0,andPRES_1 OUTPUT OUTPUTLEVELINmVpp TYPICALFR4 PREx_1(1) PREx_0(1) PREEMPHASIS LEVELINdB DEEMPHASIZED PREEMPHASIZED TRACELENGTH 0 0 0dB 1200 1200 10inchesofFR4trace 0 1 3dB 850 1200 20inchesofFR4trace 1 0 6dB 600 1200 30inchesofFR4trace 1 1 9dB 425 1200 40inchesofFR4trace (1) x=LorS Preemphasisistheprimarysignalconditioningmechanism.SeeFigure1andFigure2forfurtherdefinition. Equalization is secondary signal conditioning mechanism. The input stage provides 5-dB of fixed equalization gainfrom375MHzto1.875GHz(optimizedfor3.75-Gbps8B10Bcodeddata). 8 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 0−dB Preemphasis 3−dB Preemphasis 6−dB Preemphasis p) E1(pp) VOH 9−dB Preemphasis p) 2(p DP p E O 3( P V E D P O VOCM OD V VODB(PP) V VOL Figure1.PreemphasisandOutputVoltageWaveformsandDefinitions 1−bit 1 to N bit 9−dB Preemphasis p) p 3( E P D O V VODB(PP) 80% 20% t PRE Figure2.t )PreemphasisDurationMeasurement (PRE SubmitDocumentationFeedback 9

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 PARAMETER MEASUREMENT INFORMATION (continued) 80% 80% VODB 20% 20% tr tf Figure3.DriverOutputTransitionTime IN VID = 0 V tPLHD tPHLD OUT VOD= 0 V Figure4.PropagationDelayInputtoOutput CIRCUIT DIAGRAMS VCC OUT+ 49.9 (cid:1) IN+ VOCM OUT− 49.9 (cid:1) =R T5(0S E(cid:1)) 1 pF Gain Stage VCC + EQ RBBDC RT(SE) = 50 (cid:1) Figure6.Common-ModeOutputVoltageTest IN− Circuit LineEndTermination VBB ESD Self−Biasing Network Figure5.EquivalentInputCircuitDesign 10 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 JITTER TEST CIRCUIT DC DC GPeanteterarntor D+ Coax Block Pre-amp <2” 50 W TL SMA Coax Block DC SMA 20−inch FR4 R+X MU OUT DC D− Coax Block SMA Coupled EQ X 0 dB <2” 50 W TL SMA Coax Block Transmission line 400 mVPP SN65LVCP40 Differential Jitter Test Characterization Test Board Instrument NOTE: FortheJitterTest,thepreemphasisleveloftheoutputissetto0dB(PREx_x=0) Figure7.ACTestCircuit–JitterandOutputRiseTimeTestCircuit The SN65LVCP40 input equalizer provides 5-dB frequency gain to compensate for frequency loss of a shorter backplane transmission line. For characterization purposes, a 24-inch FR-4 coupled transmission line is used in place of the backplane trace. The 24-inch trace provides roughly 5 dB of attenuation between 375 MHz and 1.875GHz,representingcloselythecharacteristicsofashortbackplanetrace.Thelosstangentofthe FR4 in the testboardis0.018withaneffectivee (r)of3.1. TYPICAL DEVICE BEHAVIOR Data Eye Input After 30-inch of FR4 1 0 _ _ x x E E R R P P 0 0 0dB 0 1 3dB v 1 0 6dB V/ di 1 1 9dB m div 150 V/ m Data Eye Output After SN65LVCP40 0 0 1 80 ps/ div Figure9.PreemphasisSignalShape 40 ps/ div NOTE: 30 Inch Input Trace, dR = 4 Gbps; 27- 1 PRBS Figure8.DataInputandOutputPattern SubmitDocumentationFeedback 11

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 LVCP40 Output 4-Gbps with 9-dB 30-inch FR4 Signal Preemp Generator PRBS 27−1 30−inch FR4 IN Output with 0-dB 30-inch FR4 Preemp Figure10.DataOutputPattern 12 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 TYPICAL CHARACTERISTICS DETERMINISTICOUTPUTJITTER DETERMINISTICOUTPUTJITTER DETERMINISTICOUTPUTJITTER vs vs vs DATARATE DIFFERENTIALINPUTAMPLITUDE DIFFERENTIALINPUTAMPLITUDE 40 100 70 Deterministic Output Jitter − ps 1122330505055 2ADTLV7h r2 iCev−0 iPn1D i 4gnJP0 c tRDihhsB Je DFM S@RJLe V −p@a CTDa4s t OuJ=t TeT r 4r@er2 a0n=d5c ., T°e o8C n=85 −°t0hCm°eCi lO Wutidpeu t isof the Deterministic Output Jitter − ps 123456789000000000 PRBS P27R−B1S 27−1 +C 1J0T0KP C A2TI8D.5s Deterministic Output Jitter − ps 123456000000 Jitter @ 3.75 GbJipttseJr iJ@ttiett re3 r@. 1@2 25 .1 5G. 2Gb5pb Gspsbps 0 0 0 1 1.5 2 2.5 3 3.5 4 0 200 400 600 80010001200140016001800 0 200 400 600 80010001200140016001800 DR − Data Rate − Gbps VID − Differential Input Amplitude − mV VID − Differential Input Swing − mV Figure11. Figure12. Figure13. DETERMINISTICOUTPUTJITTER RANDOMOUTPUTJITTER RANDOMOUTPUTJITTER vs vs vs INPUTTRACELENGTH DATARATE DIFFERENTIALINPUTSWING 140 1.4 1.4 s−pp120 DJ @[p 3s.]7 650G0pmbVs ms 1.2 TA = 85°C − K28.7 Pattern ms 1.2 RJ @ 2.5 Gbps ministic Output Jitter − p104680000 [DpJs ]@ 20 D30J.m7 @5VG [3pp.sb1]s2 250G0bmpVs dom Output Jitter − ps-r 000...4681 TA T=A 0 =°C 8 5 −° C1T 0A −1 = 01 02 P15a0°tC tPe ar−nt t1e0rn10 Pattern RJ − Output Jitter − r 000...4681 RJ @ 3.75 GbpRsJ @ 3.125 Gbps eter 20 DJ @ 3.125Gbps Ran 0.2 0.2 D [ps] 600mV 0 0 0 0 10 20 30 40 50 60 70 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.94 0 200 400 600 800 1000120014001600 Input Trace Length − inch DR − Data Rate − Gbps VID − Differential Input Swing − mV Figure14. Figure15. Figure16. RANDOMOUTPUTJITTER TOTALOUTPUTJITTER DJ/RJOUTPUTJITTER vs vs vs INPUTTRACELENGTH POWERSUPPLYNOISE COMMON-MODEINPUTVOLTAGE 2.0 60 40 s andom Output Jitter − ps−rms 00011111........46802468 RVRV[Jp iiJns@n =−=@ 8r23m0 0.370s0.5m]1mG2VV5bppGpppsb;;ps RV[piJsn _=@r2m 03s0.]7m5VGpppb;s Total Output Jitter - ps-pp 1234500000 JJitJitteittert er@ r@ @8 40 10000 m0 m VmVV JiVttCeCr WNiothisoeut DJ − Deterministic Output Jitter − p 1122330505055 DJ @ 3.75 Gbps 1122334....0555Random Output Jitter − ps-rms R 0.2 [ps−rms] RJ @ 3.75 Gbps 0.5 0 0.0 0 1000 1200 1400 1600 1800 2000 2200 24000 0 10 20 30 40 50 0.1 1 10 100 Input Trace Length − inch Noise Frequency - MHz VICM − Common Mode Input Voltage − mV Figure17. Figure18. Figure19. SubmitDocumentationFeedback 13

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 TYPICAL CHARACTERISTICS (continued) TOTALOUTPUTJITTER SUPPLYCURRENT DIFFERENTIALOUTPUTSWING vs vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE INPUTSIGNALFREQUENCY 38 182 1.4 V 37 181 m al Output Jitter − ps−pp 33333456 TJ @ 200 mV Input Swing Supply Current − mA 111117777867890 0−dB Preemphasi9s−dB Preemphasis erential Output Swing − 001...6821 VODB @ 25 dC VODB @ 0 dC TJ − Tot 3312 TJ @ 600 mV Input Swing Icc − 117745 DBO − Diff 00..24 VODB @ 85 dC V 30 173 0 0 10 20 30 40 50 60 70 80 85 0 20 40 60 80 100 0 500 1 k 1.5 k 2 k 2.5 k 3 k 3.5 k 4 k TA − Free −Air Temperature − (cid:1)C TA − Free −Air Temperature − (cid:1)C Input Signal Frequency − MHz Figure20. Figure21. Figure22. RECEIVERINPUTRETURNLOSS vs FREQUENCY 0 −5 B − d −10 s s −15 o L urn −20 Ret −25 put −30 n er I −35 v cei −40 e R −45 −50 10 100 1000 10000 f − Frequency − MHz Figure23. 14 SubmitDocumentationFeedback

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 APPLICATION INFORMATION BANDWIDTH REQUIREMENTS Error free transmission of data over a transmission line has specific bandwidth demands. It is helpful to analyze the frequency spectrum of the transmit data first. For an 8B10B coded data stream at 3.75 Gbps of random data, the highest bit transition density occurs with a 1010 pattern (1.875 GHz). The least transition density in 8B10B allows for five consecutive ones or zeros. Hence, the lowest frequency of interest is 1.875 GHz/5 = 375 MHz. Real data signals consist of higher frequency components than sine waves due to the fast rise time. The faster the rise time, the more bandwidth becomes required. For 80-ps rise time, the highest important frequency component is at least 0.6/(p × 80 ps) = 2.4 GHz. Figure 24shows the Fourier transformation of the 375-MHz and 1.875-GHztrapezoidalsignal. 0 20 dB/dec 1875 MHz With B −5 80 ps Rise Time d 20 dB/dec − de 375 MHz With plitu−10 80 ps Rise Time 40 dB/dec m A nal −15 g 80% Si 40 dB/dec −20 20% tr tPeriod = 1/f −25 100 1000 10000 1/(pi x 100/60 tr) = 2.4 GHz f − Frequency − MHz Figure24.ApproximateFrequencySpectrumoftheTransmitOutputSignalWith80psRiseTime The spectrum analysis of the data signal suggests building a backplane with little frequency attenuation up to 2 GHz. Practically, this is achievable only with expensive, specialized PCB material. To support material like FR4,acompensationtechniqueisnecessarytocompensateforbackplaneimperfections. EXPLANATION OF EQUALIZATION Backplane designs differ widely in size, layer stack-up, and connector placement. In addition, the performance is impacted by trace architecture (trace width, coupling method) and isolation from adjacent signals. Common to most commercial backplanes is the use of FR4 as board material and its related high-frequency signal attenuation. Within a backplane, the shortest to longest trace lengths differ substantially – often ranging from 8 inches up to 40 inches. Increased loss is associated with longer signal traces. In addition, the backplane connector often contributes a good amount of signal attenuation. As a result, the frequency signal attenuation for a 300-MHz signal might range from 1 dB to 4 dB while the corresponding attenuation for a 2-GHz signal might span 6 dB to 24 dB. This frequency dependent loss causes distortion jitter on the transmitted signal. Each 'LVCP40 receiver input incorporates an equalizer and compensates for such frequency loss. The SN65LVCP40 equalizer provides 5 dB of frequency gain between 375 MHz and 1.875 GHz, compensating roughly for 20 inches of FR4 material with 8-mil trace width. Distortion jitter improvement is substantial, often providing more than 30-ps jitter reduction. The 5-dB compensation is sufficient for most short backplane traces. For longer trace lengths,itisrecommendedtoenabletransmitpreemphasisinaddition. SETTING THE PREEMPHASIS LEVEL The receive equalization compensates for ISI. This reduces jitter and opens the data eye. In order to find the best preemphasis setting for each link, calibration of every link is recommended. Assuming each link consists of a transmitter (with adjustable pre-emphasis such as 'LVCP40) and the 'LVCP40 receiver, the following steps are necessary: 1. Setthetransmitterandreceiverto0-dBpreemphasis;recordthedataeyeontheLVCP40receiveroutput. 2. IncreasethetransmitterpreemphasisuntilthedataeyeontheLVCP40receiveroutputlooksthecleanest. SubmitDocumentationFeedback 15

SN65LVCP40 www.ti.com SLLS623D–SEPTEMBER2004–REVISEDFEBRUARY2006 APPLICATION INFORMATION (continued) RECEIVER FAIL-SAFE RESPONSE If the input is removed from a powered receiver of the 'LVCP40, there are no internal fail-safe provisions to prevent noise from switching the output. Figure 25 shows one remedy using 1.6 kW resistors to pull up on one input to the SN65LVCP40 supply, and pull down the other input to its ground. Assuming the differential noise in the system is less than 25 mV, this maintains a valid output with no input. If the noise is greater than 25 mV, lowerfail-saferesistanceisrequired. VCC 1.6 kW 100 1.6 kW Figure25.Fail-SafeBiasResistors If the driver is another SN65LVCP40, attenuation from the driver to receiver must be less than 250 mV or 6 dB. This value comes from the minimum output of 500 mV into 100 W less the minimum recommended input voltage of100mV,25mVfornoise,and125mVforthemaximumfail-safebias. The fail-safe bias also introduces additional eye-pattern jitter depending upon the input voltage transition time, butisdesignedtobelessthan10%oftheunitinterval. The only other options are to have a hardware interlock that removed power to the receiver, or switched in a fail-safebias,orrelyonerrordetectiontoignorerandominputs. 16 SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVCP40RGZ ACTIVE VQFN RGZ 48 52 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 LVCP40 & no Sb/Br) SN65LVCP40RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 LVCP40 & no Sb/Br) SN65LVCP40RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 LVCP40 & no Sb/Br) SN65LVCP40RGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 LVCP40 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LVCP40RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN65LVCP40RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LVCP40RGZR VQFN RGZ 48 2500 350.0 350.0 43.0 SN65LVCP40RGZT VQFN RGZ 48 250 213.0 191.0 55.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048B VQFN - 1 mm max height SCALE 2.000 PLASTIC QUAD FLATPACK - NO LEAD B 7.15 A 6.85 PIN 1 INDEX AREA 7.15 6.85 1 MAX C SEATING PLANE 0.05 0.00 0.08 C 2X 5.5 4.1 0.1 (0.2) TYP EXPOSED 13 24 44X 0.5 THERMAL PAD 12 25 2X 49 SYMM 5.5 0.30 36 48X 1 0.18 0.1 C B A 48 37 0.05 PIN 1 ID SYMM 0.5 (OPTIONAL) 48X 0.3 4218795/B 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.1) (1.115) TYP (0.685) TYP 48 37 48X (0.6) 1 36 48X (0.24) (1.115) TYP 44X (0.5) (0.685) SYMM 49 TYP ( 0.2) TYP (6.8) VIA (R0.05) TYP 12 25 13 24 SYMM (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218795/B 02/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (1.37) TYP 48 37 48X (0.6) 1 36 48X (0.24) 44X (0.5) (1.37) TYP SYMM 49 (R0.05) TYP (6.8) 9X METAL ( 1.17) TYP 12 25 13 24 SYMM (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:12X 4218795/B 02/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated