SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 2x2 LVDS CROSSPOINT SWITCH FEATURES DESCRIPTION • HighSpeed(>1000Mbps)Upgradefor The SN65LVCP22 is a 2· 2 crosspoint switch DS90CP222x2LVDSCrosspointSwitch providing greater than 1000 Mbps operation for each • LVPECLCrosspointSwitchAvailablein path. The dual channels incorporate wide SN65LVCP23 common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The • Low-JitterFullyDifferentialDataPath dual outputs are LVDS drivers to provide low-power, • 50ps(Typ),ofPeak-to-PeakJitterWithPRBS low-EMI, high-speed operation. The SN65LVCP22 =223–1Pattern provides a single device supporting 2:2 buffering • LessThan200mW(Typ),300mW(Max)Total (repeating), 1:2 splitting, 2:1 multiplexing, 2· 2 switching, and LVPECL/CML to LVDS level PowerDissipation translation on each channel. The flexible operation of • Output(Channel-to-Channel)SkewIs10ps the SN65LVCP22 provides a single device to support (Typ),50ps(Max) the redundant serial bus transmission needs (working • Configurableas2:1Mux,1:2Demux,Repeater and protection switching cards) of fault-tolerant switch or1:2SignalSplitter systems found in optical networking, wireless infrastructure, and data commu- nications systems. TI • InputsAcceptLVDS,LVPECL,andCML offers additional gigibit repeater/ translator and Signals crosspoint products in the SN65LVDS100 and • FastSwitchTimeof1.7ns(Typ) SN65LVDS122. • FastPropagationDelayof0.65ns(Typ) The SN65LVCP22 uses a fully differential data path • 16LeadSOICandTSSOPPackages to ensure low-noise generation, fast switching times, • Inter-OperatesWithTIA/EIA-644-ALVDS low pulse width distortion, and low jitter. Output channel-to- channel skew is less than 10 ps (typ) and Standard 50 ps (max) to ensure accurate alignment of outputs • OperatingTemperature:–40(cid:176) Cto85(cid:176) C in all applications. Both SOIC and TSSOP package options are available to allow easy upgrade for APPLICATIONS existing solutions, and board area savings where • BaseStations spaceiscritical. • Add/DropMuxes OUTPUTS OPERATING SIMULTANEOUSLY • ProtectionSwitchingforSerialBackplanes • NetworkSwitches/Routers 1 Gbps • OpticalNetworkingLineCards/Switches 223 -1 PRBS OUTPUT 1 • ClockDistribution VCC = 3.3 V |VID| = 200 mV, VIC = 1.2 V Vertical Scale = 200 mV/div OUTPUT 2 500 MHz Horizontal Scale = 300 ps Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2002–2003,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION PACKAGEDESIGNATOR PARTNUMBER(1) SYMBOLIZATION SOIC SN65LVCP22D LVCP22 TSSOP SN65LVCP22PW LVCP22 (1) AddthesuffixRfortapedandreeledcarrier PACKAGE DISSIPATION RATINGS CIRCUITBOARD T £ 25(cid:176) C DERATINGFACTOR(1) T =85(cid:176) C PACKAGE MODEL POWAERRATING ABOVET =25(cid:176) C POWAERRATING A SOIC(D) High-K(2) 1361mW 13.9mW/(cid:176) C 544mW TSSOP(PW) High-K(2) 1074mW 10.7mW/(cid:176) C 430mW (1) Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mountedandwithnoairflow. (2) InaccordancewiththeHigh-KthermalmetricdefinitionsofEIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER TESTCONDITIONS VALUE UNITS D 11.2 q Junction-to-boardthermalresistance (cid:176) C/W JB PW 18.4 D 23.7 q Junction-to-casethermalresistance °C/W JC PW 16.0 Typical V =3.3V,T =25(cid:176) C,1Gbps 198 CC A P Devicepowerdissipation mW D Maximum V =3.6V,T =85(cid:176) C,1Gbps 313 CC A FUNCTIONTABLE SEL0 SEL1 OUT0 OUT1 FUNCTION 0 0 IN0 IN0 1:2Splitter 0 1 IN0 IN1 Repeater 1 0 IN1 IN0 Switch 1 1 IN1 IN1 1:2Splitter FUNCTIONALBLOCKDIAGRAM OUT 0 OUT 1 EN 0 EN 1 SEL 1 SEL 0 0 1 0 1 IINN 00 IN 1 2 SubmitDocumentationFeedback

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUTS VCC IN + IN - 400 W SEL, EN 7 V 7 V 300 kW 7 V OUTPUTS VCC OUT + OUT - 7 V 7 V ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerangeunlessotherwisenoted(1) UNITS Supplyvoltage(2)range,V –0.5Vto4V CC CMOS/TTLinputvoltage(ENO,EN1,SEL0,SEL1) –0.5Vto4V LVDSreceiverinputvoltage(IN+,IN–) –0.7Vto4.3V LVDSdriveroutputvoltage(OUT+,OUT–) –0.5Vto4V LVDSoutputshortcircuitcurrent Continuous Storagetemperaturerange –65°Cto125(cid:176) C Leadtemperature1,6mm(1/16inch)fromcasefor10seconds 235(cid:176) C Continuouspowerdissipation SeeDissipationRatingTable Humanbodymodel(3) Allpins – 5kV Electrostaticdischarge Charged-devicemode(4) Allpins – 500V (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundterminals. (3) TestedinaccordancewithJEDECStandard22,TestMethodA114-A. (4) TestedinaccordancewithJEDECStandard22,TestMethodC101. SubmitDocumentationFeedback 3

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltage,V 3 3.3 3.6 V CC Receiverinputvoltage 0 4 V Junctiontemperature 125 (cid:176) C Operatingfree-airtemperature,T (1) –40 85 (cid:176) C A Magnitudeofdifferentialinputvoltage|V | 0.1 3 V ID (1) Maximumfree-airtemperatureoperationisallowedaslongasthedevicemaximumjunctiontemperatureisnotexceeded. INPUT ELECTRICAL CHARACTERISTICS overrecommendedoperatingconditionsunlessotherwisenoted PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT CMOS/TTLDCSPECIFICATIONS(EN0,EN1,SEL0,SEL1) V High-levelinputvoltage 2 V V IH CC V Low-levelinputvoltage GND 0.8 V IL I High-levelinputcurrent V =3.6Vor2.0V,V =3.6V ±3 ±20 µA IH IN CC I Low-levelinputcurrent V =0.0Vor0.8V,V =3.6V ±1 ±10 µA IL IN CC V Inputclampvoltage I =–18mA -0.8 -1.5 V CL CL LVDSOUTPUTSPECIFICATIONS(OUT0,OUT1) R =75W ,SeeFigure2 270 365 475 L |VOD| Differentialoutputvoltage RL=75W ,VCC=3.3V,TA=25°C,See 285 365 440 mV Figure2 D |V | Changeindifferentialoutputvoltagemagnitude V =±100mV,SeeFigure2 –25 25 mV OD betweenlogicstates ID V Steady-stateoffsetvoltage SeeFigure3 1 1.2 1.45 V OS D V Changeinsteady-stateoffsetvoltagebetween SeeFigure3 –25 25 mV OS logicstates V Peak-to-peakcommon-modeoutputvoltage SeeFigure3 50 150 mV OC(PP) I High-impedanceoutputcurrent V =GNDorV ±10 µA OZ OUT CC I Power-offleakagecurrent V =0V,1.5V;V =3.6VorGND ±10 µA OFF CC OUT I Outputshort-circuitcurrent V orV =0V -24 mA OS OUT+ OUT- I Bothoutputsshort-circuitcurrent V andV =0V –12 12 mA OSB OUT+ OUT- C Differentialoutputcapacitance V =0.4sin(4E6p t)+0.5V 3 pF O I LVDSRECEIVERDCSPECIFICATIONS(IN0,IN1) V Positive-goingdifferentialinputvoltagethreshold SeeFigure1andTable1 100 mV TH V Negative-goingdifferentialinputvoltagethreshold SeeFigure1andTable1 –100 mV TL V Differentialinputvoltagehysteresis 25 mV ID(HYS) V Common-modevoltagerange V =100mV,V =3.0Vto3.6V 0.05 3.95 V CMR ID CC V =4V,V =3.6Vor0.0 ±1 ±10 IN CC I Inputcurrent µA IN V =0V,V =3.6Vor0.0 ±1 ±10 IN CC C Differentialinputcapacitance V =0.4sin(4E6p t)+0.5V 3 pF IN I SUPPLYCURRENT R =75W ,C =5pF,500MHz(1000 I Totalsupplycurrent L L 60 87 mA CCD Mbps),EN0=EN1=High I 3-statesupplycurrent EN0=EN1=Low 25 35 mA CCZ (1) Alltypicalvaluesareat25(cid:176) Candwitha3.3-Vsupply. 4 SubmitDocumentationFeedback

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 SWITCHING CHARACTERISTICS overrecommendedoperatingconditionsunlessotherwisenoted parameter TESTCONDITIONS MIN TYP MAX UNIT t InputtoSELsetuptime SeeFigure6 1 0.5 ns SET t InputtoSELholdtime SeeFigure6 1.1 0.5 ns HOLD t SELtoswitchedoutput SeeFigure6 1.7 2.5 ns SWITCH t Disabletime,high-level-to-high-impedance SeeFigure5 2 4 ns PHZ t Disabletime,low-level-to-high-impedance SeeFigure5 2 4 ns PLZ t Enabletime,high-impedance-to-high-leveloutput SeeFigure5 2 4 ns PZH t Enabletime,high-impedance-to-low-leveloutput SeeFigure5 2 4 ns PZL t Differentialoutputsignalrisetime(20%-80%)(1) C =5pF,SeeFigure4 150 280 450 ps LHT L t Differentialoutputsignalfalltime(20%-80%)(1) C =5pF,SeeFigure4 150 280 450 ps HLT L V =200mV,50%dutycycle, ID 20 40 ps V =1.2V,500MHz,C =5pF CM L t Addedpeak-to-peakjitter JIT V =200mV,PRBS=223-1datapattern, ID 50 105 ps V =1.2Vat1000Mbps,C =5pF CM L V =200mV,50%dutycycle, t Addedrandomjitter(rms) ID 1.1 1.8 ps Jrms V =1.2Vat500MHz,C =5pF RMS CM L t Propagationdelaytime,low-to-high-leveloutput(1) 400 650 1000 ps PLHD t Propagationdelaytime,high-to-low-leveloutput(1) 400 650 1000 ps PHLD t Pulseskew(|t –t |)(2) C =5pF,SeeFigure4 20 100 ps skew PLHD PHLD L t Outputchannel-to-channelskew,splittermode C =5pF,SeeFigure4 10 50 ps CCS L f Maximumoperatingfrequency(3) 1 GHz MAX (1) Input:V =1.2V,V =200mV,50%dutycycle,1MHz,t/t =500ps IC ID r f (2) t isthemagnitudeofthetimedifferencebetweenthet andt ofanyoutputofasingledevice. skew PLHD PHLD (3) Signalgeneratorconditions:50%dutycycle,t ort £ 100ps(10%to90%),transmitteroutputcriteria:dutycycle=45%to55%V ‡ r f OD 300mV. PIN ASSIGNMENTS D or PW PACKAGE (TOP VIEW) SEL1 1 16 EN0 SEL0 2 15 EN1 IN0+ 3 14 OUT0+ IN0- 4 13 OUT0- VCC 5 12 GND IN1+ 6 11 OUT1+ IN1- 7 10 OUT1- NC 8 9 NC NC - No internal connection SubmitDocumentationFeedback 5

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 PARAMETER MEASUREMENT INFORMATION IIN+ OUT + IN+ VID VOD IN+ + IN- VIC VIN+ IN- OUT - VOY VOUT++ VOUT- 2 VIN- IIN- VOZ 2 Figure1.VoltageandCurrentDefinitions 3.74 kW Y VOD 75 W _+ 0 V ≤ V(test) ≤ 2.4 V Z 3.74 kW Figure2.DifferentialOutputVoltage(V )TestCircuit OD IN+ ≈1.4 V 37.4 W ±1% IN+ OUT+ IN- ≈1 V VID VOC(PP) VOS IN- OUT- 1 pF VOS 37.4 W ±1% VOC NOTE: All input pulses are supplied by a generator having the following characteristics: t or t £ 1 ns, pulse-repetition rate r f (PRR)=0.5Mpps,pulsewidth=500±10ns;R =100W ;C includesinstrumentationandfixturecapacitancewithin L L 0,06 mm of the D.U.T.; the measurement of V is made on test equipment with a –3 dB bandwidth of at least OC(PP) 300MHz. Figure3.TestCircuitandDefinitionsfortheDriverCommon-ModeOutputVoltage 6 SubmitDocumentationFeedback

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 PARAMETER MEASUREMENT INFORMATION (continued) OUT+ IN+ VID 1 pF VOUT+ VOD 75 W VIN+ IN- OUT- VIN- 5 pF VOUT- VIN+ 1.3 V VIN- 1.1 V 0.2 V VID 0 V -0.2 V tPHLD tPLHD +VOD 80% 0 V -VOD 20% Vdiff = (OUT+) - (OUT-) tHLT tLHT NOTE: Allinputpulsesaresuppliedbyageneratorhavingthefollowingcharacteristics:t ort £ .25ns,pulse-repetitionrate r f (PRR)=0.5Mpps,pulsewidth=500±10ns.C includesinstrumentationandfixturecapacitancewithin0,06mmof L theD.U.T. Figure4.TimingTestCircuitandWaveforms 37.4 W ±1% OUT+ 1 V or 1.4 V 1.2 V VOUT+ 37.4 W ±1% EN OUT- 1.2 V 5 pF VOUT- 3 V EN 1.5 V 0 V VOH OUT 50% 1.2 V tPHZ tPZH 1.2 V OUT 50% VOL tPLZ tPZL NOTE: All input pulses are supplied by a generator having the following characteristics: t or t £ 1 ns, pulse-repetition rate r f (PRR)=0.5Mpps,pulsewidth=500±10ns.C includesinstrumentationandfixturecapacitancewithin0,06mmof L theD.U.T. Figure5.EnableandDisableTimeCircuitandDefinitions SubmitDocumentationFeedback 7

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 Table1.ReceiverInputVoltageThresholdTest RESULTINGDIFFERENTIAL RESULTINGCOMMON- APPLIEDVOLTAGES INPUTVOLTAGE MODEINPUTVOLTAGE OUTPUT(1) V V V V IA IB ID IC 1.25V 1.15V 100mV 1.2V H 1.15V 1.25V –100mV 1.2V L 4.0V 3.9V 100mV 3.95V H 3.9V 4.0V –100mV 3.95V L 0.1V 0.0V 100mV 0.05V H 0.0V 0.1V –100mV 0.05V L 1.7V 0.7V 1000mV 1.2V H 0.7V 1.7V –1000mV 1.2V L 4.0V 3.0V 1000mV 3.5V H 3.0V 4.0V –1000mV 3.5V L 1.0V 0.0V 1000mV 0.5V H 0.0V 1.0V –1000mV 0.5V L (1) H=highlevel,L=lowlevel 8 SubmitDocumentationFeedback

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 IN0 IN1 SEL tSET tHOLD OUT IN0 IN1 tSWITCH EN IN0 IN1 SEL tSET tHOLD OUT IN1 IN0 tSWITCH EN NOTE: t andt timesspecifythatdatamustbeinastablestatebeforeandaftermuxcontrolswitches. SET HOLD Figure6.InputtoSelectforBothRisingandFallingEdgeSetupandHoldTimes SubmitDocumentationFeedback 9

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 TYPICAL CHARACTERISTICS DIFFERENTIALOUTPUTVOLTAGE SUPPLYCURRENT PROPAGATIONDELAYTIME vs vs vs RESISTIVELOAD FREQUENCY FREE-AIRTEMPERATURE 600 75 900 − Differential Output Voltage − mVVOD 123450000000000 VTAC C= =2 53°.C3 V − Supply Current − mAICC 2550 VTV|VACICI DC= |= =2= 1 5 3.2°2.C03 0V ,V ,m,V t− Propagation Delay Time − pspd 678752505 VV|IVnCIpCIDCu |= t = = =1 3 .312 0− M0V 3 ,Hm.6zVt PVL,HtPHL 0 0 600 0 40 80 120 160 200 0 400 800 1200 1600 2000 −60 −40 −20 0 20 40 60 80 100 Resistive Load − W f − Frequency − MHz TA − Free-Air Temperature − °C Figure7. Figure8. Figure9. PEAK-TO-PEAKJITTER PEAK-TO-PEAKJITTER PEAK-TO-PEAKJITTER vs vs vs FREQUENCY DATARATE FREQUENCY 30 60 30 Peak-to-Peak Jitter − ps 11220505 VTVInACIpC C=u = t6=2 04= 5300 °C.C 03ml ,omVVc,Vk,300 mV 500 mV Peak-to-Peak Jitter − ps 23450000 VTVInACIpC C=u = t=2 4= 5350 °P.0C030R ,mV Bm,VSV, 223 −8100 mV Peak-to-Peak Jitter − ps 11220505 VTVInACIpC C=u = t=2 1= 53. °2C.C3 lV ,oV,c,5k00 mV 600 m40V0 mV 5 10 400 mV 5 300 mV 400 mV 800 mV 600 mV 800 mV 300 mV 00 100 200 300 400 500 600 00 200 400 600 800 1000 1200 00 100 200 300 400 500 600 f − Frequency − MHz Data Rate − Mbps f − Frequency − MHz Figure10. Figure11. Figure12. PEAK-TO-PEAKJITTER PEAK-TO-PEAKJITTER PEAK-TO-PEAKJITTER vs vs vs DATARATE FREQUENCY DATARATE 60 30 60 Peak-to-Peak Jitter − ps 23450000 VTVInACIpC C=u = t=2 6 1= 503. °02P.C3 RVm ,V,BV,S 420203 −m1V 800 mV Peak-to-Peak Jitter − ps 11220505 VTVInACIpC C=u = t=2 1= 53. °6C.C3 lV ,oV,c8,k00 mV 300 mV600 mV Peak-to-Peak Jitter − ps 23450000 VTVInACI5pC C=0u = 0t=2 1= 5m3. °6P.VC3 RV ,V,B,6S0 202 m3 −V1 4008 0m0V mV 10 300 mV 5 10 300 mV 500 mV 0 400 mV 500 mV 0 0 200 400 600 800 1000 1200 0 0 200 400 600 800 1000 1200 0 100 200 300 400 500 600 Data Rate − Mbps f − Frequency − MHz Data Rate − Mbps Figure13. Figure14. Figure15. 10 SubmitDocumentationFeedback

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 TYPICAL CHARACTERISTICS (continued) PEAK-TO-PEAKJITTER PEAK-TO-PEAKJITTER DIFFERENTIALOUTPUTVOLTAGE vs vs vs FREQUENCY DATARATE FREQUENCY 30 60 400 80 Peak-to-Peak Jitter − ps 11220505 VTVInACIpC C=u = 6 t=2 03= 503. °3 C.Cm3 lV ,oVV,c,k400 mV 300 mV Peak-to-Peak Jitter − ps 23450000 VTVInACIpC 6C=u 0= t=02 3= 53m. °3P.C3V RV ,3V,B0,S0 62m02V03 m−51V00 mV 800 mV Differential Output Voltage − mV112233050505000000 Added Random JVTV|VitACItCIe DC= r|= =2= 1 5 3.2°2.C03 0V ,V ,m,V 234567000000Period Jitter − ps 5 10 − D 50 10 800 mV 500 mV 0 VO 0 0 00 100 200 300 400 500 600 0 200 400 600 800 1000 1200 0 400 800 1200 1600 2000 f − Frequency − MHz Data Rate − Mbps f − Frequency − MHz Figure16. Figure17. Figure18. PEAK-TO-PEAKJITTER vs DATARATE 230 VCC = 3.3 V, 200 TA = 25°C, VIC = 1.2 V, er − ps 170 |IVnpIDu|t == 2P0R0B Sm V223 −1 Jitt 140 k a e P 110 o- k-t ea 80 P 50 20 0 500 1000 1500 2000 2500 30003500 Data Rate − Mbps Figure19. SubmitDocumentationFeedback 11

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 APPLICATION INFORMATION TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 3.3 V or 5 V 50 W 3.3 V SN65LVCP22 A ECL B 50 W 50 W 50 W VTT = VCC -2 V VTT Figure20.Low-VoltagePositiveEmitter-CoupledLogic(LVPECL) 3.3 V 50 W 3.3 V 50 W 3.3 V SN65LVCP22 A CML B 50 W 50 W 3.3 V Figure21.Current-ModeLogic(CML) 3.3 V 3.3 V SN65LVCP22 50 W A ECL 50 W B 1.1 kW 1.5 kW VTT 3.3 V VTT = VCC -2 V Figure22.Single-Ended(LVPECL) 3.3 V or 5 V 50 W 3.3 V SN65LVCP22 A LVDS 100 W B 50 W Figure23.Low-VoltageDifferentialSignaling(LVDS) 12 SubmitDocumentationFeedback

SN65LVCP22 www.ti.com SLLS553B–NOVEMBER2002–REVISEDJUNE2003 APPLICATION INFORMATION (continued) IN0 + OUT0 + IN0 - OUT0 - IN1 + OUT1 + IN1 - OUT1 - Figure24.2x2Crosspoint OUT0 + IN + OUT0 - (1 or 2) IN - OUT1 + OUT1 - Figure25.1:2Spitter IN0 + OUT0 + IN0 - OUT0 - IN1 + OUT1 + IN1 - OUT1 - Figure26.DualRepeater IN0 + OUT + IN0 - MUX (1 or 2) IN1 + OUT - IN1 - Figure27.2:1MUX SubmitDocumentationFeedback 13

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LVCP22D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP22 & no Sb/Br) SN65LVCP22DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP22 & no Sb/Br) SN65LVCP22DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP22 & no Sb/Br) SN65LVCP22PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP22 & no Sb/Br) SN65LVCP22PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP22 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LVCP22DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVCP22PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LVCP22DR SOIC D 16 2500 350.0 350.0 43.0 SN65LVCP22PWR TSSOP PW 16 2000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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