(cid:21)(cid:21) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 (cid:1) Qualified for Automotive Applications D PACKAGE (cid:1) (TOP VIEW) Bidirectional Transceiver (cid:1) Meet or Exceed the Requirements of ANSI R 1 8 VCC Standard RS-485 and RE 2 7 B ISO 8482:1987(E) DE 3 6 A (cid:1) High-Speed Low-Power LinBiCMOS D 4 5 GND Circuitry (cid:1) Designed for High-Speed Operation in Both Function Tables Serial and Parallel Applications DRIVER (cid:1) Low Skew INPUT ENABLE OUTPUTS (cid:1) Designed for Multipoint Transmission on D DE A B Long Bus Lines in Noisy Environments H H H L (cid:1) L H L H Very Low Disabled Supply-Current X L Z Z Requirements...200 µA Maximum (cid:1) Wide Positive and Negative Input/Output RECEIVER Bus Voltage Ranges (cid:1) Driver Output Capacity...±60 mA DIFFERENTIAL INPUTS ENABLE OUTPUT A−B RE R (cid:1) Thermal-Shutdown Protection VID ≥ 0.2 V L H (cid:1) Driver Positive-and Negative-Current −0.2 V < VID < 0.2 V L ? Limiting VID ≤ −0.2 V L L X H Z (cid:1) Open-Circuit Fail-Safe Receiver Design Open L H (cid:1) Receiver Input Sensitivity...±200 mV Max H = high level, L = low level, ? = indeterminate, (cid:1) X = irrelevant, Z = high impedance (off) Receiver Input Hysteresis...50 mV Typ (cid:1) Operate From a Single 5-V Supply (cid:1) Glitch-Free Power-Up and Power-Down Protection description/ordering information The SN65LBC176 differential bus transceiver is a monolithic, integrated circuit designed for bidirectional data communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets ANSI Standard RS-485 and ISO 8482:1987(E). (cid:1) ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE‡ PART NUMBER MARKING −40°C to 125°C SOIC − D Tape and reel SN65LBC176QDRQ1 L176Q1 †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated. (cid:22)(cid:16)(cid:23)(cid:12)(cid:19)(cid:7)(cid:17)(cid:13)(cid:23)(cid:2) (cid:12)(cid:18)(cid:17)(cid:18) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2008, Texas Instruments Incorporated (cid:22)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:17)$+(cid:30)! (cid:13)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:22)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:21) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 description (continued) The SN65LBC176 combines a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or V = 0. This port features CC wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Very low device supply current can be achieved by disabling the driver and the receiver. Both the driver and receiver are available as cells in the Texas Instruments LinASIC Library. This transceiver is suitable for ANSI Standard RS-485 and ISO 8482:1987 (E) applications to the extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain limits contained in the ANSI Standard RS-485 and ISO 8482:1987 (E) are not met or cannot be tested over the entire extended temperature range. logic diagram (positive logic) 3 DE 4 D 2 RE 6 1 A R 7 Bus B schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT VCC VCC VCC 100 kΩ NOM 3 kΩ A Port Only NOM A or B Output Input 18 kΩ NOM 100 kΩ NOM 1.1 kΩ B Port Only NOM 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:21) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V Input voltage, V (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.5 V I CC Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T SN65LBC176Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V 12 VVoollttaaggee aatt aannyy bbuuss tteerrmmiinnaall ((sseeppaarraatteellyy oorr ccoommmmoonn mmooddee)),, VVII oorr VVIICC VV −7 High-level input voltage, VIH D, DE, and RE 2 V Low-level input voltage, VIL D, DE, and RE 0.8 V Differential input voltage, VID (see Note 2) ±12 V Driver −60 mA HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt,, IIOOHH Receiver −400 µA Driver 60 LLooww--lleevveell oouuttppuutt ccuurrrreenntt,, IIOOLL mmAA Receiver 8 Operating free-air temperature, TA SN65LBC176Q −40 125 °C NOTE 2: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:21) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VIK Input clamp voltage II = −18 mA −1.5 V VO Output voltage IO = 0 0 6 V | VOD1 | Differential output voltage IO = 0 1.5 6 V VOD3 Differential output voltage Vtest = −7 V to 12 V, See Figure 2, See Note 3 1.1 V | VOD2 | Differential output voltage RL = 54 Ω, See Figure 1, See Note 3 1.1 V Change in magnitude of differential ∆| VOD | output voltage† ±0.2 V 3 VVOOCC CCoommmmoonn--mmooddee oouuttppuutt vvoollttaaggee RRLL == 5544 ΩΩ oorr 110000 ΩΩ,, SSeeee FFiigguurree 11 VV −1 Change in magnitude of ∆| VOC | common-mode output voltage† ±0.2 V OOuuttppuutt ddiissaabblleedd,, VO = 12 V 1 IIOO OOuuttppuutt ccuurrrreenntt See Note 4 VO = −7 V −0.8 mmAA IIH High-level input current VI = 2.4 V −100 µA IIL Low-level input current VI = 0.4 V −100 µA VO = −7 V −250 VO = 0 −150 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt mmAA VO = VCC 225500 VO = 12 V Receiver disabled and driver IICCCC SSuuppppllyy ccuurrrreenntt VNNIoo = lloo 0aa ddor VCC, enabled 1.75 mmAA Receiver and driver disabled 0.25 †∆ | VOD | and ∆ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a low level. NOTES: 3. This device meets the ANSI Standard RS-485 VOD requirements above 0°C only. 4. This applies for both power on and off; refer to ANSI Standard RS-485 for exact conditions. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT td(OD) Differential output delay time 8 31 ns tt(OD) Differential output transition time RRLL == 5544 ΩΩ, CCLL == 5500 ppFF,, 12 ns SSeeee FFiigguurree 33 tsk(p) Pulse skew (|td(ODH) − td(ODL)|) 6 ns tPZH Output enable time to high level RL = 110 Ω, See Figure 4 65 ns tPZL Output enable time to low level RL = 110 Ω, See Figure 5 65 ns tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 105 ns tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 105 ns †All typical values are at VCC = 5 V, TA = 25°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:21) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 SYMBOL EQUIVALENTS DATA SHEET PARAMETER RS-485 VO Voa, Vob | VOD1 | Vo | VOD2 | Vt (RL = 54 Ω) Vt (test termination | VOD3 | measurement 2) ∆ | VOD | || Vt | − | Vt || VOC | Vos | ∆ | VOC | | Vos − Vos | IOS None IO Iia, Iib RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Positive-going input threshold VIT+ voltage VO = 2.7 V, IO = −0.4 mA 0.2 V VIT− Nvoelgtaagtieve-going input threshold VO = 0.5 V, IO = 8 mA −0.2‡ V Hysteresis voltage (VIT+ − VIT−) Vhys (see Figure 4) 50 mV VIK Enable-input clamp voltage II = −18 mA −1.5 V VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 220000 mmVV,, IIOOHH == −−440000 µAA,, SSeeee FFiigguurree 66 22..77 VV VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 220000 mmVV,, IIOOLL == 88 mmAA,, SSeeee FFiigguurree 66 00..4455 VV High-impedance-state output IOZ current VO = 0.4 V to 2.4 V ±20 µA OOtthheerr iinnppuutt == 00 VV,, VI = 12 V 1 IIII LLiinnee iinnppuutt ccuurrrreenntt See Note 5 VI = −7 V −0.8 mmAA IIH High-level enable-input current VIH = 2.7 V −100 µA IIL Low-level enable-input current VIL = 0.4 V −100 µA rI Input resistance 12 kΩ IICCCC SSuuppppllyy ccuurrrreenntt VVII == 00 oorr VVCCCC,, Receiver enabled and driver disabled 3.9 mmAA No load Receiver and driver disabled 0.25 †All typical values are at VCC = 5 V, TA = 25°C. ‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:21) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 15 pF L PARAMETER TEST CONDITIONS MIN MAX UNIT tPLH Propagation delay time, low- to high-level single-ended output 11 37 ns tPHL Propagation delay time, high- to low-level single-ended output VVIIDD == −−11..55 VV ttoo 11..55 VV,, 11 37 ns SSeeee FFiigguurree 77 tsk(p) Pulse skew (|td(ODH) − td(ODL)|) 10 ns tPZH Output enable time to high level 35 ns SSeeee FFiigguurree 88 tPZL Output enable time to low level 35 ns tPHZ Output disable time from high level 35 ns SSeeee FFiigguurree 88 tPLZ Output disable time from low level 35 ns PARAMETER MEASUREMENT INFORMATION 375 Ω RL VOD2 2 VOD3 60 Ω RL VOC Vtest 2 375 Ω Figure 1. Driver V and V Figure 2. Driver V OD OC OD3 3 V Input 1.5 V 1.5 V CL = 50 pF 0 V (see Note B) Generator 50 Ω RL = 54 Ω Output td(ODH) td(ODL) (see Note A) ≈ 2.5 V 90% 3 V Output 50% 50% 10% ≈− 2.5 V tt(OD) tt(OD) TEST CIRCUIT VOLTAGE WAVEFORMS Figure 3. Driver Test Circuit and Voltage Waveforms Output 3 V S1 Input 1.5 V 1.5 V 0 V or 3 V 0 V 0.5 V CL = 50 pF RL = 110 Ω tPZH VOH Generator (see Note B) (see Note A) 50 Ω Output 2.3 V tPHZ Voff ≈ 0 V TEST CIRCUIT VOLTAGE WAVEFORMS Figure 4. Driver Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:21) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 PARAMETER MEASUREMENT INFORMATION 5 V 3 V RL = 110 Ω Input 1.5 V 1.5 V S1 0 V Output 3 V or 0 V tPZL tPLZ CL = 50 pF 5 V (sGeeen Neorateto Ar) 50 Ω (see Note B) Output 2.3 V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS Figure 5. Driver Test Circuit and Voltage Waveforms NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =50Ω. B. CL includes probe and jig capacitance. VID VOH +IOL −IOH VOL Figure 6. Receiver V and V OH OL 3 V Input 1.5 V 1.5 V Generator 51 Ω Output 0 V (see Note A) 1.5 V CL = 15 pF tPLH tPHL VOH (see Note B) Output 0 V 1.3 V 1.3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =50Ω. B. CL includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:8) (cid:21) (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) (cid:21) SGLS211A − OCTOBER 2003 − REVISED MAY 2008 PARAMETER MEASUREMENT INFORMATION S1 1.5 V 2 kΩ S2 −1.5 V 5 V CL = 15 pF 5 kΩ 1N916 or Equivalent (see Note B) Generator (see Note A) 50 Ω S3 TEST CIRCUIT 3 V 3 V S1 to 1.5 V S1 to −1.5 V Input 1.5 V S2 Open Input 1.5 V S2 Closed S3 Closed S3 Opened 0 V 0 V tPZH tPZL VOH ≈ 4.5 V Output 1.5 V Output 1.5 V 0 V VOL 3 V 3 V S1 to 1.5 V S1 to −1.5 V Input 1.5 V S2 Closed Input 1.5 V S2 Closed S3 Closed S3 Closed 0 V 0 V tPHZ tPLZ VOH ≈ 1.3 V Output 0.5 V Output 0.5 V ≈ 1.3 V VOL VOLTAGE WAVEFORMS Figure 8. Receiver Test Circuit and Voltage Waveforms NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =50Ω. B. CL includes probe and jig capacitance. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LBC176QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 J176Q1 & no Sb/Br) SN65LBC176QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 J176Q1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF SN65LBC176-Q1 : •Catalog: SN65LBC176 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LBC176QDRG4Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LBC176QDRG4Q1 SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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