(cid:2)(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 (cid:2) Bidirectional Transceiver D, JG, OR P PACKAGE (cid:2) (TOP VIEW) Meets or Exceeds the Requirements of ANSI Standard TIA/EIA−485−A and R 1 8 VCC ISO 8482:1987(E) RE 2 7 B (cid:2) High-Speed Low-Power LinBiCMOS™ DE 3 6 A Circuitry D 4 5 GND (cid:2) Designed for High-Speed Operation in Both Serial and Parallel Applications (cid:2) Low Skew FK PACKAGE (cid:2) Designed for Multipoint Transmission on (TOP VIEW) Long Bus Lines in Noisy Environments C C CCC (cid:2) N R NV N Very Low Disabled Supply Current ...200 μA Maximum 3 2 1 20 19 (cid:2) NC 4 18 NC Wide Positive and Negative Input/Output RE 5 17 B Bus Voltage Ranges NC 6 16 NC (cid:2) Thermal-Shutdown Protection DE 7 15 A (cid:2) Driver Positive-and Negative-Current NC 8 14 NC 9 10 11 12 13 Limiting (cid:2) Open-Circuit Failsafe Receiver Design C D CD C N NN N (cid:2) Receiver Input Sensitivity...±200 mV Max G (cid:2) Receiver Input Hysteresis...50 mV Typ (cid:2) NC−No internal connection Operates From a Single 5-V Supply (cid:2) Glitch-Free Power-Up and Power-Down Protection Function Tables (cid:2) Available in Q-Temp Automotive DRIVER HighRel Automotive Applications INPUT ENABLE OUTPUTS Configuration Control / Print Support D DE A B Qualification to Automotive Standards H H H L L H L H description X L Z Z The SN55LBC176, SN65LBC176, RECEIVER SN65LBC176Q, and SN75LBC176 differential bus transceivers are monolithic, integrated DIFFERENTIAL INPUTS ENABLE OUTPUT circuits designed for bidirectional data communi- VID = VIA−VIB RE R cation on multipoint bus-transmission lines. They VID ≥ 0.2 V L H are designed for balanced transmission lines and −0.2 V < VID < 0.2 V L ? VID ≤ −0.2 V L L meet ANSI Standard TIA/EIA−485−A (RS-485) X H Z and ISO 8482:1987(E). Open L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright © 2000−2006, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 description (continued) The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 combine a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or V = 0. This port features wide positive and negative common-mode voltage CC ranges, making the device suitable for party-line applications. Very low device supply current can be achieved by disabling the driver and the receiver. These transceivers are suitable for ANSI Standard TIA/EIA−485 (RS-485) and ISO 8482 applications to the extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain limits contained in TIA/EIA−485−A and ISO 8482:1987 (E) are not met or cannot be tested over the entire military temperature range. The SN55LBC176 is characterized for operation from −55°C to 125°C. The SN65LBC176 is characterized for operation from −40°C to 85°C, and the SN65LBC176Q is characterized for operation from −40°C to 125°C. The SN75LBC176 is characterized for operation from 0°C to 70°C. logic symbol† logic diagram (positive logic) 3 DE 3 EN1 DE 2 RE EN2 4 D 2 6 RE D 4 11 7 BA R 1 67 A Bus B 1 R 2 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. AVAILABLE OPTIONS TA PACKAGE PART NUMBER PART MARKING SOP SN75LBC176D 7LB176 00°°CC ttoo 7700°°CC PDIP SN75LBC176P 75LBC176 SOP SN65LBC176D 6LB176 −4400°°CC ttoo 8855°°CC PDIP SN65LBC176P 65LBC176 SOP SN65LBC176QD LB176Q −4400°°CC ttoo 112255°°CC SOP SN65LBC176QDR LB176Q LCCC SNJ55LBC176FK SNJ55LBC176FK −5555°°CC ttoo 112255°°CC CDIP SNJ55LBC176JG SNJ55LBC176 • 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 schematics of inputs and outputs EQUIVALENT OF D, RE, and TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT DE INPUTS VCC VCC VCC 100 kΩ NOM 3 kΩ A Port Only NOM A or B Output Input 18 kΩ NOM 100 kΩ NOM 1.1 kΩ B Port Only NOM absolute maximum ratings† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V Input voltage, V (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.5 V I CC Receiver output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (cid:2)10 mA O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE THMEORDMEALL POWTAE R< 2R5A°TCING DAEBROATVIEN GTA F =A C25T°OCR POWTAE R= 7R0A°TCING POWTAE R= 8R5A°TCING POTWAE =R 1 R10A°TCING Low K† 526 mW 5.0 mW/°C 301 mW 226 mW — DD High K‡ 882 mW 8.4 mW/°C 504 mW 378 mW — P 840 mW 8.0 mW/°C 480 mW 360 mW — JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW FK 1375 mW 11.0 mW/°C 880 mW 715 mW 440 mW †In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3. ‡In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V Voltage at any bus terminal (separately or common mode), VI or VIC −7 12 V High-level input voltage, VIH D, DE, and RE 2 V Low-level input voltage, VIL D, DE, and RE 0.8 V Differential input voltage, VID (see Note 2) −12 12 V Driver −60 mA HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt, IIOH Receiver −400 μA Driver 60 LLooww-lleevveell oouuttppuutt ccuurrrreenntt, IIOL Receiver 8 mmAA Junction temperature, TJ 140 °C SN55LBC176 −55 125 SN65LBC176 −40 85 OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree, TTA °°CC SN65LBC176Q −40 125 SN75LBC176 0 70 NOTE 2: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. • 4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VIK Input clamp voltage II = −18 mA −1.5 V VO Output voltage IO = 0 0 6 V | VOD1 | Differential output voltage IO = 0 1.5 6 V 5555LLBBCC117766,, || VVOD2 || DDiifffferenttiiall outtputt vollttage RRSSeeLL ee== NN55oo44tt eeΩΩ ,,33 SSeeee FFiigguurree 11,, 666555LLLBBBCCC111777666,Q, 11..11 VV 75LBC176 1.5 5 55LCB176, VOD3 Differential output voltage VSSeeteeest NN=oo −ttee7 33V to 12 V, SSee Figure 2, 666555LLLCCBCBB111777666,Q 11.11 V 75LBC176 1.5 5 Change in magnitude of differential Δ| VOD | output voltage† −0.2 0.2 V VOC Common-mode output voltage RRLL = 5544 ΩΩ oorr 110000 ΩΩ,, SSeeee FFiigguurree 11 −1 3 V Change in magnitude of Δ| VOC | common-mode output voltage† −0.2 0.2 V OOuuttppuutt ddiissaabblleedd,, VO = 12 V 1 IIO OOuuttppuutt ccuurrrreenntt See Note 4 VO = −7 V −0.8 mmAA IIH High-level input current VI = 2.4 V −100 μA IIL Low-level input current VI = 0.4 V −100 μA VO = −7 V −250 VO = 0 −150 IIOS SShhoorrtt-cciirrccuuiitt oouuttppuutt ccuurrrreenntt VO = VCC mmAA 225500 VO = 12 V 55LBC176, 1.75 RReecceeiivveerr ddiissaabblleedd 65LBC176Q and driver enabled 65LBC176, 1.5 IICC SSuuppppllyy ccuurrrreenntt VVNIIo == l o00a doorr VVCCCC,, 7555LLBBCC117766, mmAA 0.25 RReecceeiivveerr aanndd ddrriivveerr 65LBC176Q disabled 65LBC176, 0.2 75LBC176 †Δ | VOD | and Δ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a low level. NOTES: 3. This device meets the VOD requirements of TIA/EIA−485−A above 0°C only. 4. This applies for both power on and off; refer to TIA/EIA−485−A for exact conditions. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 switching characteristics over recommended ranges of supply voltage and operating free-air temperature SN55LBC176 SN65LBC176 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS SN65LBC176Q SN75LBC176 UUNNIITT MIN TYP MAX MIN TYP† MAX td(OD) Differential output delay time 8 31 8 25 ns tt(OD) Differential output transition time RRSSeeL ee= FF55ii44gg uuΩΩrree, 33 CCL = 5500 pFF, 12 12 ns tsk(p) Pulse skew (|td(ODH) − td(ODL)|) 6 0 6 ns tPZH Output enable time to high level RL = 110 Ω, See Figure 4 65 35 ns tPZL Output enable time to low level RL = 110 Ω, See Figure 5 65 35 ns tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 105 60 ns tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 105 35 ns †All typical values are at VCC = 5 V, TA = 25°C. SYMBOL EQUIVALENTS DATA SHEET PARAMETER RS-485 VO Voa, Vob | VOD1 | Vo | VOD2 | Vt (RL = 54 Ω) | VOD3 | Vmt (eteasstu treermmeinnat t2io)n Δ | VOD | || Vt | − | Vt || VOC | Vos | Δ | VOC | | Vos − Vos | IOS None IO Iia, Iib • 6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Positive-going input threshold VIT+ voltage VO = 2.7 V, IO = −0.4 mA 0.2 V VIT− Nvoelgtaagtieve-going input threshold VO = 0.5 V, IO = 8 mA −0.2‡ V Vhys H(syeset eFriegsuisre v 4o)ltage (VIT+ − VIT−) 50 mV VIK Enable-input clamp voltage II = −18 mA −1.5 V VVOH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VVSeIIDDe == F 22ig00u00r emm 6VV,, IIOOHH == −440000 μμAA,, 22.77 VV VVOL LLooww-lleevveell oouuttppuutt vvoollttaaggee VVSeIIDDe == F −ig22u00r00e mm6VV,, IIOOLL == 88 mmAA,, 00.4455 VV High-impedance-state output IOZ current VO = 0.4 V to 2.4 V −20 20 μA OOtthheerr iinnppuutt == 00 VV,, VI = 12 V 1 III LLiinnee iinnppuutt ccuurrrreenntt See Note 5 VI = −7 V −0.8 mmAA IIH High-level enable-input current VIH = 2.7 V −100 μA IIL Low-level enable-input current VIL = 0.4 V −100 μA rI Input resistance 12 kΩ Receiver enabled 3.9 mA and driver disabled IICCCC SSuuppppllyy ccuurrrreenntt VNNIoo = ll oo0aa ddor VCC, RReceiiver andd SSSNNN566555LLLBBBCCC111777666,, 00.2255 mA ddrriivveerr ddiissaabblleedd SN65LBC176Q SN75LBC176 0.2 †All typical values are at VCC = 5 V, TA = 25°C. ‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet. NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 15 pF L SN55LBC176 SN65LBC176 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS SN65LBC176Q SN75LBC176 UUNNIITT MIN MAX MIN TYP† MAX Propagation delay time, low- to high-level tPLH single-ended output 11 37 11 33 ns Propagation delay time, high- to low-level VVID = −11.55 VV tto 11.55 VV, tPHL single-ended output See Figure 7 11 37 11 33 ns tsk(p) Pulse skew (|tPLH − tPHL|) 10 3 6 ns tPZH Output enable time to high level 35 35 ns SSeeee FFiigguurree 88 tPZL Output enable time to low level 35 30 ns tPHZ Output disable time from high level 35 35 ns SSeeee FFiigguurree 88 tPLZ Output disable time from low level 35 30 ns †All typical values are at VCC = 5 V, TA = 25°C. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION 375 Ω RL VOD2 2 VOD3 60 Ω RL VOC Vtest 2 375 Ω Figure 1. Driver V and V Figure 2. Driver V OD OC OD3 3 V Input 1.5 V 1.5 V CL = 50 pF 0 V (see Note B) Generator 50 Ω RL = 54 Ω Output td(ODH) td(ODL) (see Note A) ≈ 2.5 V 90% 3 V Output 50% 50% 10% ≈− 2.5 V tt(OD) tt(OD) TEST CIRCUIT VOLTAGE WAVEFORMS Figure 3. Driver Test Circuit and Voltage Waveforms Output 3 V S1 Input 1.5 V 1.5 V 0 V or 3 V 0 V 0.5 V CL = 50 pF RL = 110 Ω tPZH VOH Generator (see Note B) (see Note A) 50 Ω Output 2.3 V tPHZ Voff ≈ 0 V TEST CIRCUIT VOLTAGE WAVEFORMS Figure 4. Driver Test Circuit and Voltage Waveforms 5 V 3 V RL = 110 Ω Input 1.5 V 1.5 V S1 0 V Output 3 V or 0 V tPZL tPLZ CL = 50 pF 5 V (sGeeen Neorateto Ar) 50 Ω (see Note B) Output 2.3 V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS Figure 5. Driver Test Circuit and Voltage Waveforms NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =50Ω. B. CL includes probe and jig capacitance. • 8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION VID VOH VOL +IOL −IOH Figure 6. Receiver V and V OH OL 3 V Input 1.5 V 1.5 V Generator 51 Ω Output 0 V (see Note A) 1.5 V CL = 15 pF tPLH tPHL VOH (see Note B) Output 0 V 1.3 V 1.3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =50Ω. B. CL includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms THERMAL CHARACTERISTICS − D PACKAGE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K board, no air flow 199.4 JJuunnccttiioonn−ttoo−aammbbiieenntt tthheerrmmaall rreeiissiissttaannccee, θθJA†† High-K board, no air flow 119 °°CC//WW Junction−to−board thermal reisistance, θJB High-K board, no air flow 67 Junction−to−case thermal reisistance, θJC 46.6 RL = 54 Ω, input to D is 10 Mbps 50% duty Average power dissipation, P(AVG) cycle square wave, VCC = 5.25 V, 330 mW TJ = 130 °C. Thermal shutdown junction temperature, TSD 165 °C †See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION S1 1.5 V 2 kΩ S2 −1.5 V 5 V CL = 15 pF 5 kΩ 1N916 or Equivalent (see Note B) Generator (see Note A) 50 Ω S3 TEST CIRCUIT 3 V 3 V S1 to 1.5 V S1 to −1.5 V Input 1.5 V S2 Open Input 1.5 V S2 Closed S3 Closed S3 Opened 0 V 0 V tPZH tPZL VOH ≈ 4.5 V Output 1.5 V Output 1.5 V 0 V VOL 3 V 3 V S1 to 1.5 V S1 to −1.5 V Input 1.5 V S2 Closed Input 1.5 V S2 Closed S3 Closed S3 Closed 0 V 0 V tPHZ tPLZ VOH ≈ 1.3 V Output 0.5 V Output 0.5 V ≈ 1.3 V VOL VOLTAGE WAVEFORMS Figure 8. Receiver Test Circuit and Voltage Waveforms NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =50Ω. B. CL includes probe and jig capacitance. • 10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 THERMAL CHARACTERISTICS OF IC PACKAGES Θ (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature JA divided by the operating power Θ is NOT a constant and is a strong function of JA (cid:2) the PCB design (50% variation) (cid:2) altitude (20% variation) (cid:2) device power (5% variation) Θ can be used to compare the thermal performance of packages if the specific test conditions are defined and used. JA Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4% to 50% difference in Θ can be measured between these two test cards JA Θ (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the JC operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. Θ is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict JC junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. It can be used with Θ in 1-dimensional thermal simulation of a package system. JB Θ (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB JB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. Θ is only JB defined for the high-k test card. Θ provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance JB (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 1). Ambient Node (cid:2)CA Calculated Surface Node (cid:2)JC Calculated/Measured Junction (cid:2)JB Calculated/Measured PC Board Figure 1. Thermal Resistance • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 MECHANICAL INFORMATION D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.010 (0,25) M 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°−(cid:2)8° 0.044 (1,12) A 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX 0.004 (0,10) PINS ** 8 14 16 DIM 0.197 0.344 0.394 A MAX (5,00) (8,75) (10,00) 0.189 0.337 0.386 A MIN (4,80) (8,55) (9,80) 4040047/D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012 • 12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

(cid:2) SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 MECHANICAL INFORMATION FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINALS SHOWN NO. OF A B 18 17 16 15 14 13 12 TERMINALS MIN MAX MIN MAX ** 0.342 0.358 0.307 0.358 19 11 20 (8,69) (9,09) (7,80) (9,09) 20 10 0.442 0.458 0.406 0.458 28 (11,23) (11,63) (10,31) (11,63) 21 9 B SQ 0.640 0.660 0.495 0.560 44 22 8 (16,26) (16,76) (12,58) (14,22) A SQ 23 7 0.740 0.761 0.495 0.560 52 (18,78) (19,32) (12,58) (14,22) 24 6 0.938 0.962 0.850 0.858 68 (23,83) (24,43) (21,6) (21,8) 25 5 1.141 1.165 1.047 1.063 84 (28,99) (29,59) (26,6) (27,0) 26 27 28 1 2 3 4 0.020 (0,51) 0.080 (2,03) 0.010 (0,25) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.045 (1,14) 0.022 (0,54) 0.035 (0,89) 0.050 (1,27) 4040140/C 11/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold-plated. E. Falls within JEDEC MS-004 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 (cid:2) DIFFERENTIAL BUS TRANSCEIVERS (cid:2) SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010 MECHANICAL INFORMATION JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE 0.400 (10,20) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.020 (0,51) MIN 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.063 (1,60) 0°−15° 0.015 (0,38) 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. E. Falls within MIL-STD-1835 GDIP1-T8 • 14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MPDI001A − JANUARY 1995 − REVISED JUNE 1999 MECHANICAL INFORMATION P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.020 (0,51) MIN 0.300 (7,62) 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.010 (0,25) M 0.015 (0,38) 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9318301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9318301Q2A SNJ55 LBC176FK 5962-9318301QPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9318301QPA SNJ55LBC176 SN65LBC176D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 6LB176 & no Sb/Br) SN65LBC176DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 6LB176 & no Sb/Br) SN65LBC176DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 6LB176 & no Sb/Br) SN65LBC176P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 65LBC176 & no Sb/Br) SN65LBC176QD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LB176Q & no Sb/Br) SN65LBC176QDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LB176Q & no Sb/Br) SN65LBC176QDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LB176Q & no Sb/Br) SN65LBC176QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (J176Q1, LB176Q) & no Sb/Br) SN75LBC176D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7LB176 & no Sb/Br) SN75LBC176DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7LB176 & no Sb/Br) SN75LBC176DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7LB176 & no Sb/Br) SN75LBC176P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 75LBC176 & no Sb/Br) SNJ55LBC176FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9318301Q2A SNJ55 LBC176FK Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SNJ55LBC176JG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9318301QPA SNJ55LBC176 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN55LBC176, SN65LBC176, SN75LBC176 : •Catalog: SN75LBC176 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Automotive: SN65LBC176-Q1 •Military: SN55LBC176 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LBC176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LBC176QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LBC176QDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75LBC176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LBC176DR SOIC D 8 2500 340.5 338.1 20.6 SN65LBC176QDR SOIC D 8 2500 350.0 350.0 43.0 SN65LBC176QDRG4 SOIC D 8 2500 350.0 350.0 43.0 SN75LBC176DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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