Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 SN65HVD485E Half-Duplex RS-485 Transceiver 1 Features 3 Description • Bus-PinESDProtectionupto15kV The SN65HVD485E device is a half-duplex 1 transceiver designed for RS-485 data bus networks. • 1/2UnitLoad:upto64NodesonaBus Powered by a 5-V supply, it is fully compliant with the • Bus-Open-FailsafeReceiver TIA/EIA-485A standard. This device is suitable for • Glitch-FreePower-UpandPower-DownBus data transmission up to 10 Mbps over long twisted- InputsandOutputs pair cables and is designed to operate with very low supply current, typically less than 2 mA, exclusive of • AvailableinSmallVSSOP-8Package the load. When the device is in the inactive shutdown • MeetsorExceedstheRequirementsofthe mode,thesupplycurrentdropsbelow1mA. TIA/EIA-485AStandard The wide common-mode range and high ESD • Industry-StandardSN75176Footprint protection levels of this device make it suitable for demanding applications such as: electrical inverters, 2 Applications status/command signals across telecom racks, cabled chassis interconnects, and industrial • MotorControl automation networks where noise tolerance is • PowerInverters essential. The SN65HVD485E device matches the • IndustrialAutomation industry-standard footprint of the SN75176 device. • BuildingAutomationNetworks Power-on reset circuits keep the outputs in a high- impedance state until the supply voltage has • IndustrialProcessControl stabilized. A thermal-shutdown function protects the • Battery-PoweredApplications device from damage due to system-fault conditions. • TelecommunicationsEquipment The SN65HVD485E device is characterized for operationfrom–40°Cto85°Cairtemperature. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(8) 4.91mm×3.90mm SN65HVD485E VSSOP(8) 3.00mm×3.00mm PDIP(8) 9.81mm×6.35mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. TypicalApplicationSchematic R R R R A A RE RE B RT RT B DE DE D D D D A B A B R R D D R RE DE D R RE DE D 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription............................................ 12 2 Applications........................................................... 1 9.1 Overview.................................................................12 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.......................................12 4 RevisionHistory..................................................... 2 9.3 FeatureDescription.................................................12 9.4 DeviceFunctionalModes........................................12 5 DeviceComparisonTable..................................... 3 10 ApplicationandImplementation........................ 14 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................14 7 Specifications......................................................... 4 10.2 TypicalApplication ...............................................14 7.1 AbsoluteMaximumRatings......................................4 11 PowerSupplyRecommendations..................... 18 7.2 ESDRatings..............................................................4 12 Layout................................................................... 18 7.3 RecommendedOperatingConditions......................4 7.4 ThermalInformation..................................................5 12.1 LayoutGuidelines.................................................18 7.5 ElectricalCharacteristics:Driver...............................5 12.2 LayoutExample....................................................18 7.6 ElectricalCharacteristics:Receiver..........................5 13 DeviceandDocumentationSupport................. 19 7.7 PowerDissipationCharacteristics............................6 13.1 DeviceSupport......................................................19 7.8 SupplyCurrent..........................................................6 13.2 DocumentationSupport........................................20 7.9 SwitchingCharacteristics:Driver..............................6 13.3 CommunityResources..........................................20 7.10 SwitchingCharacteristics:Receiver........................6 13.4 Trademarks...........................................................20 7.11 DissipationRatings.................................................7 13.5 ElectrostaticDischargeCaution............................20 7.12 TypicalCharacteristics............................................7 13.6 Glossary................................................................20 8 ParameterMeasurementInformation..................8 14 Mechanical,Packaging,andOrderable Information........................................................... 20 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(July2015)toRevisionE Page • Changed3.3VTo:5VatpinV inFigure20................................................................................................................... 16 CC ChangesfromRevisionC(March2007)toRevisionD Page • AddedPinConfigurationandFunctionssection,FeatureDescriptionsection,DeviceFunctionalModes,Application andImplementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation Supportsection,andMechanical,Packaging,andOrderableInformationsection ............................................................... 1 • DeletedOrderingInformationtable ....................................................................................................................................... 1 • ChangedThermalInformationtable ...................................................................................................................................... 5 • AddedPowerDissipationCharacteristicstable...................................................................................................................... 6 2 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 5 Device Comparison Table ImprovedReplacementforDevices PARTNUMBER REPLACEWITH BENEFITS BetterESDprotection(±15kVversusunspecified) ADM485 SN65HVD485E Fastersignalingrate(10Mbpsversus5Mbps) Morenodesonabus(64versus32)Widerpowersupplytolerance(10%vs5%) Morenodesonabus(64versus32) SP485E SN65HVD485E Widerpowersupplytolerance(10%versus5%) Highersignalingrate(10Mbpsversus2.5Mbps) LMS485E SN65HVD485E Morenodesonabus(64versus32) Widerpowersupplytolerance(10%versus5%) Highersignalingrate(10Mbpsversus2.5Mbps) BetterESD(±15kVversus±2kV) DS485 SN65HVD485E Morenodesonabus(64versus32) Widerpowersupplytolerance(10%versus5%) BetterESD(±15kVversus±2kV) LTC485 SN65HVD485E Widerpowersupplytolerance(10%versus5%) Highersignalingrate(10Mbpsversus2.5Mbps) MAX485E SN65HVD485E Morenodesonabus(64versus32) Widerpowersupplytolerance(10%versus5%) Highersignalingrate(10Mbpsversus5Mbps) ST485E SN65HVD485E Widerpowersupplytolerance(10%versus5%) Morenodesonabus(64versus32) ISL8485E SN65HVD485E Fastersignalingrate(10Mbpsversus5Mbps) 6 Pin Configuration and Functions D,DGK,PPackages 8-PinSOIC,VSSOP,PDIP TopView R 1 8 VCC RE 2 7 B DE 3 6 A D 4 5 GND PinFunctions PIN TYPE DESCRIPTION NAME NO. A 6 Businput/output Driveroutputorreceiverinput(complementarytoB) B 7 Businput/output Driveroutputorreceiverinput(complementarytoA) D 4 Digitalinput Driverdatainput DE 3 Digitalinput Driverenable,activehigh GND 5 Referencepotential Localdeviceground R 1 Digitalinput Receivedataoutput RE 2 Digitalinput Receiverenable,activelow V 8 Supply 4.5-Vto5.5-Vsupply CC Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) (2) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC VoltagerangeatAorB –9 14 V Voltagerangeatanylogicpin –0.3 V +0.3 V CC Receiveroutputcurrent –24 24 mA Voltageinputrange,transientpulse,AandB,through100Ω(seeFigure15) –50 50 V T Junctiontemperature 170 170 °C J Continuoustotalpowerdissipation RefertoDissipationRatings T Storagetemperature –65 130 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundterminal. 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS- BuspinsandGND ±15000 V Electrostatic 001(1) Allpins ±4000 V (ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN NOM MAX UNIT V Supplyvoltage 4.5 5.5 V CC V Inputvoltageatanybusterminal(separatelyorcommonmode) –7 12 V I V High-levelinputvoltage(D,DE,orREinputs) 2 V V IH CC V Low-levelinputvoltage(D,DE,orREinputs) 0 0.8 V IL V Differentialinputvoltage –12 12 V ID Driver –60 60 I Outputcurrent mA O Receiver –8 8 R Differentialloadresistance 54 60 Ω L 1/t Signalingrate 0 10 Mbps UI T Operatingfree-airtemperature –40 85 °C A T Junctiontemperature(2) –40 130 °C J (1) Thealgebraicconvention,inwhichtheleastpositive(mostnegative)limitisdesignatedasminimum,isusedinthisdatasheet. (2) SeeThermalInformationforinformationonmaintenanceofthisspecificationfortheDGKpackage. 4 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 7.4 Thermal Information SN65HVD485E THERMALMETRIC(1) D DGK P UNIT (SOIC) (VSSOP) (PDIP) 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance(2) 127 180 153 °C/W θJA R Junction-to-case(top)thermalresistance 51.4 66 40.5 °C/W θJC(top) R Junction-to-boardthermalresistance 47.6 108 28.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 7.9 4.6 17.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 47 73.1 28.3 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report(SPRA953). (2) SeethePackageThermalCharacterizationMethodologiesapplicationnote(SZZA003)foranexplanationofthisparameter. 7.5 Electrical Characteristics: Driver overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT I =0,Noload 3 4.3 O |V | Differentialoutputvoltage R =54W(seeFigure3) 1.5 2.3 V OD L V =–7Vto12V(seeFigure4) 1.5 TEST Changeinmagnitudeofdifferentialoutput Δ|V | SeeFigure3andFigure4 –0.2 0 0.2 V OD voltage V Steady-statecommon-modeoutputvoltage SeeFigure5 1 2.6 3 V OC(SS) Changeinsteady-statecommon-modeoutput ΔV –0.1 0 0.1 V OC(SS) voltage V Common-modeoutputvoltage SeeFigure5 500 mV OC(PP) I High-impedanceoutputcurrent Seereceiverinputcurrents μA OZ I Inputcurrent D,DE –100 100 μA I I Short-circuitoutputcurrent –7V≤V ≤12V(seeFigure9) –250 250 mA OS O (1) Alltypicalvaluesareat25°Candwitha5-Vsupply. 7.6 Electrical Characteristics: Receiver overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT V Positive-goinginputthresholdvoltage I =–8mA –85 –10 mV IT+ O V Negative-goinginputthresholdvoltage I =8mA –200 –115 mV IT– O V Hysteresisvoltage(V –V ) 30 mV hys IT+ IT– V High-leveloutputvoltage V =200mV,I =–8mA(seeFigure10) 4 4.6 V OH ID OH V Low-leveloutputvoltage V =–200mV,I =8mA(seeFigure10) 0.15 0.4 V OL ID OH I High-impedance-stateoutputcurrent V =0toV ,RE=V –1 1 μA OZ O CC CC V =12V,V =5V 0.5 IH CC V =12V,V =0 0.5 IH CC I Businputcurrent mA I V =–7V,V =5V –0.4 IH CC V =–7V,V =0 –0.4 IH CC I High-levelinputcurrent(RE) V =2V –60 –30 μA IH IH I Low-levelinputcurrent(RE) V =0.8V –60 –30 μA IL IL C Differentialinputcapacitance V =0.4sin(4E6πt)+0.5V,DEat0V 7 pF diff I (1) Alltypicalvaluesareat25°Candwitha5-Vsupply. Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com 7.7 Power Dissipation Characteristics PARAMETER TESTCONDITIONS MIN TYP MAX UNIT R =54Ω,InputtoDisa10Mbps50%dutycyclesquare P Averagepowerdissipation L 219 mW (AVG) waveV at5.5V,T =130°C CC J Thermalshut-downjunction T 165 °C SD temperature 7.8 Supply Current overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT Driverandreceiverenabled DatV oropenor0V, DEatV ,REat0V,Noload 2 mA CC CC ICC Driverandreceiver DatV oropen, DEat0V,REatV 1 mA disabled CC CC (1) Alltypicalvaluesareat25°Candwitha5-Vsupply. 7.9 Switching Characteristics: Driver overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Propagationdelaytime,low-to-high-leveloutput 30 ns PLH t Propagationdelaytime,high-to-low-leveloutput 30 ns PHL t Differentialoutputsignalrisetime R =54Ω,C =50pF(seeFigure6) 25 ns r L L t Differentialoutputsignalfalltime 25 ns f t Pulseskew(|t –t |) 5 ns sk(p) PHL PLH Propagationdelaytime,high-impedance-to-high-level t 150 ns PZH output R =110Ω,REat0V(seeFigure7) L Propagationdelaytime,high-level-to-high-impedance t 100 ns PHZ output Propagationdelaytime,high-impedance-to-low-level t 150 ns PZL output R =110Ω,REat0V(seeFigure8) L Propagationdelaytime,low-level-to-high-impedance t 100 ns PLZ output Propagationdelaytime,shutdown-to-high-level t R =110Ω,REatVCC(seeFigure7) 2600 ns PZH(SHN) output L t Propagationdelaytime,shutdown-to-low-leveloutput R =110Ω,REatVCC(seeFigure8) 2600 ns PZL(SHDN) L 7.10 Switching Characteristics: Receiver overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Propagationdelaytime,low-to-high-leveloutput 200 ns PLH t Propagationdelaytime,high-to-low-leveloutput 200 ns PHL V =-1.5Vto1.5V,C =15pF t Pulseskew(|t –t |) ID L 6 ns sk(p) PHL PLH (seeFigure11) t Outputsignalrisetime 3 ns r t Outputsignalfalltime 3 ns f t Outputenabletimetohighlevel 50 ns PZH tPZL Outputenabletimetolowlevel CL=15pF,DEat3V, 50 ns t Outputenabletimefromhighlevel (seeFigure12andFigure13) 50 ns PHZ t Outputenabletimefromlowlevel 50 ns PLZ Propagationdelaytime,shutdown-to-high-level t 3500 ns PZH(SHDN) output C =15pF,DEat0V, L Propagationdelaytime,shutdown-to-low-level (seeFigure14) t 3500 ns PZL(SHDN) output 6 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 7.11 Dissipation Ratings PACKAGE(1) JEDECBOARD TA<25°C DERATINGFACTOR(2) TA=70°C TA=85°C MODEL POWERRATING ABOVET =25°C POWERRATING POWERRATING A D Lowk(3) 507mW 4.82mW/°C 289mW 217mW (SIOC) Highk(3) 824mW 7.85mW/°C 471mW 353mW P Lowk(3) 686mW 6.53mW/°C 392mW 294mW (PDIP) DGK Lowk(3) 394mW 3.76mW/°C 255mW 169mW (VSSOP) Highk(4) 583mW 5.55mW/°C 333mW 250mW (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mountedandwithnoairflow. (3) Inaccordancewiththelow-kthermalmetricdefinitionsofEIA/JESD51-3. (4) Inaccordancewiththehigh-kthermalmetricdefinitionsofEIA/JESDS1-7. 7.12 Typical Characteristics 80 5 TA= 25°C 60 −V 4.5 VCC= 5 V RL= 120Ω A e 4 µ ag nt− 40 oltV 3.5 re ut Cur 20 VCC= 0 V utp 3 RL= 60Ω ut Bias 0 VCC= 5 V ential O 2.52 p r −In −20 Diffe 1.5 II − OD 1 −40 V 0.5 −60 0 −8 −6 −4 −2 0 2 4 6 8 10 12 0 10 20 30 40 50 VI−Bus Input Voltage−V IO−Differential Output Current−mA Figure1.BusInputCurrentvsBusInputVoltage Figure2.DriverDifferentialOutputVoltage vsDifferentialOutputCurrent Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com 8 Parameter Measurement Information Testloadcapacitanceincludesprobeandjigcapacitance(unlessotherwisespecified).Signalgenerator characteristics:risetimeandfalltime <6ns,pulserate100kHz,50%dutycycle.Z =50Ω (unless O otherwisespecified). II A IOA 27Ω 0 V or 3 V VOD 50 pF D 27Ω B IOB VOC Figure3. DriverTestCircuit,V andV WithoutCommon-ModeLoading OD OC 375Ω V =−7 V to 12 V TEST 0 V or 3 V VOD 60Ω 375Ω V TEST Figure4. DriverTestCircuit,V WithCommon-ModeLoading OD 27Ω A VA 3.25 V D Signal B 27Ω VB 1.75 V Generator 50Ω VOC VOC(PP) ∆VOC(SS) 50 pF VOC Figure5. DriverV TestCircuitandWaveforms OC 3 V INPUT 1.5 V 1.5 V 0 V RL= 54Ω VOD tPLH tPHL Signal CL= 50 pF 90% VOD(H) Generator 50Ω OUTPUT 0 V 10% VOD(L) tr tf Figure6. DriverSwitchingTestCircuitandWaveforms 8 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 Parameter Measurement Information (continued) Testloadcapacitanceincludesprobeandjigcapacitance(unlessotherwisespecified).Signalgeneratorcharacteristics:rise timeandfalltime<6ns,pulserate100kHz,50%dutycycle.Z =50Ω(unlessotherwisespecified). O A S1 D Output 3 V 0 V or 3 V B DE 1.5 V 1.5 V 3 V if Testing A Output 0 V 0 V if Testing B Output CL= 50 pF RL= 110Ω tPZH 0.5 V DE VOH Signal Output 2.5 V Generator 50Ω VOff0 tPHZ Figure7. DriverEnable/DisableTestCircuitandWaveforms,HighOutput 5 V A RL= 110Ω S1 D 3 V 0 V or 3 V B Output DE 1.5 V 1.5 V 0 V if Testing A Output 0 V 3 V if Testing B Output CL= 50 pF tPZL DE tPLZ 5 V Signal Output 2.5 V Generator 50Ω VOL 0.5 V Figure8. DriverEnable/DisableTestCircuitandWaveforms,LowOutput IOS VO Voltage Source Figure9. DriverShort-CircuitTest IO VID VO Figure10. ReceiverParameterDefinitions Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com Parameter Measurement Information (continued) Testloadcapacitanceincludesprobeandjigcapacitance(unlessotherwisespecified).Signalgeneratorcharacteristics:rise timeandfalltime<6ns,pulserate100kHz,50%dutycycle.Z =50Ω(unlessotherwisespecified). O Signal Generator 50Ω VID Input B 1.5 V A IO Input A 50% B R 0 V tPLH tPHL GeSnigenraatlor 50Ω CL= 15 pF VO Output 1.5 V 90% VOH 10% VOL tr tf Figure11. ReceiverSwitchingTestCircuitandWaveforms D VCC DE VCC A 54Ω B 3 V 1 kΩ R 0 V RE 1.5 V CL= 15 pF 0 V RE tPZH tPHZ GeSnigenraatlor 50Ω VOH R 1.5 V VOH−0.5 V GND Figure12. ReceiverEnable/DisableTestCircuitandWaveforms,DataOutputHigh D 0 V DE VCC A 54Ω B 3 V 1 kΩ R 5 V RE 1.5 V CL= 15 pF 0 V RE tPZL tPLZ GeSnigenraatlor 50Ω VCC R 1.5 V VOL+0.5 V VOL Figure13. ReceiverEnable/DisableTestCircuitandWaveforms,DataOutputLow 10 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 Parameter Measurement Information (continued) Testloadcapacitanceincludesprobeandjigcapacitance(unlessotherwisespecified).Signalgeneratorcharacteristics:rise timeandfalltime<6ns,pulserate100kHz,50%dutycycle.Z =50Ω(unlessotherwisespecified). O VCC Switch Down for V(A)= 1.5 V, A Switch Up for V(A)=−1.5 V 1.5 V or R 3 V −1.5 V B 1 kΩ RE 1.5 V CL= 15 pF 0 V RE tPZH(SHDN) Signal tPZL(SHDN) Generator 50Ω 5 V VOH R 1.5 V 0 V VOL Figure14. ReceiverEnableFromShutdownTestCircuitandWaveforms 100Ω VTEST 0 V Pulse Generator, 15µs Duration, 15µs 1.5 ms −VTEST 1% Duty Cycle Figure15. TestCircuitandWaveforms,TransientOver-VoltageTest Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com 9 Detailed Description 9.1 Overview The SN65HVD485E device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 10 Mbps over controlled-impedance transmission media (such as twisted-pair cabling). Up to 64 units of the SN65HVD485E device can share a common RS-485 bus due to the low bus-input currents of the device. The devicealsofeaturesahighdegreeofESDprotectionandlowstandbycurrentconsumptionof1mA(maximum). 9.2 Functional Block Diagram V CC R RE A DE B D GND 9.3 Feature Description The SN65HVD485E device provides internal biasing of the receiver input thresholds for open-circuit, bus-idle, or short-circuit failsafe conditions. It features a typical hysteresis of 30 mV to improve noise immunity. Internal ESD protection circuits protect the transceiver bus terminals against ±15-kV Human Body Model (HBM) electrostatic discharges. 9.4 Device Functional Modes When the driver enable pin (DE) is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as V = V – V is positive. When D is low, the output states reverse, B turns high, A is low, and V is OD A B OD negative. WhenDEislow,bothoutputsturnhighimpedance.Inthiscondition,thelogicstateatDisirrelevant.TheDEpin has an internal pulldown resistor to ground; thus when left open, the driver is disabled (high impedance) by default. The D pin has an internal pullup resistor to VCC; thus when left open while the driver is enabled, output AturnshighandBturnslow. Table1.DriverFunctionTable INPUT ENABLE OUTPUTS FUNCTION D DE A B H H H L ActivelydrivebusHigh L H L H ActivelydrivebusLow X L Z Z Driverdisabled X OPEN Z Z Driverdisabledbydefault OPEN H H L Activelydrivebushighbydefault When the receiver enable pin (RE) is logic low, the receiver is enabled. When the differential input voltage defined as V = V – V is positive and higher than the positive input threshold (V ) the receiver output (R) ID A B IT+ turns high. When V is negative and lower than the negative input threshold (V ), the receiver output (R) turns ID IT– low.IfV isbetweenV andV ,theoutputisindeterminate. ID IT+ IT– When RE is logic high or left open, the receiver output is high impedance and the magnitude and polarity of V ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idlebus). 12 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 Table2.ReceiverFunctionTable DIFFERENTIALINPUT ENABLE OUTPUT FUNCTION V =V –V RE R ID A B V <V L H ReceivevalidbusHigh IT+ ID V <V <V L ? Indeterminatebusstate IT– ID IT+ V <V L L ReceivevalidbusLow ID IT– X H Z Receiverdisabled X OPEN Z Receiverdisabledbydefault Open-circuitbus L H Fail-safehighoutput Short-circuitbus L H Fail-safehighoutput Idle(terminated)bus L H Fail-safehighoutput D and RE Input DE Input VCC VCC 200 kΩ 500Ω 500Ω Input Input 9 V 9 V 200 kΩ AInput B Input VCC VCC 16 V 36 kΩ 16 V 36 kΩ 180 kΩ 180 kΩ Input Input 36 kΩ 16 V 36 kΩ 16 V Aand B Outputs R Outputs VCC VCC 16 V 5Ω Output Output 16 V 9 V Figure16. EquivalentInputandOutputSchematicDiagrams Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information The SN65HVD485E device is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions.Thedriverandreceiverenablepinsallowforconfigurationofdifferentoperatingmodes. R R R R R R RE A RE A RE A DE B DE B DE B D D D D D D Figure17. Half-DuplexTransceiverConfigurations Usingindependentenablelinesprovidesthemostflexiblecontrolasitallowsforthedriverandthereceivertobe turned on and off individually. While this configuration requires two control lines, it allows for selective listening intothebustrafficwhetherthedriveristransmittingdataornot. Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal. In this configuration, the transceiver operates as a driver when the direction-control line is high and as a receiver whenthedirection-controllineislow. Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only the driver-enable input. In this configuration, a node receives the data from the bus, receives the data it sends, andcanverifythatthecorrectdatahasbeentransmitted. 10.2 Typical Application An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor (R ) whose value matches the characteristic T impedance (Z ) of the cable. This method, known as parallel termination, allows for higher data rates over longer 0 cablelength. R R R R A A RE RE B RT RT B DE DE D D D D A B A B R R D D R RE DE D R RE DE D Figure18. TypicalRS-485NetworkWithHalf-DuplexTransceivers 14 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 Typical Application (continued) 10.2.1 DesignRequirements RS-485 is a robust electrical standard suitable for long-distance networking that can be used in a wide range of applicationswithvaryingrequirementssuchasdistance,datarate,andnumberofnodes. 10.2.1.1 DataRateandBusLength There is an inverse relationship between data rate and bus length: the higher the data rate, the shorter the cable length, and conversely the lower the data rate, the longer the cable can be without introducing data errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of upto5or10%. 10000 5%, 10%, and 20% Jitter h (ft) 1000 gt Conservative n e Characteristics L e bl 100 a C 10 100 1k 10k 100k 1M 10M 100M Data Rate(bps) Figure19. CableLengthvsDataRateCharacteristic 10.2.1.2 StubLength When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, must be as short as possible. Stubs present a nonterminated piece of bus line that can introduce reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub must be less than one-tenth of the rise time of the driver; thus giving a maximum physical stub length as showninEquation1. L ≤0.1×t ×v×c stub r where • t isthe10/90risetimeofthedriver r • cisthespeedoflight(3×108m/s) • visthesignalvelocityofthecableortraceasafactorofc (1) 10.2.1.3 BusLoading TheRS-485standardspecifiesthatacompliantdrivermustbeabletodrive32-unitloads(UL),where1-unitload representsaloadimpedanceofapproximately12kΩ.BecausetheSN65HVD485Edeviceisa ½ULtransceiver, itispossibletoconnectupto64receiverstothebus. 10.2.1.4 ReceiverFailsafe ThedifferentialreceiveroftheSN65HVD485Edeviceisfailsafetoinvalidbusstatescausedbythefollowing: • Openbusconditionssuchasadisconnectedconnector • Shortedbusconditionssuchascabledamageshortingthetwistedpairtogether • Idlebusconditionsthatoccurwhennodriveronthebusisactivelydriving In any of these cases, the differential receiver outputs a failsafe logic-high state so that the output of the receiver isnotindeterminate. Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com Typical Application (continued) Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input V is more positive than 200 mV, and it must output a Low when ID V is more negative than –200 mV. The receiver parameters that determine the failsafe performance are V , ID IT+ V , and V (the separation between V and V ). As shown in the Electrical Characteristics: Receiver table, IT– hys IT+ IT– differential signals more negative than –200 mV cause a low receiver output, and differential signals more positivethan200mVcauseahighreceiveroutput. When the differential input signal is close to zero, it is still above the V threshold, and the receiver output is IT+ High. Only when the differential input is more than V below V does the receiver output transition to a Low hys IT+ state. Therefore, the noise immunity of the receiver inputs during bus fault conditions includes the receiver hysteresisvalue(V )aswellasthevalueofV . hys IT+ 10.2.2 DetailedDesignProcedure To protect bus nodes against high-energy transients, the implementation of external transient protection devices isnecessary. 5V 110000 nnFF 110000n nFF 101 k0Ωk VCC R1 R RxD MCU/ RE A TVS UART DE B DIR D TxD R2 101 k0Ωk GND Figure20. TransientProtectionAgainstESD,EFT,andSurgeTransients Figure 20 suggests a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT (IEC 61000-4-4), and 1-kV surge(IEC61000-4-5)transients.Table3showstheassociatedbillofmaterials. Table3.BillofMaterials DEVICE FUNCTION ORDERNUMBER MANUFACTURER 5-V,10-MbpsRS-485 XCVR SN65HVD485E TI transceiver 10-Ω,pulse-proofthick-film R1,R2 CRCW0603010RJNEAHP Vishay resistor Bidirectional400-W TVS CDSOT23-SM712 Bourns transientsuppressor 10.2.2.1 PowerUsageinanRS-485Transceiver Power consumption is a concern in many applications. Power supply current is delivered to the bus load and to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists ofallofthereceivingnodesplustheterminationresistorsateachendofthebus. The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standarddefinesaunitloadasallowingupto1mA.Withupto32unitloadsallowedonthebus,thetotalcurrent supplied to all receivers can be as high as 32 mA. The SN65HVD485E device is rated as a ½ unit load device, soupto64canbeconnectedononebus. 16 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at each end, this sums to 25-mA differential output current whenever the bus is active. Typically, the SN65HVD485E device can drive more than 25 mA to a 60-Ω load, which results in a differential output voltage higherthantheminimumrequiredbythestandard(seeFigure2). Supply current increases with signaling rate primarily because of the totem pole outputs of the driver. When these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting, which creates a short spike in the supply current. As the frequency of state changes increases, more powerisused. 10.2.3 ApplicationCurve Figure21.SN65HVD485ESingle-EndedInput(Top),DifferentialOutput(Middle),andSingle-EndedOutput (Bottom)at10MHz Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com 11 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, each supply must be decoupled with a 100-nF ceramic capacitor located as close as possible to the supply pins. This helps to reduce supply voltage ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and inductanceofthePCBpowerplanes. 12 Layout 12.1 Layout Guidelines Robust and reliable bus-node design often requires the use of external transient-protection devices to protect against EFT and surge transients that may occur in industrial environments. Because these transients have a wide frequency bandwidth (from approximately 3 MHz to 3 GHz), high-frequency layout techniques must be appliedduringPCBdesign. 1. Placetheprotectioncircuitryclosetothebusconnectortopreventnoisetransientsfromenteringtheboard. 2. Use V and ground planes to provide low-inductance power distribution. High-frequency currents tend to CC followthepathofleastinductanceandnotthepathofleastresistance. 3. Design the protection components into the direction of the signal path. Do not force the transient currents to divertfromthesignalpathtoreachtheprotectiondevice. 4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the V pins of transceiver, UART, or CC controllerICsontheboard. 5. Use at least two vias for V and ground connections of bypass capacitors and protection devices to CC minimizeeffectiveviainductance. 6. Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transientevents. 7. Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping currentintothetransceiverandpreventitfromlatchingup. 8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs), which reduces the transients to a few hundred volts of clamping voltage and transient blockingunits(TBUs)thatlimittransientcurrenttolessthan1mA. 12.2 Layout Example 5 Viatoground R C 4 ViatoVCC 6 R 1 R MCU P 7 R M R 5 J TVS 6 R SN65HVD485E 5 Figure22. LayoutExample 18 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

SN65HVD485E www.ti.com SLLS612E–JUNE2004–REVISEDDECEMBER2015 13 Device and Documentation Support 13.1 Device Support 13.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 13.1.2 DeviceNomenclature 13.1.2.1 ThermalCharacteristicsofICPackages θ (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient JA temperaturedividedbytheoperatingpower θ isNOTaconstantandisastrongfunctionof JA • thePCBdesign(50%variation) • altitude(20%variation) • devicepower(5%variation) θ can be used to compare the thermal performance of packages if the specific test conditions are defined and JA used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. θ is often misused when it is used to calculate junction JA temperaturesforotherinstallations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm longwith2-ozthickcopper.A4%to50%differencein θ canbemeasuredbetweenthesetwotestcards JA θ (Junction-to-CaseThermalResistance)isdefinedasdifferenceinjunctiontemperaturetocasedividedbythe JC operating power. It is measured by putting the mounted package up against a copper block cold plate to force heattoflowfromdie,throughthemoldcompoundintothecopperblock. θ is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to JC predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non- standard system and junction temperatures are backed out. It can be used with θ in 1-dimensional thermal JB simulationofapackagesystem. θ (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the JB PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure.θ isonlydefinedforthehigh-ktestcard. JB θ provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal JB resistance(especiallyforBGA'swiththermalballs)andcanbeusedforsimple1-dimensionalnetworkanalysisof packagesystem(seeFigure23). Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SN65HVD485E

SN65HVD485E SLLS612E–JUNE2004–REVISEDDECEMBER2015 www.ti.com Device Support (continued) Ambient Node q Calculated CA Surface Node q Calculated/Measured JC Junction q Calculated/Measured JB PC Board Figure23. ThermalResistance 13.2 Documentation Support 13.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: SZZA003,PackageThermalCharacterizationMethodologies 13.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 13.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN65HVD485E

PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) HPA01057EDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VP485 & no Sb/Br) SN65HVD485ED ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VP485 & no Sb/Br) SN65HVD485EDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VP485 & no Sb/Br) SN65HVD485EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (NWH, NWJ) & no Sb/Br) SN65HVD485EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (NWH, NWJ) & no Sb/Br) SN65HVD485EDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VP485 & no Sb/Br) SN65HVD485EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VP485 & no Sb/Br) SN65HVD485EP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 65HVD485 & no Sb/Br) SN65HVD485EPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 65HVD485 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Mar-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65HVD485EDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65HVD485EDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65HVD485EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Mar-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65HVD485EDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 SN65HVD485EDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 SN65HVD485EDR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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