(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 (cid:1) Operate With 3-V to 5.5-V V Supply D, DB, DW, OR PW PACKAGE CC (cid:1) (TOP VIEW) Operate Up To 1 Mbit/s (cid:1) Low Supply Current...300 µA Typ C1+ 1 16 VCC (cid:1) External Capacitors...4 × 0.1 µF V+ 2 15 GND (cid:1) Accept 5-V Logic Input With 3.3-V Supply C1− 3 14 DOUT1 (cid:1) C2+ 4 13 RIN1 Latch-Up Performance Exceeds 100 mA Per C2− 5 12 ROUT1 JESD 78, Class II (cid:1) V− 6 11 DIN1 RS-232 Bus-Pin ESD Protection Exceeds DOUT2 7 10 DIN2 ±15 kV Using Human-Body Model (HBM) RIN2 8 9 ROUT2 (cid:1) Applications − Battery-Powered Systems, PDAs, Notebooks, Laptops, Palmtop PCs, and Hand-Held Equipment description/ordering information The SN65C3232 and SN75C3232 consist of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND). These devices provide the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The devices operate at data signaling rates up to 1 Mbit/s and a driver output slew rate of 24 V/µs to 150 V/µs. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube of 40 SN65C3232D SSOOIICC −− DD 6655CC33223322 Reel of 2500 SN65C3232DR Tube of 40 SN65C3232DW SSOOIICC −− DDWW 6655CC33223322 −−4400°CC ttoo 8855°CC Reel of 2000 SN65C3232DWR SSOP − DB Reel of 2000 SN65C3232DBR 65C3232 Tube of 90 SN65C3232PW TTSSSSOOPP −− PPWW CCBB33223322 Reel of 2000 SN65C3232PWR Tube of 40 SN75C3232D SSOOIICC −− DD 7755CC33223322 Reel of 2500 SN75C3232DR Tube of 40 SN75C3232DW SSOOIICC −− DDWW 7755CC33223322 00°CC ttoo 7700°CC Reel of 2000 SN75C3232DWR SSOP − DB Reel of 2000 SN75C3232DBR 75C3232 Tube of 90 SN75C3232PW TTSSSSOOPP −− PPWW CCAA33223322 Reel of 2000 SN75C3232PWR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:23)(cid:22)(cid:13)(cid:25)(cid:16)(cid:5)(cid:12)(cid:18)(cid:13)(cid:2) (cid:25)(cid:20)(cid:12)(cid:20) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’(cid:14) Copyright  2004, Texas Instruments Incorporated (cid:23)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #,’ #’(cid:31)!$ (cid:30)(cid:29) (cid:12)’-"$ (cid:18)(cid:28)$#(cid:31)&!’(cid:28)#$ $#"(cid:28)+"(cid:31)+ ."(cid:31)(cid:31)"(cid:28)#/(cid:14) (cid:23)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)0 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*/ (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)0 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$(cid:14) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 Function Tables EACH DRIVER INPUT OUTPUT DIN DOUT L H H L H = high level, L = low level EACH RECEIVER INPUT OUTPUT RIN ROUT L H H L Open H H = high level, L = low level, Open = input disconnected or connected driver off logic diagram (positive logic) 11 14 DIN1 DOUT1 10 7 DIN2 DOUT2 12 13 ROUT1 RIN1 9 8 ROUT2 RIN2 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V CC Positive output supply voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Negative output supply voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to −7 V Supply voltage difference, V+ − V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V Input voltage range, V: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V I Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 V to 25 V Output voltage range, V : Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −13.2 V to 13.2 V O Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V CC Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W JA DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to network GND. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4 and Figure 4) MIN NOM MAX UNIT VCC = 3.3 V 3 3.3 3.6 SSuuppppllyy vvoollttaaggee VV VCC = 5 V 4.5 5 5.5 VCC = 3.3 V 2 VVIIHH DDrriivveerr hhiigghh--lleevveell iinnppuutt vvoollttaaggee DDIINN VV VCC = 5 V 2.4 VIL Driver low-level input voltage DIN 0.8 V Driver input voltage DIN 0 5.5 VVII VV Receiver input voltage −25 25 SN65C3232 −40 85 TTAA OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree °°CC SN75C3232 0 70 NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT ICC Supply current No load, VCC = 3.3 V or 5 V 0.3 1 mA ‡All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.4 V VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC −5 −5.4 V IIH High-level input current VI = VCC ±0.01 ±1 µA IIL Low-level input current VI at GND ±0.01 ±1 µA IIOOSS‡‡ SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt VVCCCC == 35..56 VV,, VVOO == 00 VV ±±3355 ±±6900 mmAA ro Output resistance VCC, V+, and V− = 0 V, VO = ±2 V 300 10M (cid:1) †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. ‡Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output should be shorted at a time. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT CL = 1000 pF 250 MMaaxxiimmuumm ddaattaa rraattee RRLL == 33 kkΩΩ, CL = 250 pF, VCC = 3 V to 4.5 V 1000 kkbbiitt//ss ((sseeee FFiigguurree 11)) OOnnee DDOOUUTT sswwiittcchhiinngg CL = 1000 pF, VCC = 4.5 V to 5.5 V 1000 tsk(p) Pulse skew§ CpFL = 150 pF to 2500 RSeLe = F 3ig kuΩre t o2 7 kΩ, 300 ns Slew rate, SR(tr) transition region RVCL C= =3 k3Ω.3 tVo 7 kΩ, CL = 150 pF to 1000 pF 18 150 V/µs (see Figure 1) †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. §Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage IOH = −1 mA VCC − 0.6 V VCC − 0.1 V V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VCC = 3.3 V 1.5 2.4 VVIITT++ PPoossiittiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VV VCC = 5 V 1.8 2.4 VCC = 3.3 V 0.6 1.2 VVIITT−− NNeeggaattiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VV VCC = 5 V 0.8 1.5 Vhys Input hysteresis (VIT+ − VIT−) 0.3 V ri Input resistance VI = ±3 V to ±25 V 3 5 7 k(cid:1) †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 3) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH Propagation delay time, low- to high-level output 300 ns CCLL== 115500 ppFF tPHL Propagation delay time, high- to low-level output 300 ns tsk(p) Pulse skew‡ 300 ns †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. ‡Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. PARAMETER MEASUREMENT INFORMATION 3 V Input 1.5 V 1.5 V RS-232 0 V Output Generator (see Note B) 50 Ω CL tTHL tTLH RL (see Note A) VOH 3 V 3 V Output −3 V −3 V VOL TEST CIRCUIT SR(tr)(cid:1) 6V VOLTAGE WAVEFORMS t ort THL TLH NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤10 ns, tf ≤ 10 ns. Figure 1. Driver Slew Rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION 3 V RS-232 Input 1.5 V 1.5 V Generator Output 0 V (see Note B) 50 Ω CL tPHL tPLH RL (see Note A) VOH Output 50% 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 2. Driver Pulse Skew 3 V Input 1.5 V 1.5 V Output −3 V Generator (see Note B) 50 Ω CL tPHL tPLH (see Note A) VOH Output 50% 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 3. Receiver Propagation Delay Times 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:6)(cid:7) (cid:6)(cid:10)(cid:11) (cid:12)(cid:13) (cid:4)(cid:14)(cid:4)(cid:10)(cid:11) (cid:15)(cid:16)(cid:17)(cid:12)(cid:18)(cid:5)(cid:19)(cid:20)(cid:2)(cid:2)(cid:21)(cid:17) (cid:22)(cid:1)(cid:10)(cid:7)(cid:6)(cid:7) (cid:5)(cid:13)(cid:15)(cid:23)(cid:20)(cid:12)(cid:18)(cid:24)(cid:17)(cid:21) (cid:17)(cid:18)(cid:2)(cid:21) (cid:25)(cid:22)(cid:18)(cid:11)(cid:21)(cid:22)(cid:26)(cid:22)(cid:21)(cid:5)(cid:21)(cid:18)(cid:11)(cid:21)(cid:22) SLLS540B − JULY 2002 − REVISED NOVEMBER 2004 APPLICATION INFORMATION 1 16 C1+ VCC + CBYPASS = 0.1 µF − + 2 15 C1 †+ V+ GND − C3 − 14 3 DOUT1 C1− 13 4 RIN1 C2+ + C2 5 kΩ − 5 C2− 12 ROUT1 6 − V− 11 C4 DIN1 + 7 10 DOUT2 DIN2 8 9 RIN2 ROUT2 5 kΩ †C3 can be connected to VCC or GND. VCC vs CAPACITOR VALUES VCC C1 C2, C3, C4 3.3 V ± 0.3 V 0.1 µF 0.1 µF 5 V ± 0.5 V 0.047 µF 0.33 µF 3 V to 5.5 V 0.1 µF 0.47 µF Figure 4. Typical Operating Circuit and Capacitor Values POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65C3232D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 & no Sb/Br) SN65C3232DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 & no Sb/Br) SN65C3232DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 & no Sb/Br) SN65C3232DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 & no Sb/Br) SN65C3232DWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 & no Sb/Br) SN65C3232PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CB3232 & no Sb/Br) SN65C3232PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CB3232 & no Sb/Br) SN75C3232D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 & no Sb/Br) SN75C3232DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 CA3232 & no Sb/Br) SN75C3232DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 & no Sb/Br) SN75C3232DRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 & no Sb/Br) SN75C3232DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 & no Sb/Br) SN75C3232DWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 & no Sb/Br) SN75C3232PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 CA3232 & no Sb/Br) SN75C3232PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 CA3232 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65C3232DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65C3232DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN65C3232PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN75C3232DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN75C3232DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN75C3232PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65C3232DR SOIC D 16 2500 333.2 345.9 28.6 SN65C3232DWR SOIC DW 16 2000 350.0 350.0 43.0 SN65C3232PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN75C3232DR SOIC D 16 2500 333.2 345.9 28.6 SN75C3232DWR SOIC DW 16 2000 350.0 350.0 43.0 SN75C3232PWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

None

None

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated