SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 (cid:0) Meet or Exceed the Requirements of SN65C1154...N PACKAGE TIA/EIA-232-F and ITU Recommendation SN75C1154...DW, N, OR NS PACKAGE (TOP VIEW) V.28 (cid:0) Very Low Power Consumption... V 1 20 V DD CC 5 mW Typ 1RA 2 19 1RY (cid:0) Wide Driver Supply Voltage... 1DY 3 18 1DA ±4.5 V to ±15 V 2RA 4 17 2RY (cid:0) Driver Output Slew Rate Limited to 2DY 5 16 2DA 30 V/µs Max 3RA 6 15 3RY (cid:0) 3DY 7 14 3DA Receiver Input Hysteresis...1000 mV Typ (cid:0) 4RA 8 13 4RY Push-Pull Receiver Outputs 4DY 9 12 4DA (cid:0) On-Chip Receiver 1-µs Noise Filter V 10 11 GND SS description/ordering information The SN65C1164 and SN75C1154 are low-power BiMOS devices containing four independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1154 and SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs and the receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need for external components. The SN65C1154 and SN75C1154 have been designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices usually are insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN65C1154 and SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING –40°C to 85°C PDIP (N) Tube of 20 SN65C1154N SN65C1154N PDIP (N) Tube of 20 SN75C1154N SN75C1154N Tube of 25 SN75C1154DW 00°°CC ttoo 7700°°CC SSOOIICC ((DDWW)) SSNN7755CC11115544 Reel of 2500 SN75C1154DWR SOP (NS) Reel of 2000 SN75C1154NSR SN75C1154 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 logic diagram (positive logic) Typical of Each Receiver 2, 4, 6, 8 19, 17, 15, 13 RA RY Typical of Each Driver 3, 5, 7, 9 18, 16, 14, 12 DY DA 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 schematics of inputs and outputs EQUIVALENT DRIVER INPUT EQUIVALENT DRIVER OUTPUT VDD VDD Input Internal DA 1.4-V Reference 160 Ω Output VSS GND 74 Ω DY 72 Ω VSS EQUIVALENT RECEIVER INPUT EQUIVALENT RECEIVER OUTPUT Input 3.4 kΩ VCC RA 1.5 kΩ ESD ESD Protection Protection Output RY 530 Ω GND GND Resistor values shown are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage: V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V DD V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V SS V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage range, V:Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V I SS DD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V Output voltage range, V :Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V – 6 V) to (V + 6 V) O SS DD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V + 0.3 V) CC Package thermal impedance, θ (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W JA N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage s are with respect to the network GND terminal. θ 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 4.5 12 15 V VSS Supply voltage –4.5 –12 –15 V VCC Supply voltage 4.5 5 6 V Driver VSS + 2 VDD VVII IInnppuutt vvoollttaaggee VV Receiver ±25 VIH High-level input voltage Driver 2 V VIL Low-level input voltage Driver 0.8 V IOH High-level output current Receiver –1 mA IOL High-level output current Receiver 3.2 mA SN65C1154 –40 85 TTAA OOpeerraattiinngg ffrreeee--aaiirr tteemmpeerraattuurree °°CC SN75C1154 0 70 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 DRIVER SECTION electrical characteristics over operating free-air temperature range, V = 12 V, V = –12 V, DD SS V = 5 V ±10% (unless otherwise noted) CC PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VIILL = 0.8 V,, RLL = 3 kΩ,, VDD = 5 V, VSS = –5 V 4 4.5 VV See Figure 1 VDD = 12 V, VSS = –12 V 10 10.8 VVOOLL Low-level output voltagge VIIHH = 2 V,, RLL = 3 kΩ,, VDD = 5 V, VSS = –5 V –4.4 –4 VV (see Note 4) See Figure 1 VDD = 12 V, VSS = –12 V –10.7 –10 IIH High-level input current VI = 5 V, See Figure 2 1 µA IIL Low-level input current VI = 0, See Figure 2 –1 µA Higgh-level short-circuit IIOOSS((HH)) output current‡ VVII == 00.88 VV, VVOO == 00 oorr VVSSSS, SSeeee FFiigguurree 11 –77.55 –1122 –1199.55 mmAA Low-level short-circuit IIOOSS((LL)) output current‡ VVII == 22 VV, VVOO == 00 oorr VVDDDD, SSeeee FFiigguurree 11 77.55 1122 1199.55 mmAA IIDDDD SSuuppppllyy ccuurrrreenntt ffrroomm VVDDDD NNAlool illnoopaauddt,,s at 2 V or 0.8 V VVDDDD == 152 V V,, VVSSSS == ––152 V V 111155 225500 µµAA IISSSS SSuuppppllyy ccuurrrreenntt ffrroomm VVSSSS NNAlool illnoopaauddt,,s at 2 V or 0.8 V VVDDDD == 152 V V,, VVSSSS == ––152 V V ––111155 ––225500 µµAA ro Output resistance VDD = VSS = VCC = 0, VO = –2 V to 2 V, See Note 5 300 400 Ω †All typical values are at TA = 25°C. ‡Not more than one output should be shorted at one time. NOTES: 4. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only. 5. Test conditions are those specified by TIA/EIA-232-F. switching characteristics, V = 12 V, V = –12 V, V = 5 V ±10%, T = 25°C (see Figure 3) DD SS CC A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output§ RL = 3 to 7 kΩ, CL = 15 pF 1.2 3 µs tPHL Propagation delay time, high- to low-level output§ RL = 3 to 7 kΩ, CL = 15 pF 2.5 3.5 µs tTLH Transition time, low- to high-level output¶ RL = 3 to 7 kΩ, CL = 15 pF 0.53 2 3.2 µs tTHL Transition time, high- to low-level output¶ RL = 3 to 7 kΩ, CL = 15 pF 0.53 2 3.2 µs tTLH Transition time, low- to high-level output# RL = 3 to 7 kΩ, CL = 2500 pF 1 2 µs tTHL Transition time, high- to low-level output# RL = 3 to 7 kΩ, CL = 2500 pF 1 2 µs SR Output slew rate RL = 3 to 7 kΩ, CL = 15 pF 4 10 30 V/µs §tPHL and tPLH include the additional time due to on-chip slew rate control and are measured at the 50% points. ¶Measured between 10% and 90% points of output waveform #Measured between 3 V and –3 V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 RECEIVER SECTION electrical characteristics over operating free-air temperature range, V = 12 V, V = –12 V, V DD SS CC = 5 V ± 10% (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Positive-ggoingg input VVIITT+ SSeeee FFiigguurree 55 11.77 22.11 22.5555 VV threshold voltage Neggative-ggoingg input VVIITT– SSeeee FFiigguurree 55 00.6655 11 11.2255 VV threshold voltage Input hysteresis voltage Vhys (VIT+ – VIT–) 600 1000 mV VI = 0.75 V, IOH = –20 µA, See Figure 5 and Note 6 3.5 VCC = 4.5 V 2.8 4.4 VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VVI = 00.7755 VV, IIOH = –11 mAA, VCC = 5 V 3.8 4.9 VV SSeeee FFiigguurree 55 VCC = 5.5 V 4.3 5.4 VOL Low-level output voltage VI = 3 V, IOL = 3.2 mA, See Figure 5 0.17 0.4 V VI = 25 V 3.6 4.6 8.3 IIIIHH HHiigghh-lleevveell iinnppuutt ccuurrrreenntt mmAA VI = 3 V 0.43 0.55 1 VI = –25 V –3.6 –5 –8.3 IIIILL LLooww-lleevveell iinnppuutt ccuurrrreenntt mmAA VI = –3 V –0.43 –0.55 –1 Short-circuit output IIOOSS((HH)) VVII == 00.7755 VV, VVOO == 00, SSeeee FFiigguurree 44 –88 –1155 mmAA at high level Short-circuit output IIOOSS((LL)) VVII == VVCCCC, VVOO == VVCCCC, SSeeee FFiigguurree 44 1133 2255 mmAA at low level No load, VDD = 5 V, VSS = –5 V 400 600 IICCCC SSuuppppllyy ccuurrrreenntt ffrroomm VVCCCC All inputs at 0 or 5 V VDD = 12 V, VSS = –12 V 400 600 µµAA †All typical values are at TA = 25°C. NOTE 6: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs will remain in the high state. switching characteristics, V = 12 V, V = –12 V, V = 5 V ± 10%, T = 25°C DD SS CC A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation delay time, tPLH low- to high-level output CL = 50 pF, RL = 5 kΩ, See Figure 6 3 4 µs Propagation delay time, tPHL high- to low-level output CL = 50 pF, RL = 5 kΩ, See Figure 6 3 4 µs tTLH Transition time, low- to high-level output CL = 50 pF, RL = 5 kΩ, See Figure 6 300 450 ns tTHL Transition time, high- to low-level output CL = 50 pF, RL = 5 kΩ, See Figure 6 100 300 ns Duration of longest pulse tw(N) rejected as noise‡ CL = 50 pF, RL = 5 kΩ 1 4 µs ‡The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or negative-going pulse greater than the maximum of tw(N). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION IOSL VDD VDD or GND VDD VCC –IOSH IIH VCC VSS or GND VI VI –IIL VO RL = 3 kΩ VI VSS VSS Figure 1. Driver Test Circuit (VOH, VOL, IOSL, IOSH) Figure 2. Driver Test Circuit (IIL, IIH) VDD 3 V Input VCC Input 1.5 1.5 0 V Pulse Generator tPHL tPLH (see Note A) VOH RL CL 90% 90% (see Note B) 50% 50% Output 10% 10% VOL VSS tTHL tTLH TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms VDD –IOS(H) VDD VCC VCC VI IOS(L) VIT, VI VCC VOH –IOH VOL IOL VSS VSS Figure 4. Receiver Test Circuit (I , I ) Figure 5. Receiver Test Circuit (V , V , V ) OSH OSL IT OL OH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VDD 4 V Input VCC Input 50% 50% 0 V Pulse Generator tPHL tPLH (see Note A) VOH RL CL 90% 90% (see Note B) 50% 50% Output 10% 10% VOL VSS tTHL tTLH TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65C1154N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN65C1154N (RoHS) SN65C1154NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN65C1154N (RoHS) SN75C1154DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1154 & no Sb/Br) SN75C1154DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1154 & no Sb/Br) SN75C1154N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN75C1154N (RoHS) SN75C1154NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN75C1154N (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN75C1154DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN75C1154DWR SOIC DW 20 2000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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