SN10501 SN10502 (cid:7)(cid:6)(cid:12)(cid:1)(cid:4) (cid:7)(cid:1)(cid:5) (cid:7)(cid:8)(cid:10)(cid:1)(cid:5) (cid:7)(cid:8)(cid:9)(cid:1)(cid:5) (cid:7)(cid:1)(cid:2)(cid:3) (cid:11)(cid:13)(cid:11)(cid:1)(cid:2)(cid:3) SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 HIGH-SPEED RAIL-TO-RAIL OUTPUT VIDEO AMPLIFIERS FEATURES 1 • HighSpeed VIDEODRIVECIRCUIT 2 – 100MHzBandwidth(–3dB,G=2) VS+ – 900V/sSlewRate • ExcellentVideoPerformance + – 50MHzBandwidth(0.1dB,G=2) 10 m F 0.1 m F Video In 5 – 0.007%DifferentialGain 3 SN10501 – 0.007DifferentialPhase + 1 75 W VO 4 • Rail-to-RailOutputSwing 75 W − 2 – VO=–4.5/4.5(RL=150Ω) 75 W • HighOutputDrive,IO=100mA(typ) VS− + 10 m F 0.1 m F • UltralowDistortion – HD2=–78dBc(f=5MHz,RL=150Ω) 1.43 kW 1.43 kW – HD3=–85dBc(f=5MHz,R =150Ω) L • WideRangeofPowerSupplies 6.3 VO = 0.1 VPP – V =3Vto15V 6.2 −0.1 dB at 49 MHz S 6.1 APPLICATIONS dB 6.0 − • VideoLineDriver ain 5.9 VO = 2 VPP • Imaging al G 5.8 −0.1 dB at 51 MHz n • DVD/CDROM Sig 5.7 5.6 • ActiveFiltering Gain = 2 5.5 RL = 150 W to GND • GeneralPurposeSignalChainConditioning 5.4 VRSF == ±15.4 3V kW 5.3 DESCRIPTION 100 k 1 M 10 M 100 M 1 G f − Frequency − Hz The SN1050x family is a set of rail-to-rail output single, dual, and triple low-voltage, high-output swing, low-distortion high-speed amplifiers ideal for driving data converters, video switching, or low distortion applications. This family of voltage-feedback amplifiers can operate from a single 15-V power supply down to a single 3-V power supply while consuming only 14 mA of quiescent current per channel. In addition, the family offers excellent ac performance with 100-MHz bandwidth, 900-V/m s slew rate and harmonic distortion (THD) at –78 dBc at 5MHz. DEVICE DESCRIPTION SN10501 Single SN10502 Dual SN10503 Triple 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. owerPADisatrademarkofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ABSOLUTE MAXIMUM RATINGS operatingfree-airtemperaturerangeunlessotherwise (1) UNIT Supplyvoltage,V 16.5V S Inputvoltage,V ±V I S Outputcurrent,I 150mA O Differentialinputvoltage,V 4V ID ContinuouspowerdissipationSeeDissipationRatingTable Maximumjunctiontemperature,T 150°C J Maximumjunctiontemperature,continuousoperation,longtermreliability,T (2) 125°C J Storagetemperaturerange,T –65°Cto150°C stg Leadtemperature1,6mm(1/16inch)fromcasefor10seconds 300°C (1) Theabsolutemaximumratingsunderanyconditionislimitedbytheconstraintsofthesiliconprocess.Stressesabovetheseratingsmay causepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmaydegradedevicereliability.Theseare stressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthosespecifiedisnotimplied. (2) Themaximumjunctiontemperatureforcontinuousoperationislimitedbypackageconstraints.Operationabovethistemperaturemay resultinreducedreliabilityand/orlifetimeofthedevice. PACKAGE DISSIPATION RATINGS POWERRATING(2) PACKAGE q (°C/W)(1) q (°C/W) JC JA T ≤25°C T =85°C A A DBV(5) 55 255.4 391mW 156mW D(8) 38.3 97.5 1.02W 410mW D(14) 26.9 66.6 1.5W 600mW DGK(8) 54.2 260 385mW 154mW DGN(8)(3) 4.7 58.4 1.71W 685mW PWP(14)(3) 2.07 37.5 2.67W 1.07W (1) ThisdatawastakenusingtheJEDECstandardHigh-KtestPCB. (2) Powerratingisdeterminedwithajunctiontemperatureof125°C.Thisisthepointwheredistortion startstosubstantiallyincrease.ThermalmanagementofthefinalPCBshouldstrivetokeepthe junctiontemperatureatorbelow125°Cforbestperformanceandlongtermreliability. (3) TheSN10501,SN10502,andSN10503mayincorporateaPowerPAD™ontheundersideofthechip. Thisactsasaheatsinkandmustbeconnectedtoathermallydissipatingplaneforproperpower dissipation.Failuretodosomayresultinexceedingthemaximumjunctiontemperaturewhichcould permanentlydamagethedevice.SeeTITechnicalBriefSLMA002formoreinformationaboututilizing thePowerPAD™thermallyenhancedpackage. 2 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Dualsupply 1.35 8 Supplyvoltage,(V andV ) V S+ S- Singlesupply 2.7 16 Inputcommon-modevoltagerange V +1.1 V -1.1 V S- S+ PACKAGEORDERINGINFORMATION PACKAGEDDEVICES PACKAGETYPE TRANSPORTMEDIA,QUANTITY SINGLE DUAL TRIPLE SN10501DBVT — — SOT-23-5 TapeandReel,250 SN10501DBVR — — SOT-23-5 TapeandReel,3000 SN10501DGK SN10502DGK — MSOP-8 Rails,75 SN10501DGKR SN10502DGKR — MSOP-8 TapeandReel,2500 SN10501DGN SN10502DGN — MSOP-8-PP Rails,75 SN10501DGNR SN10502DGNR — MSOP-8-PP TapeandReel,2500 SN10501D SN10502D SN10503D SOIC Rails,75 SN10501DR SN10502DR SN10503DR SOIC TapeandReel,2500 — — SN10503PWP TSSOP-14-PP Rails,75 — — SN10503PWPR TSSOP-14-PP TapeandReel,2000 PIN ASSIGNMENTS PACKAGE DEVICES SN10501 SN10501 SN10502 DBV PACKAGE D, DGK, DGN PACKAGE D, DGK, DGN PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) VOUT 1 5 VS+ NC 1 8 NC 1OUT 1 8 VS+ VS− 2 IINN+− 23 76 VVSO+UT 11IINN+− 23 76 22OINU−T IN+ 3 4 IN− VS− 4 5 NC VS− 4 5 2IN+ NC − No internal connection SN10503 D, PWP PACKAGE (TOP VIEW) NC 1 14 2OUT NC 2 13 2IN− NC 3 12 2IN+ VS+ 4 11 VS− 1IN+ 5 10 3IN+ 1IN− 6 9 3IN− 1OUT 7 8 3OUT NC − No internal connection Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS V =5V,R =150Ω,andG=2unlessotherwisenoted S L TYP OVERTEMPERATURE PARAMETER TESTCONDITIONS 0°Cto –40°Cto 25°C 25°C UNITS MIN/MAX 70°C 85°C ACPERFORMANCE G=1,V =100mV 170 MHz Typ O PP G=2,V =100mV , O PP 100 MHz Typ Smallsignalbandwidth R =1kΩ f G=10,V =100mV , O PP 12 MHz Typ R =1kΩ f G=2,V =100mV , 0.1dBflatbandwidth O PP 50 MHz Typ R =1.43kΩ f Gainbandwidthproduct G>10,f=1MHz,R =1kΩ 120 MHz Typ f Full-powerbandwidth((1)) G=2,VO=±2.5VPP 57 MHz Typ Slewrate G=2,V =±2.5V 900 V/m s Min O PP Settlingtimeto0.1% 25 ns Typ G=-2,V =±2V O PP Settlingtimeto0.01% 52 ns Typ Harmonicdistortion Secondharmonicdistortion G=2,V =2V ,f=5MHz, –78 dBc Typ O PP Thirdharmonicdistortion RL=150Ω –85 dBc Typ Differentialgain(NTSC,PAL) 0.007 % Typ G=2,R=150Ω Differentialphase(NTSC,PAL) 0.007 ° Typ Inputvoltagenoise 13 nV/√Hz Typ f=1MHz Inputcurrentnoise 0.8 pA/√Hz Typ Crosstalk(dualandtripleonly) f=5MHzCh-to-Ch –90 dB Typ DCPERFORMANCE Open-loopvoltagegain(A ) V =±2V 100 80 75 75 dB Min OL O Inputoffsetvoltage 12 25 30 30 mV Max Inputbiascurrent V =0V 0.9 3 5 5 m A Max CM Inputoffsetcurrent 100 500 700 700 nA Max INPUTCHARACTERISTICS Common-modeinputrange –4/4 –3.9/3.9 V Min Common-moderejectionratio V =2V 94 70 65 65 dB Min CM Inputresistance 33 MΩ Typ Inputcapacitance Common-mode/differential 1/0.5 pF Max OUTPUTCHARACTERISTICS R =150Ω –4.5/4.5 V Typ L Outputvoltageswing R =499Ω –4.7/4.7 –4.5/4.5 –4.4/4.4 -4.4/4.4 V Min L Outputcurrent(sourcing) 100 92 88 88 mA Min R =10Ω L Outputcurrent(sinking) -100 -92 -88 -88 mA Min Outputimpedance f=1MHz 0.09 Ω Typ POWERSUPPLY Specifiedoperatingvoltage ±5 ±8 ±8 ±8 V Max Maximumquiescentcurrent Perchannel 14 18 20 22 mA Max Powersupplyrejection(±PSRR) 75 62 60 60 dB Min (1) Full-powerbandwidth=SR/2p Vpp 4 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 ELECTRICAL CHARACTERISTICS V =5V,R =150Ω,andG=2unlessotherwisenoted S L TYP OVERTEMPERATURE PARAMETER TESTCONDITIONS 0°Cto -40°Cto 25°C 25°C UNITS MIN/MAX 70C 85C ACPERFORMANCE G=1,V =100mV 170 MHz Typ O PP Smallsignalbandwidth G=2,V =100mV ,R =1.5kΩ 100 MHz Typ O PP f G=10,V =100mV ,R =1.5kΩ 12 MHz Typ O PP f 0.1dBflatbandwidth G=2,V =100mV ,R =1.24kΩ 50 MHz Typ O PP f Gainbandwidthproduct G>10,f=1MHz,R =1.5kΩ 120 MHz Typ f Full-powerbandwidth((1)) 60 MHz Typ G=2,V =4Vstep Slewrate O 750 V/m s Min Settlingtimeto0.1% 27 ns Typ G=-2,V =2V O Settlingtimeto0.01% 48 ns Typ Harmonicdistortion Secondharmonicdistortion G=2,V =2V ,f=5MHz, –82 dBc Typ O PP Thirdharmonicdistortion RL=150Ω –88 dBc Typ Differentialgain(NTSC,PAL) 0.014 % Typ G=2,R=150Ω Differentialphase(NTSC,PAL) 0.011 ° Typ Inputvoltagenoise 13 nV/√Hz Typ f=1MHz Inputcurrentnoise 0.8 pA/√Hz Typ Crosstalk(dualandtripleonly) f=5MHzCh-to-Ch –90 dB Typ DCPERFORMANCE Open-loopvoltagegain(A ) V =1.5Vto3.5V 100 80 75 75 dB Min OL O Inputoffsetvoltage 12 25 30 30 mV Max Inputbiascurrent V =2.5V 0.9 3 5 5 m A Max CM Inputoffsetcurrent 100 500 700 700 nA Max INPUTCHARACTERISTICS Common-modeinputrange 1/4 1.1/3.9 V Min Common-moderejectionratio V =1.5Vto3.5V 96 70 65 65 dB Min CM Inputresistance 33 MΩ Typ Inputcapacitance Common-mode/differential 1/0.5 pF Max OUTPUTCHARACTERISTICS R =150Ω 0.5/4.5 V Typ L Outputvoltageswing R =499Ω 0.2/4.8 0.3/4.7 0.4/4.6 0.4/4.6 V Min L Outputcurrent(sourcing) 95 85 80 80 mA Min R =10Ω L Outputcurrent(sinking) –95 -85 –80 –80 mA Min Outputimpedance f=1MHz 0.09 Ω Typ POWERSUPPLY Specifiedoperatingvoltage 5 16 16 16 V Max Maximumquiescentcurrent Perchannel 12 15 17 19 mA Max Powersupplyrejection(±PSRR) 70 62 60 60 dB Min (1) Full-powerbandwidth=SR/2p Vpp Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Frequencyresponse 1–8 Smallsignalfrequencyresponse 9,10 Largesignalfrequencyresponse 11 Slewrate vsOutputvoltagestep 12,13 Harmonicdistortion vsFrequency 14,15 Voltageandcurrentnoise vsFrequency 16 Differentialgain vsNumberofloads 17,18 Differentialphase vsNumberofloads 19,20 Quiescentcurrent vsSupplyvoltage 21 Outputvoltage vsLoadresistance 22 Open-loopgainandphase vsFrequency 23 Rejectionratio vsFrequency 24 Rejectionratio vsCasetemperature 25 Common-moderejectionratio vsInputcommon-moderange 26,27 Outputimpedance vsFrequency 28,29 Crosstalk vsFrequency 30 Inputbiasandoffsetcurrent vsCasetemperature 31,32 FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 8 6.3 8 VO = 2 VPP VO = 0.1 VPP VO = 2 VPP 7 −3 dB at 99 MHz 6.2 −0.1 dB at 49 MHz 7 −3 dB at 99 MHz 6 6.1 6 Signal Gain − dB 2345 V−3O d=B 0 a.1t 9V9P PMHz Signal Gain − dB 5556....7890 V−0O. 1= d2B V aPtP 51 MHz Signal Gain − dB 2345 V−3O d=B 0 a.1t 9V9P PMHz 1 5.6 1 Gain = 2 Gain = 2 Gain = 2 0 RL = 150 W to GND 5.5 RL = 150 W to GND 0 RL = 150 W to GND −1 VRSF == ±15.4 3V kW 5.4 VRSF == ±15.4 3V kW −1 VRSF == ±3051 V W −2 5.3 −2 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure1. Figure2. Figure3. FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 6.3 8 6.3 VO = 2 VPP 6.2 V−0O. 1= d2B V aPtP 14 MHz 7 −3 dB at 99 MHz 6.2 VO = 2 VPP −0.1 dB at 58 MHz 6.1 6 6.1 B Signal Gain − dB 5556....7890 V−0O. 1= d0B.1 a Vt P1P4 MHz Signal Gain − dB 2345 V−3O d=B 0 a.1t 9V9P PMHz Signal Gain − d 5556....7890 V−0O. 1= d0B.1 a Vt P4P8 MHz 5.6 1 5.6 Gain = 2 Gain = 2 Gain = 2 5.5 RL = 150 W to GND 0 RL = 150 W to VS/2 5.5 RL = 150 W to VS/2 5.4 VRSF == ±3051 V W −1 VRSF == 51 .2V4 kW 5.4 VRSF == 51 .2V4 kW 5.3 −2 5.3 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure4. Figure5. Figure6. 6 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 8 6.3 8 VO = 2 VPP 7 −3 dB at 89 MHz 6.2 VO = 0.1 VPP 7 Gain = 2 6 6.1 −0.1 dB at 16 MHz 6 Signal Gain − dB 2345 V−3O d=B 0 a.1t 8V4P PMHz gnal Gain − dB 5556....7890 V−0O. 1= d2B V aPtP 16 MHz gnal Gain − dB 2345 RRVVOSLF ==== 1±1155 0k0 0WV WmVPP 1 Si 5.6 Si 1 Gain = 2 Gain = 2 0 RL = 150 W to VS/2 5.5 RL = 150 W to VS/2 0 −1 VRSF == 53 0V1W 5.4 VRSF == 350 V1 W −1 Gain = 1 −2 5.3 −2 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure7. Figure8. Figure9. SLEWRATE vs FREQUENCYRESPONSE FREQUENCYRESPONSE OUTPUTVOLTAGESTEP 8 8 1200 Gain = 2 Signal Gain − dB 01234567 GainRRVV =OSLF 2==== 45119 .05V90 k WmW VPP Signal Gain − dB 234567 GRRLFa i==n 1=15 k20W W VS =V S5 =V ±5 V msSR − Slew Rate − V/ 1046800000000 RRVSLF === 1±155 k0 WV W Rise Fall −1 Gain = 1 1 VVOS == ±25 V VPP 200 −2 0 0 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 0 1 2 3 4 5 6 7 8 f − Frequency − Hz f − Frequency − Hz VO − Output Voltage Step − V Figure10. Figure11. Figure12. SLEWRATE HARMONICDISTORTION HARMONICDISTORTION vs vs vs OUTPUTVOLTAGESTEP FREQUENCY FREQUENCY 800 0 0 Gain = 2 msSR − Slew Rate − V/ 234567000000000000 RRVSLF === 1515 Vk0W W Fall Rise monic Distortion − dBc −−−−−−−76543210000000 GRVVOSLa i==n= 1±=255 2V0 VP WP HD2 HD3 monic Distortion − dBc −−−−−−−76543210000000 GRVVOSLa i==n= 1=525 V2V0P WP Har −80 Har −80 HD2 100 −90 −90 HD3 0 −100 −100 0 0.5 1 1.5 2 2.5 3 3.5 4 0.1 1 10 100 0.1 1 10 100 VO − Output Voltage Step − V f − Frequency − MHz f − Frequency − MHz Figure13. Figure14. Figure15. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com VOLTAGEANDCURRENTNOISE DIFFERENTIALGAIN DIFFERENTIALPHASE vs vs vs FREQUENCY NUMBEROFLOADS NUMBEROFLOADS 100 10 0.20 0.4 Gain = 2 Hz Hz 0.18 R40f =IR 1E.5 − k NW TSC 0.35 GRfa =in 1=.5 2 kW nV/ pA/ % 00..1146 WIRoEr sRt aCmapse ±100 °− 0.3 4W0o IrRstE C −a sNeT S±1C00 IRE Ramp − Voltage Noise −Vn10 VInn 1 − Current Noise −In Differential Gain − 00000.....0001146802 VS = 5 V VS = ±5 V Differential Phase 00..0012..5512 VVSS == 5± 5V V 0.02 0.05 1 0.1 0 0 1 k 10 k 100 k 1 M 10 M 0 1 2 3 4 5 0 1 2 3 4 5 f − Frequency − Hz Number of Loads − 150 W Number of Loads − 150 W Figure16. Figure17. Figure18. DIFFERENTIALGAIN DIFFERENTIALPHASE QUIESCENTCURRENT vs vs vs NUMBEROFLOADS NUMBEROFLOADS SUPPLYVOLTAGE 0.20 0.4 22 Gain = 2 Differential Gain − % 00000000........0001111146802468 R4W0fo =IrRs 1tE .C5 − ak sPWeA L±V1S0 0= I5R EV RamVpS = ±5 V °Differential Phase − 000...000123...555123 GR4W0fao =iIrnRs 1tE= .C5 2− ak sPWVVeAS SL± =1= 0 5±0 5 VI RVE Ramp Quiescent Current − mA/Ch 111112024680468 TA = 85°C TA T=A 2 =5 °−C40°C 0.02 0.05 2 0 0 0 0 1 2 3 4 5 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 Number of Loads − 150 W Number of Loads − 150 W VS − Supply Voltage − ±V Figure19. Figure20. Figure21. OUTPUTVOLTAGE OPEN-LOOPGAINANDPHASE REJECTIONRADIO vs vs vs LOADRESISTANCE FREQUENCY FREQUENCY 5 110 220 100 4 100 VS = ±5 V, 5 V, 200 90 VS = ±5 V, 5 V, and 3.3 V − Output Voltage − VVO −−012321 TA = −40 to 85°C pen-Loop Gain − dB34567890000000 and 3.3 V 6811111000246800000°Phase − ejection Ratios − dB 345678000000 PSRR CMMR O20 40 R −3 10 20 20 −4 0 0 10 −5 −10 −20 0 10 100 1 k 10 k 100 1 k 10 k 100 k 1 M 10 M 100 M 1 G 0.1 1 10 100 RL − Load Resistance − W f − Frequency − Hz f − Frequency − MHz Figure22. Figure23. Figure24. 8 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 REJECTIONRATIO COMMON-MODEREJECTIONRATIO COMMON-MODEREJECTIONRATIO vs vs vs CASETEMPERATURE INPUTCOMMON-MODERANGE INPUTCOMMON-MODERANGE 100 B 100 B 100 90 VS = ±5 V, 5 V, and 3.3 VCMMR Ratio − d 8900 Ratio − d 8900 ejection Ratio − dB 678000 PSRR mon-Mode Rejection 3456700000 mon-Mode Rejection 3456700000 R m m 50 RR − Co 1200 VTAS == 2±55° CV RR − Co 1200 VTAS == 255 V°C 40 CM 0 CM 0 −40−30−20−10 0 102030405060708090 −6 −4 −2 0 2 4 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TC − Case Temperature − °C VICR − Input Common-Mode Voltage Range − V VICR − Input Common-Mode Voltage Range − V Figure25. Figure26. Figure27. OUTPUTIMPEDANCE OUTPUTIMPEDANCE CROSSTALK vs vs vs FREQUENCY FREQUENCY FREQUENCY 100 100 120 Gain = 2 Gain = 2 Crosstalk all Channels RL = 150 W to GND RL = 150 W to VS/2 W− VO = 2 VPP W− VO = 2 VPP 100 ce 10 VS = ±5 V ce 10 VS = 5 V n n peda peda − dB 80 − Output Im 1 RF = 301 W − Output Im 1 RF = 301 W Crosstalk 4600 VS = ±5 V, 5 V, and 3.3 V O 0.1 O 0.1 Gain = 1 Z Z 20 RL = 150 W VIN= −1 dB RF = 1.43 kW RF = 1.24 kW TA = 25°C 0.01 0.01 0 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure28. Figure29. Figure30. INPUTBIASANDOFFSETCURRENT INPUTBIASANDOFFSETCURRENT vs vs CASETEMPERATURE CASETEMPERATURE 0.84 10 0.9 5 VS = 5 V VS = ±5 V m− Input Bias Current −AIIB 00000.....077778.246828 IOS IIB+ IIB− −−−−052115050− Input Offset Current −nAIOS m− Input Bias Current −AIIB00000.....078888.824688 IOS IIB− IIB+ −−−−−0221155050 − Input Offset Current −nAIOS 0.7 −25 0.76 −30 −40−30−20−100 102030405060708090 −40−30−20−10 0 102030405060708090 Case Temperature − °C Case Temperature − °C Figure31. Figure32. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com APPLICATION INFORMATION decrease the loading effect of the feedback network HIGH-SPEED OPERATIONAL AMPLIFIERS on the output of the amplifier, but this enhancement comes at the expense of additional noise and The SN1050x operational amplifiers are a family of potentially lower bandwidth. Feedback-resistor values single, dual, and triple rail-to-rail output voltage between 1 kΩ and 2 kΩ are recommended for most feedback amplifiers. The SN1050x family combines situations. bothahighslewrateandarail-to-railoutputstage. WIDEBAND, INVERTING OPERATION Applications Section Contents • Wideband,NoninvertingOperation Since the SN1050x family are general-purpose, wideband voltage-feedback amplifiers, several • Wideband,InvertingGainOperation familiar operational-amplifier applications circuits are • VideoDriveCircuits available to the designer. Figure 34 shows a typical • SingleSupplyOperation inverting configuration where the input and output • Power Supply Decoupling Techniques and impedances and noise gain from Figure 33 are retained in an inverting circuit configuration. Inverting Recommendations operation is one of the more common requirements • ActiveFilteringWiththeSN1050x and offers several performance benefits. The • DrivingCapacitiveLoads inverting configuration shows improved slew rates • BoardLayout and distortion due to the pseudo-static voltage • ThermalAnalysis maintainedontheinvertinginput. • AdditionalReferenceMaterial 5 V • MechanicalPackageDrawings +VS + WIDEBAND, NONINVERTING OPERATION 100 pF 0.1 m F 6.8 m F The SN1050x is a family of unity gain stable rail-to-rail output voltage feedback operational + a1m5-pVlifpieorwsedressuipgpnleyd. to operate from a single 3-V to 0.1 Cm FT R64T9 W _ VO 499 W 50 W Source Figure 33 is the noninverting gain configuration of Rg Rf 2V/V used to demonstrate the typical performance curves. VI 1.3 kW 1.3 kW RM 0.1 m F 6.8 m F 5 V 52.3 W +VS 100 pF + + −5 V−VS 50 W Source 100 pF 0.1 m F 6.8 m F Figure34.Wideband,InvertingGain VI + Configuration 49.9 W _ VO 499 W In the inverting configuration, some key design Rf considerations must be noted. One is that the gain 1.3 kW Rg 1.3 kW resistor (Rg) becomes part of the signal channel input 0.1 m F 6.8 m F impedance. If input impedance matching is desired 100 pF + (beneficial when the signal is coupled through a cable, twisted pair, long PC-board trace, or other transmission-line conductors), R may be set equal to −VS g −5 V the required termination value and R adjusted to give f the desired gain. However, care must be taken when Figure33.Wideband,NoninvertingGain Configuration dealingwithlowinvertinggains,becausetheresulting feedback-resistor value can present a significant load to the amplifier output. For an inverting gain of 2, Voltage-feedback amplifiers, unlike current-feedback setting R to 49.9 Ω for input matching eliminates the designs, can use a wide range of resistors values to g need for R but requires a 100-Ω feedback resistor. set their gain with minimal impact on their stability M This has the advantage that the noise gain becomes and frequency response. Larger-valued resistors equal to 2 for a 50-Ω source impedance—the same 10 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 as the noninverting circuit in Figure 33. However, the Video Drive Circuits amplifier output now sees the 100-Ω feedback Most video-distribution systems are designed with resistor in parallel with the external load. To eliminate 75-Ω series resistors to drive a matched 75-Ω cable. this excessive loading, increase both R and R, g f In order to deliver a net gain of 1 to the 75-Ω values, as shown in Figure 34, and then provide the matched load, the amplifier is typically set up for a input-matching impedance with a third resistor (R ) to M voltage gain of 2, compensating for the 6-dB ground. The total input impedance becomes the attenuationofthevoltagedividerformed by the series parallelcombinationofR andR . g M and shunt 75-Ω resistors at either end of the cable. The last major consideration to discuss in inverting The circuit shown in Figure 36 meets this amplifier design is setting the bias-current requirement. The SN1050x gain flatness and cancellation resistor on the noninverting input. If the differential gain/phase performance provide resistance is set equal to the total dc resistance exceptionalresultsinvideodistributionapplications. looking out of the inverting terminal, the output dc error, due to the input bias currents, is reduced to the VS+ input-offset current multiplied by R in Figure 34. The f dc source impedance looking out of the inverting + terminal is 1.3 kΩ || (1.3 kΩ + 25.6 Ω) = 649 Ω. To 10 m F 0.1 m F reduce the additional high-frequency noise introduced Video In 5 by the resistor at the noninverting input, and 3 + 75 W power-supply feedback, R is bypassed with a 1 T 4 capacitortoground. 75 W − VO 2 SINGLE SUPPLY OPERATION 75 W The SN1050x family is designed to operate from a VS− + 10 m F 0.1 m F single 3-V to 15-V power supply. When operating from a single power supply, care must be taken to 1.43 kW 1.43 kW ensure that the input signal and amplifier are biased appropriately to allow for the maximum output voltage Figure36.CableDriveApplication swing. The circuits shown in Figure 35 demonstrate methods to configure an amplifier for single-supply Differential gain and phase measure the change in operation. overall small-signal gain and phase for the color subcarrier frequency (3.58 MHz in NTSC systems) vs +VS changes in the large-signal output level (which 50 W Source represents luminance information in a composite + video signal). The SN1050x, with the typical 150-Ω VI load of a single matched video cable, shows less RT 49.9 W _ VO than 0.007% / 0.007° differential gain/phase errors 499 W over the standard luminance range for a positive +VS Rf video(negativesync)signal. 2 R1.g3 kW 1.3 kW VS+ 0.1 m F 75 W + VO +VS 2 Rf Video In 5 10 m F 75 W 3 VS1.3 kW + 1 75 W 50 W Source 4 Rg _ − VO 75 W 2 VI 1.3 kW 75 W 52.3 W RT + VO 499 W 75 W 1.43 kW 1.43 kW 0.1 m F +VS +VS 2 2 VO VS− + 10 m F Figure35.DC-CoupledSingleSupplyOperation 75 W Figure37.VideoDistribution Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com Similar performance is observed for negative video 1.24 kW 1.24 kW signals. In practice, similar performance is achieved even with three video loads as shown in Figure 37 Output Range due to the linear high-frequency output impedance of 5 V = 2 V to 4.5 V the SN1050x. This circuit is suitable for driving video VO Range cables, provided that the length does not exceed a Input Range - 75 W = 0 V to 1.25V few feet. If longer cables are driven, the gain of the = 1 V to 2.25 V + SN1050x can be increased to compensate for cable 470 m F loss. 75 W RT Configuring the SN1050x for single-supply video applications is easily done, but attention must be given to input and output bias voltages to ensure Figure39.AC-CoupledOutputSingle-Supply proper system operation. Unlike some video VideoAmplifier amplifiers, the SN1050x input common-mode voltage range does not include the negative power supply, In some systems, the physical size and/or cost of a but rather it is about 1-V from each power supply. For 470-m F capacitor can be prohibitive. One way to split supply configurations, this is very beneficial. For circumvent this issue is to use two smaller capacitors single-supply systems, there are some design in a feedback configuration as shown in Figure 40. constraintsthatmustbeobserved. This is commonly known as SAG correction. This Figure 38 shows a single-supply video configuration circuit increases the gain of the amplifier up to 3 V/V illustrating the dc bias voltages acceptable for the at low frequencies to counteract the increased SN1050x. The lower end of the input common-mode impedance of the capacitor placed at the amplifier range is specified as 1 V. The upper end is limited to output. One issue that must be resolved is that the 4 V with the 5-V supply shown, but the output range gain at low frequencies is typically limited by the and gain of 2 limit the highest acceptable input power-supply voltage and the output swing of the voltage to 4.5 V / 2 = 2.25 V. The 4.5-V output is amplifier. Therefore, it is possible to saturate the what is typically expected with a 150-Ω load. It is amplifieratthese low frequencies if full analysis is not easily seen that the input and output voltage ranges done on this system which includes both input and are limiting factors in the total system. Both outputrequirements. specifications must be taken into account when 1.24 kW 1.24 kW 22 m F designingasystem. 1.24 kW 1.24 kW 5 V 1.24 kW VO Range Output Range 5 V = 2 V to 4.5 V Input Range - 75 W = 0 V to 1.25V VO Range = 1 V to 2.25 V + Input Range − 75 W = 1 V to 2.25 V 22 m F = 1 V to 2.25 V 75 W + RT Output Range = 2 V to 4.5 V 75 W RT Figure40.AC-CoupledSAGCorrectedOutput Single-SupplyVideoAmplifier Figure38.DC-CoupledSingle-SupplyVideo Amplifier Many times the output of the video encoder or DAC does not have the capability to output the 1-V to 2.25-V range, but rather a 0-V to 1.25-V range. In this In most systems, this may be acceptable because instance, the signal must be ac-coupled to the most receivers are ac-coupled and set the black level amplifier input as shown in Figure 41. Note that it to the desired system value, typically 0 V (0-IRE). does not matter what the voltage output of the DAC But, to ensure full compatibility with any system, it is is, but rather the voltage swing should be kept less often desirable to place an ac coupling capacitor on than1.25V . the output as shown in Figure 39. This removes the PP dc-bias voltage appearing at the amplifier output. To minimize field tilt, the size of this capacitor is typically 470 m F, although values as small as 220 m F have beenusedwithacceptableresults. 12 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 1.24 kW 1.24 kW 68 m F 1.24 kW 2.49 kW Output Range 5 V 5 V = 2 V to 4.5 V =D 0A VC tOou 2tVput 5 V 5 V =O u0.t5p uVt tRo a4n.5gVe =D 0A CV tOou 1tp.2u5tV 4.64 kW - 75 W =V O0 RVa tnog 1e.25V 10 kW − 75 W =V O0 RVa tnog 2eV + 470 m F + 470 m F 47 m F 75 W 10 m F 75 W 2.26 kW Input Range 10 kW Input = 2.5 V = 1 V to 2.25V Figure41.AC-CoupledInputandOutput Figure44.InvertingAC-CoupledWideOutput Single-SupplyVideoAmplifier SwingSingle-SupplyVideoAmplifier To further increase dynamic range at the output, the output dc bias should be centered around 2.5 V for APPLICATION CIRCUITS the 5-V system shown. However, a wide output range requires a wide input range, and should be centered ActiveFilteringWiththeSN1050x around 2.5 V. The best ways to accomplish this are High-frequency active filtering with the SN1050x is to ac-couple the gain resistor or bias it at 2.5 V with a achievable due to the amplifier's high slew rate, wide reference supply as shown in Figure 42 and bandwidth, and voltage feedback architecture. Figure43. Several options are available for high-pass, low-pass, 68 m F 1.24 kW 1.24 kW bandpass, and bandstop filters of varying orders. A simple two-pole, low-pass filter is presented in Output Range Figure45asanexample,withtwopolesat25MHz. 5 V = 0.5 V to 4.5V 5 V DAC Output - 75 W V=O 0 RVa tnog 2eV 4.7 pF = 0 V to 2V 3.01 kW 50 W Source + 1.3 kW 470 m F 47 m F 75 W VI 1.3 kW 5 V 3.01 kW Input Range 52.3 W _ = 1.5 V to 3.5V 49.9 W VO Figure42.AC-CoupledWideOutputSwing + Single-SupplyVideoAmplifier 33 pF −5 V 1.24 kW 1.24 kW 2.5 V Figure45.ATwo-PoleActiveFilterWithTwo PolesBetween90MHzand100MHz Output Range 5 V = 0.5 V to 4.5V 5 V VO Range DAC Output - 75 W = 0 V to 2V DrivingCapacitiveLoads = 0 V to 2V 3.01 kW + 470 m F A demanding, yet very common application for an op 47 m F 75 W amp is capacitive loading. Often, this load is the input 3.01 kW Input Range of an A/D converter, including additional external = 1.5 V to 3.5V capacitance, sometimes recommended to improve A/D linearity. A high-speed, high open-loop gain Figure43.AC-CoupledWideOutputSwing amplifier like the SN1050x can be very susceptible to Single-SupplyVideoAmplifierUsingVoltage decreased stability and closed-loop response peaking Reference when a capacitive load is placed directly on the output pin. When the amplifier's open-loop output Another beneficial configuration is to use the amplifier resistance is considered, the capacitance introduces inaninvertingconfigurationasshowninFigure44. an additional pole in the signal path that can decrease the phase margin. When the primary considerations are frequency-response flatness, pulse response fidelity, or distortion, the simplest and most effective solution is to isolate the capacitive load Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 SLOS408B–MARCH2003–REVISEDJANUARY2009.................................................................................................................................................. www.ti.com from the feedback loop by inserting a series isolation ground- and power-plane layout should not be in resistor between the amplifier output and the close proximity to the signal I/O pins. Avoid capacitive load. This does not eliminate the pole from narrow power and ground traces to minimize the loop response, but rather shifts it and adds a zero inductance between the pins and the decoupling atahigherfrequency.Theadditional zero cancels the capacitors. The power supply connections should phase lag from the capacitive-load pole, thus always be decoupled with these capacitors. increasingthephasemarginandimprovingstability. Larger (2.2-m F to 6.8-m F) decoupling capacitors, effective at lower frequency, should also be used PowerSupplyDecouplingTechniquesand on the main supply pins. These may be placed Recommendations somewhat farther from the device and may be shared among several devices in the same area Power-supply decoupling is a critical aspect of any ofthePCboard. high-performance amplifier design process. Careful 3. Careful selection and placement of external decoupling provides higher-quality ac performance, components preserves the high frequency most notably improved distortion performance. The performance of the SN1050x. Choose following guidelines ensure the highest level of low-reactance resistors. Surface-mount resistors performance. work best, and allow a tighter overall layout. 1. Place decoupling capacitors as close to the Metal-film and carbon-composition axial-lead power-supply inputs as possible, with the goal of resistors can also provide good high-frequency minimizing the inductance of the path from performance. Again, keep component leads and groundtothepowersupply PC-board trace length as short as possible. 2. Placement priority; locate the smallest-value Never use wirewound resistors in a high capacitorsnearesttothedevice. frequency application. Since the output pin and inverting-input pin are the most sensitive to 3. Solid power and ground planes are parasitic capacitance, always position the recommended to reduce the inductance along feedback and series-output resistor, if any, as power-supply return-current paths, with the close as possible to the output pin. Other network exception of the areas underneath the input and components, such as noninverting-input outputpins. termination resistors, should also be placed close 4. Recommended values for power supply to the package. Where double-sided component decoupling include a bulk decoupling capacitor mounting is allowed, place the feedback resistor (6.8 to 22 m F), a mid-range decoupling capacitor directly under the package on the other side of (0.1 m F) and a high frequency decoupling the board between the output and inverting input capacitor (1000 pF) for each supply. A 100 pF pins. Even with a low parasitic capacitance capacitorcan be used across the supplies as well shunting the external resistors, excessively high for extremely high-frequency return currents, but resistor values can create significant time oftenisnotrequired. constants that can degrade performance. Good axial-lead metal-film or surface-mount resistors BOARD LAYOUT have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 kΩ, this Achieving optimum performance with a parasitic capacitance can add a pole and/or a high-frequency amplifier like the SN1050x requires zero below 400MHz that can affect circuit careful attention to board layout parasitics and operation. Keep resistor values as low as externalcomponenttypes. possible, consistent with load-driving Recommendationstooptimizeperformanceinclude: considerations. A good starting point for design is 1. Minimize parasitic capacitance to any ac to set the Rf to 1.3 kΩ for low-gain, noninverting ground for all signal I/O pins. Parasitic applications. This automatically keeps the resistor capacitanceontheoutputandinverting-inputpins noise terms low, and minimizes the effect of their can cause instability: on the noninverting input, it parasiticcapacitance. can react with the source impedance to cause 4. Connections to other wideband devices on unintentional band limiting. To reduce unwanted the board may be made with short, direct capacitance, open a window in all ground and traces or through onboard transmission lines. power planes around the signal I/O pins. Keep For short connections, consider the trace and the ground and power planes unbroken elsewhere on input to the next device as a lumped capacitive theboard. load. Use relatively wide traces (50 mils to 100 2. Minimize the distance (< 0.25”) from the mils), preferably with ground and power planes power-supply pins to high frequency 0.1-m F opened up around them. Low parasitic capacitive decoupling capacitors. At the device pins, the loads (<4pF) may not need an R(ISO), since the SN1050x is nominally compensated to operate 14 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):SN10501SN10502SN10503

SN10501 SN10502 SN10503 www.ti.com.................................................................................................................................................. SLOS408B–MARCH2003–REVISEDJANUARY2009 with a 2-pF parasitic load. Higher parasitic THERMAL ANALYSIS capacitive loads without an R are allowed as (ISO) The SN1050x family of devices does not incorporate the signal gain increases (increasing the automatic thermal shutoff protection, so the designer unloaded phase margin). If a long trace is must take care to ensure that the design does not required, and the 6-dB signal loss intrinsic to a violate the absolute-maximum junction temperature of doubly-terminated transmission line is the device. Failure may result if the acceptable, implement a matched-impedance absolute-maximum junction temperature of 150°C is transmission line using microstrip or stripline exceeded. techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A The thermal characteristics of the device are dictated 50-Ω environment is normally not necessary by the package and the PC board. Maximum power onboard, and in fact a higher-impedance dissipation for a given package can be calculated environment improves distortion as shown in the usingthefollowingformula. distortion-versus-load plots. With a characteristic board-trace impedance definition based on board P (cid:1)Tmax–TA material and trace dimensions, a matching series Dmax (cid:1) JA resistor in the trace from the output of the where: SN1050x is used as well as a terminating shunt P is the maximum power dissipation in the amplifier (W). Dmax resistor at the input of the destination device. T is the absolute maximum junction temperature (°C). max Rememberalsothattheterminatingimpedanceis T is the ambient temperature (°C). A the parallel combination of the shunt resistor and q JA = q JC + q CA the input impedance of the destination device: q JC is the thermal coefficient from the silicon junctions to the this total effective impedance should be set to case (°C/W). q is the thermal coefficient from the case to ambient air match the trace impedance. If the 6-dB CA (°C/W). attenuation of a doubly terminated transmission line is unacceptable, a long trace can be 1.5 series-terminated at the source end only. Treat W the trace as a capacitive load in this case and n − 1.25 8-Pin D Package add an R resistor in series with the output to o (ISO) ati isolate any capacitance to the amplifier. This sip 1 setting does not preserve the signal integrity of a Dis doubly-terminated line. If the input impedance of wer 0.75 o 5-Pin DBV Package the destination device is low, the signal is P m attenuated due to the voltage divider formed by mu 0.5 theseriesoutputintotheterminatingimpedance. axi M 5. Socketing a high speed part like the SN1050x − 0.25 D is not recommended. The additional lead length P 0 and pin-to-pin capacitance introduced by the −40 −20 0 20 40 60 80 socket can create a troublesome parasitic TA − Ambient Temperature − °C network which can make it almost impossible to q JA = 170°C/W for 8-Pin SOIC (D) achieve a smooth, stable frequency response. q JA = 324.1°C/W for 5-Pin SOT−23 (DBV) TJ = 150°C, No Airflow Best results are obtained by soldering the SN1050xontotheboard. Figure46. MaximumPowerDissipation vs AmbientTemperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often maximum power dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibilityintoapossibleproblem. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):SN10501SN10502SN10503

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN10501D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 10501D & no Sb/Br) SN10501DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SBBI & no Sb/Br) SN10501DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SBBI & no Sb/Br) SN10501DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 SBBI & no Sb/Br) SN10501DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BHA & no Sb/Br) SN10501DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BHA & no Sb/Br) SN10501DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AJU & no Sb/Br) SN10502D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 10502D & no Sb/Br) SN10502DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AJT & no Sb/Br) SN10502DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AJT & no Sb/Br) SN10502DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AJV & no Sb/Br) SN10502DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 10502D & no Sb/Br) SN10503D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 10503D & no Sb/Br) SN10503PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 SN10503 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN10501DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 SN10501DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 SN10502DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN10502DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN10501DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 SN10501DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 SN10502DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN10502DR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

None

PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated