Application Information SLA7070MPRT Series Unipolar 2-Phase Stepper Motor Driver ICs General Description This document describes the SLA7070MPRT series, which are unipolar 2-phase stepping motor driver ICs. The SLA7070MPRT series employs a clock input method as a control signal input method, enabling full control of the device operation using only a few signal lines, instead of the conventional phase input method that requires about 10 signal lines. This allows simplification of the circuit design Figure 1. SLA7070MPRT packages are fully molded ZIPs with an and a reduced workload on the control microprocessor. exposed pad for heatsink mounting. In addition, the SLA7070MPRT series is improved in its reliability by preventing the IC from damage due to abnor- mal conditions. For example, it has a flag output terminal • Built-in sense resistor, R SInt to signal that a protection circuit has operated. The series • All variants are pin-compatible for enhanced also has a built-in protection circuitry against motor coil design flexibility opens/shorts and thermal shutdown protection as well. • ZIP type 23-pin molded package (SLA package) • Self-excitation PWM current control with fixed off-time All the SLA7070MPRT series ICs are compatible in their (microstepping options off-time adjusted automatically by pin layouts and interface specifications, allowing custom- step reference current ratio; 3 levels) ers the flexibility of choosing the IC that is optimal for the • Built-in synchronous rectifying circuit reduces losses at target equipment characteristics. PWM-off • Synchronous PWM chopping function prevents motor Features and Benefits noise in Hold mode • Sleep mode for reducing the IC input current in • Power supply voltages, V : 46 V (max.), 10 to 44 V BB stand-by state normal operating range • Built-in protection circuitry against motor coil • Logic supply voltages, V : 3.0 to 5.5 V DD opens/shorts and thermal shutdown protection options • Maximum output currents: 1 A, 1.5 A, 2 A, 3 A • Built-in sequencer • Full-, half-, and microstepping available (microstepping Applications options are capable of full-, half-, quarter-, eighth-, and sixteenth-stepping • LBPs, PPCs, ATMs, industrial robots, and so forth The SLA7070MMPR series product variants and optional features Output Current Input Clock Blanking Time Part Number SteRpapteing (IOUT) Edge Detection (µs) (A) Standard Standard SLA7070MPRT 1 SLA7071MPRT Full and 1.5 Rising (positive) 3.2 SLA7072MPRT half step 2 edge SLA7073MPRT 3 SLA7075MPRT 1 SLA7076MPRT 1.5 Rising (positive) Microstep 1.7 SLA7077MPRT 2 edge SLA7078MPRT 3 SLA7070MPRT-AN, Rev. 2 SANKEN ELECTRIC CO., LTD. January 10, 2013 http://www.sanken-ele.co.jp/en/

Table of Contents Specifications 3 Functional Block Diagrams 3 Pin Descriptions 3 Package Outline Drawing 5 Electrical Characteristics 6 Allowable Power Dissipation 10 Typical Application 11 Device Logic 12 Pin Logic and Timing 12 Common Input Pins 12 Monitor Output Pin 12 Logic Input Pins 13 Clock Edge Timing 13 Reset Release and Clock Input Timing 13 Logic Level Change 13 Stepping Sequence Diagrams 14 Motor Excitation Sequencing 21 Individual Circuit Descriptions 22 Monolithic IC (MIC) 22 Output MOSFET Chip 22 Sense Resistor 22 Functional Description 23 PWM Current Control 23 Blanking Time 23 PWM Off-Time 26 Protection Functions 27 Application Information 29 Motor Current Ratio Setting (R1, R2, RS) 29 Lower Limit of Control Current 29 Avalanche Energy 29 On-Off Sequence of Power Supply (VBB and VDD) 30 Motor Supply Voltage (VM) and Main Power Supply Voltage (VBB) 31 Internal Logic Circuits 31 Reset 31 Clock Input 31 Chopping Synchronous Circuit 31 Output Disable (Sleep1 and Sleep2) Circuits 31 Ref/Sleep1 Pin 32 Logic Input Pins 32 Thermal Design Information 32 Characteristic Data 34 SLA7070MPRT-AN, Rev. 2 2 SANKEN ELECTRIC CO., LTD.

Functional Block Diagrams SLA7070MPRT to SLA7073MPRT: Full and Half step R e C OutA OutA OutA OutA VDD f/Sleep1 Flag N.C. M1 M2 M3 W/CCW Clock Reset VBB OutB OutB OutB OutB 1 2 3 4 14 13 18 6 7 8 9 16 10 15 11 20 21 22 23 MIC Reg. Pre- Sequencer Pre- Driver and Driver Sleep Circuit Protect Protect DAC TSD DAC + + Synchro SenseA 5 C-omp PWM Control PWM Com-p 19 SenseB Control Control Rs OSC OSC Rs SLA707xMPRT 17 12 Sync Gnd Pad Side 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21 23 Pin Number. Symbol Function 1, 2 OutA Output of phase A 3, 4 ¯O¯ ¯u¯ ¯ ¯t ¯A¯ Output of phase A¯ 5 SenseA Phase A current sensing 6 N.C. No connection 7 M1 8 M2 Commutation and Sleep2 setting 9 M3 10 Clock Step clock input 11 VBB Main power supply (for motor) 12 Gnd Ground 13 Ref/Sleep1 Input for control current and Sleep1 setting 14 VDD Power supply to logic 15 Reset Reset for internal logic 16 CW/CCW Forward/reverse switch input 17 Sync Synchronous PWM control switch input 18 Flag Output from protection circuits monitor 19 SenseB Phase B current sensing 20, 21 ¯O¯ ¯u¯ ¯ ¯t ¯B¯ Output of phase B¯ 22, 23 OutB Output of phase B SLA7070MPRT-AN, Rev. 2 3 SANKEN ELECTRIC CO., LTD.

SLA7075MPRT to SLA7078MPRT: Microstep R e C OutA OutA OutA OutA VDD f/Sleep1 Flag OM M1 M2 M3 W/CCW Clock Reset VBB OutB OutB OutB OutB 1 2 3 4 14 13 18 6 7 8 9 16 10 15 11 20 21 22 23 MIC Reg. Pre- Sequencer Pre- Driver and Driver Sleep Circuit Protect Protect DAC TSD DAC + + Synchro SenseA 5 C-omp PWM Control PWM Com-p 19 SenseB Control Control Rs OSC OSC Rs SLA707xMPRT 17 12 Sync Gnd Pad Side 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21 23 Pin Number. Symbol Function 1, 2 OutA Output of phase A 3, 4 ¯O¯ ¯u¯ ¯ ¯t ¯A¯ Output of phase A¯ 5 SenseA Phase A current sensing 6 MO 2-phase commutation status monitor output 7 M1 8 M2 Commutation and Sleep2 setting 9 M3 10 Clock Step clock input 11 VBB Main power supply (for motor) 12 Gnd Ground 13 Ref/Sleep1 Input for control current and Sleep1 setting 14 VDD Power supply to logic 15 Reset Reset for internal logic 16 CW/CCW Forward/reverse switch input 17 Sync Synchronous PWM control switch input 18 Flag Output from protection circuits monitor 19 SenseB Phase B current sensing 20, 21 ¯O¯ ¯u¯ ¯ ¯t ¯B¯ Output of phase A¯ 22, 23 OutB Output of phase B SLA7070MPRT-AN, Rev. 2 4 SANKEN ELECTRIC CO., LTD.

Package Outline Drawing, SLA 23-Pin 31 ±0.2 24.4±0.2 4.8±0.2 φ3.2 ±0.15 x 3.8 16.4±0.2 1.7±0.1 Gate Flash φ3.2 ±0.15 ad) caJapan b 9.9±0.2 12.9±0.2 16±0.2 (Heatsink P 5±0.5 (BM2a.es4ae5s ou±fr 0eP.di2n ast) 4-(R1) 5 R-end +1-0. 5 5 0. +0.2 0.65 -0.1 3) 0.55+-00..21 4. ( 22 × P1.27±0.5 = 27.94±1 (Measured at Pin Tips) 4.5±0.7 (Measured at Pin Tips) 31.3 ±0.2 (Includes Mold Flash) a: Item name 1: SLA707xMRT (x is 0 to 3, or 5 to 8; last digit of part number, corresponding to current rating and stepping rate) b: Item name 2: P c: Lot number: 1 3 5 7 9 11 13 15 17 19 21 23 1st letter is last digit of year 2 4 6 8 10 12 14 16 18 20 22 2nd letter is month January to September: 1 to 9 October: O November: N Unit: mm December: D Pin material: Cu 3rd and 4th are date of manufacture (01 to 31) Pin Plating: Solder plating (Pb free) Leadframe plating Pb-free. Device composition includes high-temperature solder (Pb >85%), which is exempted from the RoHS directive. SLA7070MPRT-AN, Rev. 2 5 SANKEN ELECTRIC CO., LTD.

Electrical Characteristics • This section provides separate sets of electrical characteristic data for each product. • The polarity value for current specifies a sink as "+ ," and a source as “−,” referencing the IC. • Please refer to the datasheet of each product for additional details. Absolute Maximum Ratings Unless specifically noted, T is 25°C A Characteristic Symbol Notes Rating Unit Load (Motor Supply) Voltage VM 46 V Main Power Supply Voltage VBB 46 V 6 V Logic Supply Voltage VDD ≤1 μs (5% duty) 7 V SLA7070MPRT 1.0 A SLA7075MPRT SLA7071MPRT 1.5 A SLA7076MPRT Output Current IO Control current value SLA7072MPRT 2.0 A SLA7077MPRT SLA7073MPRT 3.0 A SLA7078MPRT Logic Input Voltage VIN −0.3 to VDD+0.3 V REF Input Voltage VREF −0.3 to VDD+0.3 V Sense Voltage VRS ±2 V Power Dissipation PD Without heatsink 4.7 W Junction Temperature TJ 150 °C Recommended Operating Conditions Unless specifically noted, T is 25°C A Characteristic Symbol Test Conditions Min. Typ. Max. Unit Load (Motor Supply) Voltage VM – – 44 V Main Power Supply Voltage VBB 10 – 44 V Surge voltage at VDD pin should Logic Supply Voltage VDD be less than ±0.5 V to avoid 3.0 – 5.5 V malfunctioning in operation Measured at pin 12, without Case Temperature Tc heatsink – – 90 °C SLA7070MPRT-AN, Rev. 2 6 SANKEN ELECTRIC CO., LTD.

Electrical Characteristics Common to All Variants Unless specifically noted, T is 25°C A Characteristic Symbol Test Conditions Min. Typ. Max. Unit IBB Normal mode – – 15 mA Main Power Supply Current IBBS Sleep1 and Sleep2 mode – – 100 μA Logic Power Current IDD – – 5 mA MOSFET Breakdown Voltage VDSS VBB = 44 V, ID = 1 mA 100 – – V Maximum Response Frequency fclk Clock duty = 50% 250 – – KHz VIL – – 0.25 × VDD V Logic Supply Voltage VIH 0.75 × VDD – – V IIL – ±1 – μA Logic Supply Current IIH – ±1 – μA VREF See figure 1 – – – V REF Input Voltage1 VREFS Output off, Sleep1 mode 2.0 – VDD V REF Input Current IREF – ±10 – μA SENSE Voltage VSENSE VSRteEpF  r=e 0fe troe n1c.5e  Vcurrent ratio: 100% V0R.E0F3 – – V0R.E0F3 – V Sleep to Enable Recovery Time tSE Sleep1 and Sleep2 100 – – μs tcon Clock edge to output on – 2.0 – μs Switching Time tcoff Clock edge to output off – 1.5 – μs Overcurrent Detection Voltage2 VOCP At motor coil short-circuit 0.65 0.7 0.75 V SLA7070MPRT, SLA7075MPRT, – 2.3 – A SLA7071MPRT, SLA7076MPRT Overcurrent Detection Current ( VOCP / RS ) IOCP SLA7072MPRT, SLA7077MPRT – 3.5 – A SLA7073MPRT, SLA7078MPRT – 4.6 – A Load Disconnection Undetected Time topp From PWM off – 2 – µs Measured at back of device case (after heat Overheat Protection Temperature Ttsd has saturated) – 140 – °C VFlagL IFlagL = 1.25 mA – – 1.25 V Flag Output Voltage VFlagH IFlagH = –1.25 mA V1D.2D5 – – – V IFlagL – – 1.25 mA Flag Output Current IFlagH –1.25 – – mA 1In a state of: Sleep1, IBBS, output off, and Sequencer enabled. 2In a condition of VSENSE ≥ VOCP , the protection circuit will activate. SLA7070MPRT-AN, Rev. 2 7 SANKEN ELECTRIC CO., LTD.

Electrical Characteristics Varying with Stepping Sequence Unless specifically noted, T is 25°C, V = 24 V, V = 5 V A BB DD SLA7070MPRT, SLA7071MPRT, SLA7072MPRT, and SLA7073MPRT (Full- and Half-Stepping) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Step Reference Current Ratio Mode F VREF ≈ VSENSE = 100 V, – 100 – % Mode 8 VREF = 0 to 1.0 V – 70 – % PWM Minimum On-Time ton(min) – 3.2 – µs PWM Off-Time toff – 12 – µs SLA7075MPRT, SLA7076MPRT, SLA7077MPRT, and SLA7078MPRT (Microstepping) Mode F – 100 – % Mode E – 98.1 – % Mode D – 95.7 – % Mode C – 92.4 – % Mode B – 88.2 – % Mode A – 83.1 – % Mode 9 – 77.3 – % Step Reference Current Ratio Mode 8 VREF ≈ VSENSE = 100 V, – 70.7 – % VREF = 0 to 1.0 V Mode 7 – 63.4 – % Mode 6 – 55.5 – % Mode 5 – 47.1 – % Mode 4 – 38.2 – % Mode 3 – 29 – % Mode 2 – 19.5 – % Mode 1 – 9.8 – % VMOL IMOL = 1.25 mA – – 1.25 V MO (Load) Output Voltage VMOH IMOH = –1.25 mA VDD – 1.25 – – V IMOL – – 1.25 mA MO (Load) Output Current IMOH –1.25 – – mA PWM Minimum On-Time ton(min) – 1.7 – µs toff1 Mode 8, 9, A, B, C, D, E, and F – 12 – µs PWM Off-Time toff2 Mode 4, 5, 6, and 7 – 9 – µs toff3 Mode 1, 2, and 3 – 7 – µs SLA7070MPRT-AN, Rev. 2 8 SANKEN ELECTRIC CO., LTD.

Electrical Characteristics Varying with Output Current Range Unless specifically noted, T is 25°C, V = 24 V, V = 5 V A BB DD SLA7070MPRT and SLA7075MPRT (I = 1.0 A) O Characteristic Symbol Test Conditions Min. Typ. Max. Unit Output On-Resistance RDS(on) ID = 1 A – 0.7 0.85 Ω Body Diode Forward Voltage Vf If = 1 A – 0.85 1.1 V Sense Resistor* RS ±3% tolerance 0.296 0.305 0.314 Ω REF Input Voltage VREF Within specified current limit, IO = 1.0 A 0.04 – 0.3 V SLA7071MPRT and SLA7076MPRT (I = 1.5 A) O Output On-Resistance RDS(on) ID = 1.5 A – 0.45 0.6 Ω Body Diode Forward Voltage Vf If = 1.5 A – 1.0 1.25 V Sense Resistor* RS ±3% tolerance 0.296 0.305 0.314 Ω REF Input Voltage VREF Within specified current limit, IO = 1.5 A 0.04 – 0.45 V SLA7072MPRT and SLA7077MPRT (I = 2.0 A) Electrical Characteristics O Output On-Resistance RDS(on) ID = 2 A – 0.25 0.4 Ω Body Diode Forward Voltage Vf If = 2 A – 0.95 1.2 V Sense Resistor* RS ±3% tolerance 0.199 0.205 0.211 Ω REF Input Voltage VREF Within specified current limit, IO = 2.0 A 0.04 – 0.4 V SLA7073MPRT and SLA7078MPRT (I = 3.0 A) Electrical Characteristics O Output On-Resistance RDS(on) ID = 3 A – 0.18 0.24 Ω Body Diode Forward Voltage Vf If = 3 A – 0.95 2.1 V Sense Resistor* RS ±3% tolerance 0.150 0.155 0.160 Ω REF Input Voltage VREF Within specified current limit, IO = 3.0 A 0.04 – 0.45 V *Includes the inherent bulk resistance (approximately 5 mΩ) of the resistor itself. SLA7070MPRT-AN, Rev. 2 9 SANKEN ELECTRIC CO., LTD.

VDD Sleep1 Set Range 2.0V Prohibition Zone 0.45V VOCP=0.7V 0.4V 0.3V 1D.e0v Aices 2D.e0v Aices 13..50 AA and Motor Current Set Range* Devices 0V *Motor Current Set Range is determined by the value of the resistor built into the device. Figure 1. Reference Voltage Setting (VREF, REF/SLEEP1 Pin). Please pay extra attention to the change-over between the motor current specification range, IMO , and the Sleep1 Set Range. VOCP falls on the "prohibition zone" threshold. If the change- over time is too slow, OCP operation will start when VSInt > VOCP. 5 ] W [ PD4 Rθj-a=26.6℃/W , n o i t a p 3 i s s i D r e 2 w o P e l b a 1 w o l l A 0 0 10 20 30 40 50 60 70 80 90 Ambient Temperature, T [℃] A Figure 2. Allowable Power Dissipation SLA7070MPRT-AN, Rev. 2 10 SANKEN ELECTRIC CO., LTD.

Typical Application (Microstepper Variants) Vs=10to44V V =3.0to5.5V CA CC OutA OutA VBB OutB OutB VDD Sleep C1 R1 Q1 Reset/Sleep1 Clock CB CW/CCW SLA7075MPRT Micro- M1 SLA7076MPRT controller M2 SLA7077MPRT M3 SLA7078MPRT Sync Mo Flag Ref/Sleep SenseA Gnd SenseB R2 R3 C2 Pin12 Gnd Logic Gnd Power Gnd Figure 3. Typical Application Circuit External Component Typical Values • Take precautions to avoid noise on the VDD line; noise (for reference use only): levels greater than 0.5 V on the VDD line may cause device Component Value Component Value malfunction. Noise can be reduced by separating the logic ground and the power ground on a PCB from the GND pin R1 10 kΩ CA 100 μF / 50 V (pin 12). R2 1 kΩ (varistor) CB 10 μF / 10 V • Unused logic input pins (CW / CCW, M1, M2, M3, Reset, and SYNC) must be pulled up or down to VDD or ground. If R3 10 kΩ C1 0.1 μF those unused pins are left open, the device malfunctions. • Unused logic output pins (Mo, Flag) must be kept open. SLA7070MPRT-AN, Rev. 2 11 SANKEN ELECTRIC CO., LTD.

Truth Tables Monitor Output Pin Common Input Pins The SLA7070MPRT series provides two device status monitor Table 1 shows the truth table for input pins common to both outputs: half/full step and microstep variants of the SLA7070MPRT • Flag pin – Protection feature operation series. • Mo pin (microstep variants only) – Stepping sequence • The Reset function is asynchronous. If the input on the Reset Table 3 shows the logic for the monitor pins. The outputs turn off pin is high, the internal logic circuit is reset. At this point, if the when the protection circuit starts operating. To release the protec- Ref pin stays low, then the DMOS outputs turn on at the starting tion state, cycle (set low, and then high) the logic supply voltage point of excitation. Note that the Disable control functions are not (V ). available with the Reset pin signal set high. DD • Voltage at the Ref / Sleep1 pin controls the PWM current and the Sleep1 function. For normal operation, V should be below REF 1.5 V (low level). Applying a voltage greater than 2.0 V (high Table 2. Commutation-Sleep2 Truth Table for level) to the Ref / Sleep1 pin disables the outputs and puts the Common Input Pins (Half/Full and Microstep) motor in a free state (coast). This function is used to minimize Pin Name power consumption when the device is not in use. Although Full / Half Step Microstep it disables much of the internal circuitry, including the out- M1 M2 M3 put MOSFETs and regulator, the sequencer / translator circuit L L L Full step (Mode 8 fixed) Full step (Mode 8 fixed) remains active. H L L Full step (Mode F fixed) Full step (Mode F fixed) L H L Half step Half step • The Sync function is active only for 2-phase excitation timing. If this function is used during other than 2-phase excitation tim- H H L Half step (Mode F fixed) Half step (Mode F fixed) ing, the overall stepping sequence might collapse because PWM L L H Quarter step off-time and set current are different in each phase A and phase H L H Eighth step Sleep2 function B control scenario. (2-phase excitation timing is when the step L H H Sixteenth step reference current ratio of both phase A and phase B is Mode 8.) H H H Sleep2 function Commutation/Sleep2 Function Table 2 shows the logic of the pins (M1, M2, and M3) which set commutation. In the Sleep2 function, the outputs are disabled and Table 3. Monitor Output Pins Logic the driver supply current (I ) is reduced. However, unlike the BB Pin Name Low Level High Level Sleep1 function, the logic circuitry is put into a standby state and therefore the sequencer / translator circuit is not active. Flag Normal operation Protection circuit operation Other than 2-phase Note: When awakening from Sleep2 mode, a delay of 100 μs or Mo excitation timing 2-phase excitation timing longer before sending a Clock pulse is recommended. Table 1. Truth Table for Common Input Pins (Half/Full and Microstep) Pin Name Low Level High Level Clock Reset Normal operation Logic reset CW/CCW Forward (CW) Reverse (CCW) M1, M2, M3 Commutation (Sleep2 is not included) Ref / Sleep1 Normal operation Sleep1 function Sync Non-sync PWM control Sync PWM control (Positive Edge) SLA7070MPRT-AN, Rev. 2 12 SANKEN ELECTRIC CO., LTD.

Logic Input Pins edges and as setup and hold times. The sequencer logic circuitry The low pass filter incorporated with the logic input pins (Reset, might malfunction if the logic polarity is changed during these Clock, CW/CCW, M1, M2, M3, and Sync) improves noise rejec- setup and hold times. (Refer to figure 4). tion. The logic inputs are CMOS input compatible, and therefore Reset Release and Clock Input Timing they are in a high impedance state. Use the IC at a fixed input level, either low or high. The Reset pulse width is equivalent to the high pulse level hold time. It should be greater than the 2 μs Clock input pulse width. Input Logic Timing When the timing of a Reset release (falling edge) and a Clock edge is simultaneous, the internal logic might cause an unex- Clock Signal pected operation. Therefore, a greater than 5 μs delay is required A low-to-high then high-to-low transition on the Clock input between the falling edge of the Reset input and the next rising advances the sequencer / translator. The Clock pulse width should edge of the Clock input. (Refer to figure 4). be set at 2 μs in both positive and negative polarities. Therefore, clock response frequency should be 250 kHz. Only the positive Logic Level Change edge is used for timing, however, it is necessary to control the Logic level inputs on CW/CCW, M1, M2, and M3 set the transla- logic levels of the Clock signal both before and after each Clock tor step direction (CW/CCW) and step mode (M1, M2, and M3; signal edge sent to the sequencer logic circuit, in order to main- refer to the Commutation Truth Table). Changes to these inputs tain proper stepping operation. do not take effect until the rising edge of the Clock input. How- Clock Edge Timing ever, depending on the type and state of a motor, there may be With regard to the input logic of the CW/CCW, M1, M2, and M3 errors in motor operation. A thorough evaluation on the changes pins, a 1 μs delay should occur both before and after the pulse of sequence should be carried out. Reset 2 µs(min) 5 µs(min) 4 µs(min) Clock 2 µs(min) 2 µs(min) 2 µs(min) 1 µs(min) 1 µs(min) CW/CCW M1, M2, M3 1 µs(min) 1 µs(min) 2 µs(min) Figure 4. Input Signal Timing. When awakening from Sleep1 or Sleep2 mode, a delay of 100 μs or  longer before sending a Clock pulse is recommended. SLA7070MPRT-AN, Rev. 2 13 SANKEN ELECTRIC CO., LTD.

Stepping Sequence Diagrams RESET CLOCK … 0 1 2 B CW A A 0 70.7 CCW 70.7 0 B Figure 5. Full step; for microstep and full/half step products Sequence Selection Pin Logic Mode M1 M2 M3 Full Step Low Low Low 8 Shows the state to which the stepping sequence progresses at the rising (positive) edge of the Clock input. SLA7070MPRT-AN, Rev. 2 14 SANKEN ELECTRIC CO., LTD.

RESET CLOCK … 0 1 2 B CW A A 0 CCW 100 0 B Figure 6. Full step; for microstep and full/half step products Sequence Selection Pin Logic Mode M1 M2 M3 Full Step High Low Low F Shows the state to which the stepping sequence progresses at the rising (positive) edge of the Clock input. SLA7070MPRT-AN, Rev. 2 15 SANKEN ELECTRIC CO., LTD.

RESET CLOCK … 0 1 2 3 4 B CW A A 0 70.7 CCW 100 70.7 0 B Figure 7. Half step; for microstep and full/half step products Sequence Selection Pin Logic Mode M1 M2 M3 Half Step Low High Low 8, F Shows the state to which the stepping sequence progresses at the rising (positive) edge of the Clock input. SLA7070MPRT-AN, Rev. 2 16 SANKEN ELECTRIC CO., LTD.

RESET CLOCK … 0 1 2 3 4 B CW A A 0 CCW 100 0 B Figure 8. Half step; for microstep and full/half step products Sequence Selection Pin Logic Mode M1 M2 M3 Half Step High High Low F Shows the state to which the stepping sequence progresses at the rising (positive) edge of the Clock input. SLA7070MPRT-AN, Rev. 2 17 SANKEN ELECTRIC CO., LTD.

RESET CLOCK … 0 1 2 3 4 5 6 7 ８ B CW A A 0 38.2 70.7 CCW 92.4 100 92.4 70.7 38.2 0 B Figure 9. Quarter step; for microstep products Sequence Selection Pin Logic Mode M1 M2 M3 Quarter Low Low High Step SLA7070MPRT-AN, Rev. 2 18 SANKEN ELECTRIC CO., LTD.

RESET CLOCK … 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B CW A A 0 19.5 38.2 55.5 70.7 83.1 CCW 92.4 98.1 10098.1 92.4 83.1 70.7 55.5 38.2 19.5 0 B Figure 10. Eighth step; for microstep products Sequence Selection Pin Logic Mode M1 M2 M3 Eighth High Low High Step Shows the state to which the stepping sequence progresses at the rising (positive) edge of the Clock input. SLA7070MPRT-AN, Rev. 2 19 SANKEN ELECTRIC CO., LTD.

RESET CLOCK … 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B CW A A 0 9.8 19.5 29.0 38.2 47.1 55.5 63.4 70.7 77.3 83.1 CCW 88.2 92.4 95.7 98.1 100 95.7 88.283.1 77.3 70.7 63.4 55.5 47.1 38.2 29.0 19.5 9.8 0 98.192.4 B Figure 11. Sixteenth step; for microstep products Sequence Selection Pin Logic Mode M1 M2 M3 Sixteenth Low High High Step Shows the state to which the stepping sequence progresses at the rising (positive) edge of the Clock input. SLA7070MPRT-AN, Rev. 2 20 SANKEN ELECTRIC CO., LTD.

Excitation Change Sequence The change of excitation modes is determined by the settings of the excitation pins (M1, M2, and M3) before and after the step signal.Table 4 shows each excitation mode state setting. Table 4. Excitation Mode States Internal Sequence State Step Sequencing Direction Phase A Phase B Full Step Half Step 1/4 Step 1/8 Step 1/16 Step PWM Mode PWM Mode Mode 8 Mode F Mode 8, F Mode F A 8 B 8 X X* X X* X X X A 7 B 9 X A 6 B A X X A 5 B B X Counter A 4 B C X X X Clockwise A 3 B D X A 2 B E X X A 1 B F X – – B F X X X X X A¯ 1 B F X A¯ 2 B E X X A¯ 3 B D X A¯ 4 B C X X X A¯ 5 B B X A¯ 6 B A X X A¯ 7 B 9 X A¯ 8 B 8 X X* X X* X X X A¯ 9 B 7 X A¯ A B 6 X X A¯ B B 5 X A¯ C B 4 X X X A¯ D B 3 X A¯ E B 2 X X A¯ F B 1 X A¯ F – – X X X X X A¯ F B¯ 1 X A¯ E B¯ 2 X X A¯ D B¯ 3 X A¯ C B¯ 4 X X X A¯ B B¯ 5 X A¯ A B¯ 6 X X A¯ 9 B¯ 7 X A¯ 8 B¯ 8 X X* X X* X X X A¯ 7 B¯ 9 X A¯ 6 B¯ A X X A¯ 5 B¯ B X A¯ 4 B¯ C X X X A¯ 3 B¯ D X A¯ 2 B¯ E X X A¯ 1 B¯ F X – – B¯ F X X X X X A 1 B¯ F X A 2 B¯ E X X A 3 B¯ D X A 4 B¯ C X X X A 5 B¯ B X A 6 B¯ A X X A 7 B¯ 9 X A 8 B¯ 8 X X* X X* X X X A 9 B¯ 7 X A A B¯ 6 X X A B B¯ 5 X A C B¯ 4 X X X A D B¯ 3 X A E B¯ 2 X X A F B¯ 1 X A F – – X X X X X A F B 1 X A E B 2 X X Clockwise A D B 3 X A C B 4 X X X A B B 5 X A A B 6 X X A 9 B 7 X ∗ Sequence state is Mode 8, but step reference current ratio is Mode F. Mode F has step reference current ratio of 100%, and PWM off-time of 12 μs. SLA7070MPRT-AN, Rev. 2 21 SANKEN ELECTRIC CO., LTD.

Individual Circuit Descriptions • Protect Circuit A built-in protection circuit against motor coil opens or shorts is provided. Protection is activated by sensing Monolithic IC (MIC) voltage on the internal RSInt resistors; therefore, an overcurrent • Sequencer Logic The single Clock input is used for step tim- condition cannot be detected which results from the the Outx pins ing. Direction is controlled by the CW/CCW input. Commutation or Sensex pins, or both, shorting to Gnd. Protection against motor mode is controlled by the combination of the M1, M2, and M3 coil opens is available only during PWM operation; therefore, inputs logic levels. For details, refer to the Commutation Truth it does not work at constant voltage driving, when the motor is Table. rotating at high speed. Operation of the protection circuit disables all of the DMOS outputs. To come out of protection mode, cycle • PWM Control Each pair of outputs is controlled by a fixed off- the logic supply, V . DD time PWM current-control circuit. The internal oscillator (OSC) sets the off-time. Its operation mechanism is identical to that of • TSD circuit This circuit protects a driver by shifting the output the SLA7070M family. Refer to the PWM Current Control sec- to Disable mode when the temperature of a product control IC tion for further details. (MIC) rises and becomes higher than threshold value. In order to reset, cycle the logic supply, V . DD • Synchronous Control This function prevents occasional motor noise during Hold mode, which normally results from Output MOSFET Chip asynchronous PWM operation of both motor phases. A logic The value of the built-in output DMOS chip varies according high at the Sync input sets synchronous operation. A logic low to which of the four different output current ratings has been sets asynchronous operation. The use of synchronous operation selected. during normal stepping is not recommended because it produces less motor torque and can cause motor vibration due to staircase Sense Resistor current. The use of synchronous operation when the motor is not The resistance varies according to which of the four different in operation is allowed only in full/half step sequence timing, due output current ratings has been selected, as follows: to the difference in the current controlled and PWM off-time at other step sequence timings. Output Current RSInt Resistance (A) (Ω typ) • DAC (D-to-A Converter) In microstep sequencing, the cur- 1 0.305 rent at each step is set by the value of a sense resistor (RSInt), a 1.5 0.305 reference voltage (V ), and the output voltage of the DACs, REF 2 0.205 controlled by the output of the sequencer / translator). Please refer the electric characteristic, Step Reference Current Ratio, page 8. 3 0.155 • Regulator Circuit The integrated regulator circuit is used in driving the output MOSFET gates and powering other internal Each resistance shown above includes the inherent resistance linear circuits. (approximately 5 mΩ) in the resistor itself. SLA7070MPRT-AN, Rev. 2 22 SANKEN ELECTRIC CO., LTD.

Functional Description PWM Current Control Blanking Time The actual operating waveforms on the Sensex pins when driving a motor are shown in figure 12. The actual operating waveforms on the Sensex pins when driving a motor are shown in figure 13. Immediately after PWM turns OFF, ringing (or spike) noise on the Sensex pins isobserved for a few μs. Ringing noise can be A PWM Pulse Width generated by various causes, such as capacitance between motor coils and inappropriate motor wiring. tON t(OFFixFed) I Each pair of outputs is controlled by a fixed off-time (7 to 12 μs, TRIP depending on stepping mode) PWM current-control circuit that limits the load current to a target value, I . Initially, an output 0 TRIP is enabled and current flows through the motor winding and the current-sense resistors. When the voltage across the current sense resistor equals the DAC output voltage, V , the current sense TRIP A comparator resets the PWM latch. This turns off the driver for the Blanking Time fixed off-time, during which the load inductance causes the cur- rent to recirculate for the off-time period. Therefore, if the ringing noise on the sense resistor equals and surpasses V , PWM TRIP turns off. To prevent this phenomenon, the blanking time is set to override signals from the current-sense comparator for a certain period Figure 13. Sensex pin waveform during PWM control immediately after PWM turns on. 5 µs/div 500 ns/div ITRIP ITRIP Figure 12. Operating waveforms on the Sensex pins during PWM chopping (circled area of left panel is shown in expanded scale in right panel) SLA7070MPRT-AN, Rev. 2 23 SANKEN ELECTRIC CO., LTD.

• Blanking time and seeking phenomenon Although current • Coil current waveform distortion during a high velocity control can be improved by shortening blanking time, the degree revolution While a microstep drive is active, the ITrip value of margin to a ringing noise decreases simultaneously. For this changes with the Clock input, to the predetermined value. The reason, when a motor is driven by the device, a seeking phenom- Itrip value (internal reference voltage splitting ratio) is set up to be enon may occur. Figure 14 shows an example of the waveform a sine wave. Because PWM control of the motor coil current is when the phenomenon occurs. set according to the Itrip value, the coil current will be controlled to be sine wave-like. In fact, according the inductance character- istic of the coil, the device requires some time to bring the coil • Blanking time difference The difference in blanking time is current completely to the targeted value. shown in table 5. This comparison is based on the case where Roughly, the relationship between the convergence time (t ) conv drive conditions, such as a motor, motor power supply voltage, between the I value of the coil current and the duty cycle (t ) trip clk and Ref input voltage, and a circuit constant were kept the same of the input Clock pulse in any mode is: while only the indicated parameter was changed. t < t (1) conv clk where the coil current waveform amplitude serves as the limit ▫ Minimum PWM On-time ton(min) . The product blanking time is for Itrip . fixed by the PWM control. Thus, when the on-time is shortened When the current attempts to increase, the full limits of t are in order to reduce the current, it would not go below the blanking conv determined by the damping time constant of power supply volt- time. Minimum PWM On-time refers to the time the output is age and the coil used. When the current attempts to decrease, the on during this blanking period, that is, when the output MOSFET limits are determined by the power supply voltage, the damping actually is turned on. In other words, the blanking time deter- time constant, and the minimum on-time. mines the minimum time (small in table 5). When the frequency of the input clock is raised, because t clk becomes small, it is normal that the case will occur in which the ▫ Minimum coil current. This refers to the coil current when coil current cannot be raised to the I value within a single clock trip PWM control is performed during PWM minimum on-time. In period. In this situation, the waveform amplitude of the coil cur- other words, when the coil current is reduced when the power is rent degenerates from the sine wave, referred to as waveform dis- reduced, where blanking time is shorter can reduce current. tortion. 20 µs/div Table 5. Characteristic Comparison by the Difference in Blanking Time Parameter Better Performance Internal Blanking Time Setting Short Long PWM minimum on-time Short ← Maximize ringing noise suppression → Large Minimum coil current Small ← Coil current waveform distortion at a → Large high rotation (mainly microstep) Figure 14. Example of a Sensex terminal waveform during hunching phenomenon SLA7070MPRT-AN, Rev. 2 24 SANKEN ELECTRIC CO., LTD.

Figure 15 shows the compared result of the waveform distor- The term Large in table 5 means that the wave distortion will be tion by observing the waveform of various devices for which the less where the blanking time is longer, assuming the same drive operating condition of power supply voltage, the current preset conditions, while the wave distortion will be larger where the value, the motor, and so forth are kept the same. As shown in the blanking time is shorter, if the Clock frequency is the same. In places circled (blanking time) in the figure, while the amplitude addition, when such waveform distortion is confirmed, there is envelope of the Sensex pin waveform, which is the same as the uncertainty if the motor characteristic will be affected. Therefore, current waveform, in the 1.7 μs case has become sine wave-like, please make a final judgment after evaluating very thoroughly. the blanking time in the 3.2 μs case has degenerated from an ideal sine wave. Blanking Time: 1.51 .µ5s (typt)yp( Clock SenseA SenseB 500 µs/div Figure 15. Comparison of a Sense terminal waveform during high speed revolution SLA7070MPRT-AN, Rev. 2 25 SANKEN ELECTRIC CO., LTD.

PWM Off-Time Figure 16 shows the difference in back EMF generation between the SLA7060M series and SLA7070MPRT series. The The PWM off-time for the SLA7070MPRT series is controlled SLA7060M series performs on–off operations using only the at a fixed time by an internal oscillator. It also is switched in MOSFET on the PWM-on side, but the SLA7070MPRT series three levels by current proportion (see the Electrical Character- istics table). In addition, the SLA7070MPRT series provides a also performs on–off operations using only the MOSFET on function that decreases losses occurring when the PWM turns the PWM-off side. To prevent simultaneous switching of the off. This function dissipates back EMF stored in the motor coil MOSFETs at synchronous rectification operation, the IC has a at MOSFET turn-on, as well as at PWM turn-on (synchronous dead time of approximately 0.5 μs. During dead time, the back rectification operation). EMF flows through the body diode of the MOSFET. SLA7060M Series SLA7070MPRT Series VBB VBB Ion Ioff Ion Ioff Stepper Motor Stepper Motor Vg Vg Vg Vg Back EMF at Dead Time RSExt RSInt VS VS +V +V PWM On PWM Off PWM On PWM On PWM Off PWM On Dead Dead Vg Vg Time Time FET Gate 0 FET Gate 0 Signal Signal t t Vg Vg VREF VREF VS VS 0 0 t t Figure 16. Synchronous rectification operation SLA7070MPRT-AN, Rev. 2 26 SANKEN ELECTRIC CO., LTD.

Protection Functions rises, and when the applied energy exceeds the tolerance, the driver will be destroyed. Therefore, a circuit which detects The SLA7070MPRT series includes a motor coil short-circuit this avalanche state and protects the driver was added in the protection circuit, a motor coil open protection circuit, and an SLA7070MPRT series. The operation is shown in figure 18. overheating protection circuit. An explanation of each protection circuit is provided below. As explained above, when the motor coil is disconnected, the accumulated voltage in the MOSFET causes a reverse current to • Motor Coil Short-Circuit Protection (Load Short) Circuit. flow during the PWM off-time. For this reason, V that is nega- This protection circuit, embedded in the SLA7070MPRT series, RS tive during the PWM off-time in a normal operation becomes begins to operate when the device detects an increase in the sense positive when the motor coil is disconnected. Thus, a discon- resistor voltage level, V . The voltage at which motor coil short- RS nected motor is detectable by sensing that V in the PWM off- circuit protection starts its operation, V , is set at approxi- RS OCP time is positive. mately 0.7 V. The output is disabled at the time the protection circuit starts, where VRS exceeds VOCP . (See figure 17.) In the SLA7070MPRT series, in order to avoid detection mal- functions, when a state of motor disconnection is detected 3 times • Motor Coil Open Protection (Patent acquired) Driver destruc- continuously, the protection functions are enabled (figure 19). tion can occur when one output pin (motor coil) is disconnected in a unipolar drive during operation. This is because a MOSFET Note: When the breakdown of an output is confirmed by the connected after disconnection will be in the avalanche break- occurrence of surge noise after PWM turn-off, when a breakdown down state, where very high energy is added with back EMF condition continues after an overload disconnection undetected when PWM is off. With an avalanche state, an output cancels time (t ) has elapsed, even if the load is not actually discon- opp the energy stored in the motor coil where the resisting pressure nected, a protection feature may operate. Please review the place- between the drain and source of the MOSFET is reached (the ment of the motor, wiring, and so forth to improve and to settle condition which caused the breakdown). the breakdown time within the load disconnection undetected time (t ) (application variations also must be taken into consid- Although MOSFETs with a certain amount of avalanche energy opp eration). When the breakdown is not confirmed, there will be no tolerance rating are used in the SLA7070MPRT series, avalanche issue in operation. Moreover, the device may be made to operate energy tolerance falls as temperature increases. normally by inserting a capacitor for surge noise suppression Because high energy is added repeatedly whenever PWM opera- between the Out and Gnd pins as one possible corrective strategy. tion disconnects the MOSFET, the temperature of the MOSFET VM Coil Short Circuit Coil Short Circuit +V Normal Operation Output Disable VOCP Stepper Motor Vg VREF VS 0 VS RSInt t Figure 17. Motor coil short circuit protection circuit operation. Overcurrent that flows without passing the sense resistor is undetectable. To recover the circuit after protection operates, VDD must be cycled and started up again. SLA7070MPRT-AN, Rev. 2 27 SANKEN ELECTRIC CO., LTD.

Surge does not Breakdown period Breakdown period reach VDSS level shorter than tOPP longer than tOPP When the product temperature rises and exceeds T , the protec- tsdk t t t tion circuit starts operating and all the outputs are set to Disable OPP OPP OPP mode. VDSS Note: This product has multichip composition (one IC for control, four MOSFETs, and two chip resistors). Although the loca- VOUT tion which actually detects temperature is the control IC (MIC), because the main heat sources are the MOSFET chips and the chip resistors, which are separated by a distance from the control t t t CONFIRM CONFIRM CONFIRM IC, some delay will occur while the heat propagates to the control No problem No problem Improvement IC. For this reason, because a rapid temperature change cannot required be detected, please perform worst-case thermal evaluations in the Figure 19. Coil Open Protection (Patent acquired) application design phase. PWM Operation PWM Operation at Normal Device Operation at Motor Disconnection VM VM Stepper Motor Stepper Motor Ion Ioff Disconnection Vg Vg VOUT VOUT VRS RS VRS RS Motor Disconnection FET FET Gate Signal Gate Signal Vg Vg 0 0 VDSS 2VM Vout Vout VM Breakdown (Avalanche state) 0 0 VREF VREF VRS VRS 0 0 Motor Disconnection Sense Figure 18. Motor coil short circuit protection circuit operation. Overcurrent that flows without passing the sense resistor is undetectable. To recover the circuit after protection operates, VDD must be cycled and started up again. SLA7070MPRT-AN, Rev. 2 28 SANKEN ELECTRIC CO., LTD.

Application Information Motor Current Ratio Setting (R1, R2, RS) RDS(on) is the MOSFET on-resistance, The setting calculation of motor current, IOUT , for the IO is the target current level, SLA7070MPRT series is determined by the ratios of the external R is the motor winding resistance, components R1, R2, and current sense resistor, RS. The following m L is the motor winding reactance, is a formula for calculating I : m OUT R2 tOFF is the PWM off-time, and IOUT = R1 + R2 VDD / RS (2) tC is calculated as: when VREF is within specification. If VREF is set less than 0.1 V, tc = Lm / R , (5) variation or impedance of the wiring pattern may influence the IC where and the possibility of less accurate current sensing becomes high. R = R + R + R (6) m DS(on) S The standard voltage for current ITrip that the SLA7070MPRT Even if the control current value is set at less than the lower limit series controls is partially divided by the internal DAC: of the control current, there is no setting at which the IC fails to V operate. However, control current will worsen against setting REF ITrip= Mode Proportion (3) current. RS Lower Limit of Control Current Avalanche Energy The SLA7070MPRT series uses a self-oscillating PWM current In the unipolar topology of the SLA7070MPRT series, a surge control topology in which the off- time is fixed. As energy stored voltage (ringing noise) that exceeds the MOSFET capacity to in motor coil is eliminated within the fixed PWM off-time, coil withstand might be applied to the IC. To prevent damage, the current flows intermittently, as shown in figure 20. Thus, average SLA7070MPRT series is designed with a built-in MOSFET hav- current decreases and motor torque also decreases. ing sufficient avalanche resistance to withstand this surge volt- age. Therefore, even if surge voltages occur, users will be able The point at which current starts flowing to the coil is considered to use the IC without any problems. However, in cases in which as the lower limit of the control current, I (min) , where I is OUT OUT the motor harness is long or the IC is used above its rated current the target current level. The lower limit of control current differs or voltage, there is a possibility that an avalanche energy could by conditions of the motor or other factors, but it is calculated be applied that exceeds Sanken design expectations. Thus, users from the following formula: must test the avalanche energy applied to the IC under actual application conditions. VM 1 The following procedure can be used to check the avalanche IO(min) = R –t – 1 (4) energy in an application. OFF exp t c where V is the motor supply voltage, M A I TRIP(Big) I 0 TRIP(Small) A Figure 20. Control current lower limit model waveform SLA7070MPRT-AN, Rev. 2 29 SANKEN ELECTRIC CO., LTD.

Given: VM From the waveform test result (reference figure 22) V = 140 V, DS(AV) I Stepper Motor I = 1 A, and D D t = 0.5 μs. The avalanche energy, E can be calculated using the following: VDS(AV) AV EAV=VDS(AV) 1/2 ID t (7) RSInt = 140 (V) 1/2 1 (A)0 .5 10-6 (µs) = 0.035 (mJ) Figure 21. Test points By comparing the E calculated with the graph shown in fig- AV ure 23, the application can be evaluated if it is safe for the IC, by being within the avalanche energy-tolerated does range of the MOSFET. VDS(AV) On-Off Sequence of Power Supply (VBB and VDD) There is no restriction of the on-off sequence between the main power supply, VBB, and the logic supply, VDD. I D t Figure 22. Waveform at avalanche breakdown 20 SLA7073M and SLA7078M 16 ] J12 SLA7072M m and SLA7077M [ V A SLA7071M and E 8 SLA7076M SLA7070M and 4 SLA7075M 0 0 25 50 75 100 125 150 Product Temperature, Tc [°C] Figure 23. SLA7070MPRT iterated avalanche energy tolerated level, EAV(max) SLA7070MPRT-AN, Rev. 2 30 SANKEN ELECTRIC CO., LTD.

Motor Supply Voltage (V ) and Main Power Supply The schematic diagram in figure 24 shows how the IC is designed M Voltage (V ) so that the Sync signal can be determined by the Clock input BB Because the SLA7070MPRT series has a structure that sepa- signal. When a logic high signal is received on the Clock pin, rates the control IC (MIC) and the power MOSFETs as shown the internal capacitor, C, is charged, and the Sync signal is set to in the Functional Block diagrams, the motor supply and main logic low level. However, if the Clock signal cannot rise above power supply are separated. Therefore, it is possible to drive logic low level (such as when the circuit between the microcom- the IC using different power supplies and different voltages for puter and the IC is not adequate), the capacitor is discharged by motor supply and main power supply. However, extra caution is the internal resistor, R, and the Sync signal is set to logic high, required because the supply voltage ranges differ among power causing the IC to shift to synchronous mode. supplies. The RC time constant in the circuit should be determined by the minimum clock frequency used. In the case of a sequence that Internal Logic Circuits keeps the Clock input signal at logic high, an inverter circuit must Reset be added. In a case where the Clock signal is set at an undeter- The sequencer/translator circuit of this product is initialized after mined level, an edge detection circuit (figure 25) can be used to logic supply (VDD) is applied, and the power-on reset function prepare the signal for the Clock input, allowing correct process- operates. To initialize the sequencer/translator, the output imme- ing by the circuit shown in figure 24. diately after power-on indicates the status that the power circuits are in the home state. In a case where the sequencer/translator Output Disable (Sleep1 and Sleep2) Circuits must be reset after the motor has been operating, a reset signal There are two methods to set this IC at motor free-state (coast, must be input on the Reset pin. In a case in which external reset with outputs disabled). One is to set the Ref/Sleep1 pin to more control is not necessary, and the Reset pin is not used, the Reset than 2 V (Sleep1), and the other (Sleep2) is to set the excitation pin must be pulled to logic low on the application circuit board. signals (pins M1, M2, and M3). In either way, the IC will change to Sleep mode, stopping the main power supply at the same time, Clock Input and decreasing circuit current. The difference between the two When the Clock input signal stops, excitation changes to the methods is that, in the first way, the internal sequencer remains motor Hold state. At this time, there is no difference to the IC if in an enabled state, and in the latter method, the IC enters the the Clock input signal is at the low level or the high level. The SLA7070MPRT series is designed to move one sequence incre- ment at a time, according to the current stepping mode, when a VCC positive Clock pulse edge is detected. 74HC14 74HC14 Clock Sync Chopping Synchronous Circuit The SLA7070MPRT series has a chopping synchronous func- tion to protect from abnormal noises that may occasionally occur during the motor Hold state. This function can be operated by R C setting the Sync pin at high level. However, if this function is used during motor rotation, control current does not stabilize, and therefore this may cause reduction of motor torque or increased Figure 24. Clock signal shutoff detection circuit vibration. So, Sanken does not recommend using this function while the motor is rotating. In addition, the synchronous circuit should be disabled in order to control motor current properly in case it is used other than in dual excitation state (Modes 8 and F) Clock Step or single excitation Hold state. Clock In normal operation, generally the input signal for switching can be sent from an external microcomputer. However, in applica- tions where the input signal cannot be transmitted adequately due to limitations of the port, the following method can be taken to Figure 25. Clock signal edge detection circuit use the functions. SLA7070MPRT-AN, Rev. 2 31 SANKEN ELECTRIC CO., LTD.

Hold state. Moreover, in the method using the excitation signals where (Sleep2), excitation timing remains in a standby state, even if a P is the power dissipation in the IC, signal is input on the Clock pin during Sleep mode. I is the operating output current, OUT When awaking to normal operating mode (motor rotation) from R is the resistance of the output MOSFET, and Disable (Sleep1 or Sleep2) mode, set an appropriate delay time DS(on) from cancellation of the Disable mode to the initial Clock input RS is the current sense resistance. edge. In doing so, consider not only the rise time for the IC, Based on the PD calculated using the above formula, the but also the rise time for the motor excitation current, which is expected increase in operating junction temperature, ΔT , of the J important (see figure 26). IC can be estimated using figure 28. This result must be added to the worst case ambient temperature when operating, T (max). Ref/Sleep1 Pin A Based on the calculation, there is no problem unless T (max) plus The Ref/Sleep1 pin provides access to the following functions: A ΔT exceeds 150°C. J • Standard voltage setting for output current level setting • Output Enable-Disable control input Ref/Sleep1 or These functions are further described in the Truth Table section, M1, M2, and M3 and in the discussion of output disabling, above. 100 µs Range A. In this range, control current value also varies in (minimum) accordance with VREF. Therefore, losses in the IC and the sense Clock resistors must be given extra consideration. t Range B. In this range, the voltage that switches output enable and disable (Sleep mode) exists. At enable, the same cautions Figure 26. Timing delay between Disable mode cancellation and the next apply as in range A. In addition, for some cases, there are pos- Clock input sibilities that the output status will become unstable as a result of iteration between enable and disable. V Logic Input Pins DD If a logic input pin (Clock, Reset, CW/CCW, M1, M2, M3, or Sync) is not used (fixed logic level), the pin must be tied to VDD Static electricity or Gnd. Please do not leave them floating, because there is pos- Mo or FLAG protection circuit sibility of undefined effects on IC performance when they are left open. Output Pins (MO and Flag). The MO and Flag output pins are designed as monitor outputs, and inside of the IC is an output Figure 27. MO pin and Flag pin general internal circuit layout inverter (see figure 27). Therefore, let these pins float if they are not used. 150 e r u Thermal Design Information at 125 r e It is not practical to calculate the power dissipation of the p m 100 SLA7070MPRT series accurately, because that would require e factors that are variable during operation, such as time periods n TC) ∆TJ-A = 26.6 x PD o°75 and excitation modes during motor rotation, input frequencies nctiT (J ∆TC-A = 21.3 x PD and sequences, and so forth. Given this situation, it is preferable u∆50 J to perform an approximate calculation at worst conditions. The e in 25 following is a simplified formula for calculation of power dis- s a e sipation: cr 0 n I 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 PD= I2OUT (RDS(on)+ RS) 2 (8) Maximum Allowable Power Dissipation, PD(max) (W) Figure 28. Temperature increase SLA7070MPRT-AN, Rev. 2 32 SANKEN ELECTRIC CO., LTD.

When the IC is used with a heatsink attached, device package CAUTION thermal resistance, R , is a variable used in calculating ΔT . θJA j-a The SLA7070MPRT series is designed as a multichip, with The value of R is calculated from the following formula: θFIN separate power elements (MOSFET), control IC (MIC), and RθJA≈RθJC+RθFin=RθJA–RθCA+RθFin (9) sense resistance. Consequently, because the control IC cannot accurately detect the temperature of the power elements (which where Rθj-a is the thermal resistance of the heatsink. ΔTj-a can be are the primary sources of heat), the ICs do not provide a protec- calculated with using the value of RθJA. tion function against overheating. For thermal protection, users must conduct sufficient thermal evaluations to be able to ensure The following procedure should be used to measure product tem- that the junction temperature does not exceed the warranty level perature and to estimate junction temperature in actual operation: (150°C). First, measure the temperature rise at pin 12 of the device (ΔT ). c-a This thermal design information is provided for preliminary Second, estimate the loss (P) and junction temperature (Tj) from design estimations only. The thermal performance of the IC will the temperature rise with reference to figure 28, temperature be significantly determined by the conditions of the application, increase graph. At this point, the device temperature rise )(ΔTc-a) in particular the state of the mounting PCB, heatsink, and the and the junction temperature rise (Tj) are almost equivalent under ambient air. Before operating the IC in an application, the user the following formula: must experimentally determine the actual thermal performance. The maximum recommended case temperatures (at the center, pin ∆T ≈ ∆T +P R J c-a D θj-c (10) 12) for the IC are: • With no external heatsink connection: 90°C • With external heatsink connection: 80° SLA7070MPRT-AN, Rev. 2 33 SANKEN ELECTRIC CO., LTD.

Characteristic Data Output MOSFET On-Voltage, VDS(on) SLA7070MPRT/SLA7075MPRT SLA7071MPRT/SLA7076MPRT 1.4 1.4 Io=1.5A Io=1A 1.2 1.2 1.0 1.0 V)0.8 V) 0.8 ( Io=0.5A ( on) on) Io=1A S(0.6 S( 0.6 D D V V 0.4 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Product Temperature, TC (°C) Product Temperature, TC (°C) SLA7072MPRT/SLA7077MPRT SLA7073MPRT/SLA7078MPRT 1.2 1.4 Io=2A Io=3A 1.2 1.0 1.0 0.8 V) V) 0.8 Io=2A ( ( on)0.6 on) S( Io=1A S( D D 0.6 V V 0.4 Io=1A 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Product Temperature, TC (°C) PrPordoudcut cTt eTmepmepreartuartuer, eT, CT C(° C(°)C) SLA7070MPRT-AN, Rev. 2 34 SANKEN ELECTRIC CO., LTD.

Output MOSFET Body Diode Forward Voltage, Vf SLA7070MPRT/SLA7075MPRT SLA7071MPRT/SLA7076MPRT 1.1 1.1 1.0 1.0 0.9 0.9 ) ) V V ( ( V f V f 0.8 Io=1A 0.8 Io=1.5A 0.7 Io=0.5A 0.7 Io=1A 0.6 0.6 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Product Temperature, T (°C) Product Temperature, T (°C) C C SLA7072MPRT/SLA7077MPRT SLA7073MPRT/SLA7078MPRT 1.1 1.1 1.0 1.0 Io=3A 0.9 0.9 ) ) V V V (f Io=2A V (f Io=2A 0.8 0.8 Io=1A 0.7 0.7 Io=1A 0.6 0.6 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Product Temperature, T (°C) Product Temperature, T (°C) C C SLA7070MPRT-AN, Rev. 2 35 SANKEN ELECTRIC CO., LTD.

• The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the latest revision of the document before use. • Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the prod- ucts herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or any other rights of Sanken or any third party which may result from its use. • Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semicon- ductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device failure or malfunction. • Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equip- ment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products herein. The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited. • In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum values must be taken into consideration. In addition, it should be noted that since power devices or IC's including power devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly. • When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility. • Anti radioactive ray design is not considered for the products listed herein. • Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken's distribu- tion network. • The contents in this document must not be transcribed or copied without Sanken's written consent. SLA7070MPRT-AN, Rev. 2 36 SANKEN ELECTRIC CO., LTD.