SiM3L1xx High-Performance, Low-Power, 32-Bit Precision32™ MCU Family with up to 256 kB of Flash 32-bit ARM Cortex-M3 CPU Analog Peripherals - 50 MHz maximum frequency - 12-Bit Analog-to-Digital Converter: Up to 250 ksps 12-bit mode - Single-cycle multiplication, hardware division support or 1 Msps 10-bit mode - Nested vectored interrupt control (NVIC) with 8 priority levels - 10-Bit Current-mode Digital-to-Analog Converter - 2 x Low-current comparators Memory - 32–256 kB flash, in-system programmable Digital and Communication Peripherals - 8–32 kB SRAM with configurable low power retention - 1 x USART with IrDA and ISO7816 Smartcard support - 1 x UART that operates in low power mode Clock Sources - 2 x SPIs, 1 x I2C, 16/32-bit CRC - Internal oscillator with PLL: 23–50 MHz - 128/192/256-bit Hardware AES Encryption - Low power internal oscillator: 20 MHz - Encoder/Decoder: Manchester and Three-out-of-Six - Low frequency internal oscillator (LFO): 16.4 kHz - Integrated LCD Controller: up to 160 segments (40x4), auto- - External real-time clock (RTC) crystal oscillator contrast and low power operation - External oscillator: Crystal, RC, C, CMOS clock Timers/Counters Power Management - 3 x 32-bit or 6 x 16-bit timers with capture/compare - Three adjustable low drop-out (LDO) regulators - 16-bit, 6-channel counter with capture/compare/PWM and - Power-on reset circuit and brownout detectors dead-time controller with differential outputs - DC-DC buck converter allows dynamic voltage scaling for - 16-bit low power timer/advanced capture counter operational in maximum efficiency (250 mW output) the lowest power mode - Multiple power modes supported for low power optimization - 32-bit real time clock (RTC) with multiple alarms - Watchdog timer Low Power Features - Low power mode advanced capture counter (ACCTR) - 75 nA typical current in Power Mode 8 - Low-current RTC (180 nA from LFO, 300 nA from crystal) Data Transfer Peripherals - 4 µs wakeup, register state retention and no reset required from - 10-Channel DMA Controller lowest power mode - 3 Channel Data Transfer Manager manages complex DMA - 175 µA/MHz at 3.6 V executing from flash transfers without core intervention - 140 µA/MHz at 3.6 V executing from SRAM On-Chip Debugging - Specialized on-chip charge pump reduces power consumption - Process/Voltage/Temperature (PVT) Monitor - Serial wire debug (SWD) with serial wire viewer (SWV) or JTAG (no boundary scan) allow debug and programming 5 V Tolerant Flexible I/O - Cortex-M3 embedded trace macrocell (ETM) - Up to 62 contiguous 5 V tolerant GPIO with one priority cross- Package Options bar providing flexibility in pin assignments - QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm) Temperature Range: –40 to +85 °C - TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) Supply Voltage: 1.8 to 3.8 V Power Core / Memory / Support Analog Peripherals Scalable Digital LDO ARM Cortex M3 (50 MHz) SAR ADC ng DSSCcca-aDlalaCbb lelBe u MAcenkm aClooorgny v LLeDDrOtOer 321/604-C/1h2 D8/M25A6 C koBn Ftrloalslehr + 3x8 /D16a/t3a2 T RkraBAn MRsfeetre Mntgior.n (12-biCt V2u5orr0ltea nkgste-pS sRo /eu 1frec0re-e bDnitcA 1eC Msps) xible Pin Muxi nt I/O Pins Low Power Mode Charge Pump Watchdog Supply Monitor 2 x Low Current Comparators Fle era Power Management Unit Serial Wire or JTAG Debug / Programming + ETM Advanced Capture Counter Tol V- 5 n o Clocking / Oscillators Digital Peripherals ncti Real-Tim16e2 0kCH MlozHc Lkzo wLw5o/0 FwD Mr eePHdqoizucw eaPentLerc LdOy CsOcrsyilclsaitltlaaolt roOrscillator Clock Selectionand Gating 1 Ex n1I2c xCo dUeAr/R3D Txe, c2 31o 2x dx- beS UirtP STIAimReTr sw (/6 AIL rxEoD wS1A6-/PS-bomiwt)aertrC TaCimrdReCr Priority Crossbar Encoder 62 Multi-Fu External Clock (XTAL / RC / C / CMOS) 6-Channel PWM LCD Controller Rev 1.1 11/14 Copyright © 2014 by Silicon Laboratories SiM3L1xx

2 Rev 1.1

SiM3L1xx Table of Contents 1. Related Documents and Conventions...............................................................................5 1.1. Related Documents........................................................................................................5 1.1.1. SiM3L1xx Reference Manual.................................................................................5 1.1.2. Hardware Access Layer (HAL) API Description....................................................5 1.1.3. ARM Cortex-M3 Reference Manual.......................................................................5 1.2. Conventions...................................................................................................................5 2. Typical Connection Diagrams............................................................................................6 2.1. Power.............................................................................................................................6 3. Electrical Specifications......................................................................................................8 3.1. Electrical Characteristics................................................................................................8 3.2. Thermal Conditions......................................................................................................30 3.3. Absolute Maximum Ratings..........................................................................................31 4. Precision32™ SiM3L1xx System Overview.....................................................................32 4.1. Power...........................................................................................................................34 4.1.1. DC-DC Buck Converter (DCDC0)........................................................................34 4.1.2. Three Low Dropout LDO Regulators (LDO0)......................................................35 4.1.3. Voltage Supply Monitor (VMON0).......................................................................35 4.1.4. Power Management Unit (PMU)..........................................................................35 4.1.5. Device Power Modes...........................................................................................35 4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0).......................38 4.2. I/O.................................................................................................................................39 4.2.1. General Features.................................................................................................39 4.2.2. Crossbar..............................................................................................................39 4.3. Clocking........................................................................................................................40 4.3.1. PLL (PLL0)...........................................................................................................41 4.3.2. Low Power Oscillator (LPOSC0).........................................................................41 4.3.3. Low Frequency Oscillator (LFOSC0)...................................................................41 4.3.4. External Oscillators (EXTOSC0)..........................................................................41 4.4. Integrated LCD Controller (LCD0)................................................................................42 4.5. Data Peripherals...........................................................................................................43 4.5.1. 10-Channel DMA Controller.................................................................................43 4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2).................................................43 4.5.3. 128/192/256-bit Hardware AES Encryption (AES0)............................................43 4.5.4. 16/32-bit Enhanced CRC (ECRC0).....................................................................44 4.5.5. Encoder / Decoder (ENCDEC0)..........................................................................44 4.6. Counters/Timers...........................................................................................................45 4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2)...........................................................45 4.6.2. Enhanced Programmable Counter Array (EPCA0).............................................45 4.6.3. Real-Time Clock (RTC0).....................................................................................46 4.6.4. Low Power Timer (LPTIMER0)............................................................................46 4.6.5. Watchdog Timer (WDTIMER0)............................................................................46 4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0)...................................47 4.7. Communications Peripherals.......................................................................................48 4.7.1. USART (USART0)...............................................................................................48 Rev 1.1 3

SiM3L1xx 4.7.2. UART (UART0)....................................................................................................48 4.7.3. SPI (SPI0, SPI1)..................................................................................................49 4.7.4. I2C (I2C0)............................................................................................................49 4.8. Analog..........................................................................................................................50 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)...................................................50 4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0).........................................................50 4.8.3. Low Current Comparators (CMP0, CMP1)..........................................................50 4.9. Reset Sources..............................................................................................................51 4.10.Security........................................................................................................................52 4.11.On-Chip Debugging.....................................................................................................52 5. Ordering Information.........................................................................................................53 6. Pin Definitions....................................................................................................................55 6.1. SiM3L1x7 Pin Definitions.............................................................................................55 6.2. SiM3L1x6 Pin Definitions.............................................................................................62 6.3. SiM3L1x4 Pin Definitions.............................................................................................69 6.4. TQFP-80 Package Specifications................................................................................74 6.4.1. TQFP-80 Solder Mask Design.............................................................................77 6.4.2. TQFP-80 Stencil Design......................................................................................77 6.4.3. TQFP-80 Card Assembly.....................................................................................77 6.5. QFN-64 Package Specifications..................................................................................78 6.5.1. QFN-64 Solder Mask Design...............................................................................80 6.5.2. QFN-64 Stencil Design........................................................................................80 6.5.3. QFN-64 Card Assembly.......................................................................................80 6.6. TQFP-64 Package Specifications................................................................................81 6.6.1. TQFP-64 Solder Mask Design.............................................................................84 6.6.2. TQFP-64 Stencil Design......................................................................................84 6.6.3. TQFP-64 Card Assembly.....................................................................................84 6.7. QFN-40 Package Specifications..................................................................................85 6.7.1. QFN-40 Solder Mask Design...............................................................................87 6.7.2. QFN-40 Stencil Design........................................................................................87 6.7.3. QFN-40 Card Assembly.......................................................................................87 7. Revision Specific Behavior...............................................................................................88 7.1. Revision Identification..................................................................................................88 Document Change List...........................................................................................................90 Contact Information................................................................................................................91 4 Rev 1.1

SiM3L1xx 1. Related Documents and Conventions 1.1. Related Documents This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices. 1.1.1. SiM3L1xx Reference Manual The Silicon Laboratories SiM3L1xx Reference Manual provides the detailed description for each peripheral on the SiM3L1xx devices. 1.1.2. Hardware Access Layer (HAL) API Description The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual. 1.1.3. ARM Cortex-M3 Reference Manual The ARM-specific features like the Nested Vectored Interrupt Controller are described in the ARM Cortex-M3 reference documentation. The online reference manual can be found here: http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3. 1.2. Conventions The block diagrams in this document use the following formatting conventions: Internal Module Other Internal External Memory Peripheral Block Block DMA Block Memory Block External to MCU Block Input_Pin Output_Pin Functional Block Internal_Input_Signal Internal_Output_Signal REGn_NAME / BIT_NAME Figure 1.1. Block Diagram Conventions Rev 1.1 5

SiM3L1xx 2. Typical Connection Diagrams This section provides typical connection diagrams for SiM3L1xx devices. 2.1. Power Figure 2.1 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck converter is not used. SiM3L1xx Device VIORF VIO DC-DC IND Converter VBAT/VBATDC VDC VLCD VDRV 1 uF and 0.1 uF bypass capacitors required for Low Dropout each power pin placed Regulator (LDO0) as close to the pins as possible. VSSDC VSS 10 uF capacitor required on the VLCD pin Figure 2.1. Connection Diagram with DC-DC Converter Unused Figure 2.2 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the internal dc-dc buck converter is in use and I/O are powered directly from the battery. SiM3L1xx Device VIORF 4.7, 0.1, and 0.01 uF bypass capacitors VIO 0.56 uH inductor required on required between the DC-DC IND VBAT/VBATDC input Converter IND and VDC pins VBAT/VBATDC VDC to external VLCD VDRV circuitry 1 uF and 0.1 uF bypass capacitors required for Low Dropout 2.2, 0.1, and 0.01 uF each power pin placed Regulator bypass capacitors (LDO0) as close to the pins as required on VDC output possible. VSSDC VSS 10 uF capacitor required on the VLCD pin Figure 2.2. Connection Diagram with DC-DC Converter Used and I/O Powered from Battery Figure 2.3 shows a typical connection diagram for the power pins of the SiM3L1xx devices when used with an external radio device like the Silicon Labs EZRadio® or EZRadioPRO® devices. Rev 1.1 6

SiM3L1xx 1 uF and 0.1 uF bypass SiM3L1xx Device capacitors required for each I/O power pin 0.56 uH inductor required between the DC-DC IND VBAT/VBATDC Converter IND and VDC pins VDC to external VIO VDRV radio 4.7, 0.1, and 0.01 uF Low Dropout VIORF 2.2, 0.1, and 0.01 uF bypass capacitors Regulator bypass capacitors required on (LDO0) required on VDC output VBAT/VBATDC input VLCD VSSDC VSS 10 uF capacitor required capacitors must be on the VLCD pin placed as close to the pins as possible. Figure 2.3. Connection Diagram with External Radio Device Figure 2.4 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck converter is used and the I/O are powered separately. 1 uF and 0.1 uF bypass SiM3L1xx Device capacitors required for each I/O power pin 0.56 uH inductor required between the DC-DC IND Converter IND and VDC pins 1.8-VBAT V VBAT/VBATDC VDC to external VDRV circuitry VIORF 4.7, 0.1, and 0.01 uF 1.8-VBAT V Low Dropout 2.2, 0.1, and 0.01 uF bypass capacitors Regulator bypass capacitors required on VIO (LDO0) required on VDC output VBAT/VBATDC input VLCD VSSDC VSS 10 uF capacitor required capacitors must be on the VLCD pin placed as close to the pins as possible. Figure 2.4. Connection Diagram with DC-DC Converter Used and I/O Powered Separately 7 Rev 1.1

SiM3L1xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all Tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Operating Supply Voltage on V 1.8 — 3.8 V BAT VBAT/VBATDC Operating Supply Voltage on VDC V 1.25 — 3.8 V DC Operating Supply Voltage on VDRV V 1.25 — 3.8 V DRV Operating Supply Voltage on VIO V 1.8 — V V IO BAT Operation Supply Voltage on VIORF V 1.8 — V V IORF BAT Operation Supply Voltage on VLCD V 1.8 — 3.8 V LCD System Clock Frequency (AHB) f 0 — 50 MHz AHB Peripheral Clock Frequency (APB) f 0 — 50 MHz APB Operating Ambient Temperature T –40 — +85 °C A Operating Junction Temperature T –40 — 105 °C J Note: All voltages with respect to V . SS Rev 1.1 8

SiM3L1xx Table 3.2. Power Consumption Parameter Symbol Test Condition Min Typ Max Unit Digital Core Supply Current Normal Mode1,2,3,4—Full speed I F = 49 MHz, — 17.5 18.9 mA BAT AHB with code executing from flash, F = 24.5 MHz APB peripheral clocks ON F = 20 MHz, — 6.7 7.2 mA AHB F = 10 MHz APB F = 2.5 MHz, — 1.15 1.4 mA AHB F = 1.25 MHz APB Normal Mode1,2,3,4—Full speed I F = 49 MHz, — 13.3 14.5 mA BAT AHB with code executing from flash, F = 24.5 MHz APB peripheral clocks OFF F = 20 MHz, — 5.4 5.9 mA AHB F = 10 MHz APB F = 2.5 MHz, — 980 1.2 µA AHB F = 1.25 MHz APB Normal Mode1,2,3,4—Full speed I F = 49 MHz, — 9.7 — mA BAT AHB with code executing from flash, F = 24.5 MHz APB LDOs powered by dc-dc at 1.9 V, V = 3.3 V BAT peripheral clocks OFF F = 49 MHz, — 8.65 — mA AHB F = 24.5 MHz APB V = 3.8 V BAT F = 20 MHz, — 4.15 — mA AHB F = 10 MHz APB V = 3.3 V BAT F = 20 MHz, — 3.9 — mA AHB F = 10 MHz APB V = 3.8 V BAT Notes: 1. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the BAT functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded I is included in all I PM8 VIO BAT production test measurements. 9 Rev 1.1

SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Power Mode 11,2,3,4—Full speed I F = 49 MHz, — 13.4 16.6 mA BAT AHB with code executing from RAM, F = 24.5 MHz APB peripheral clocks ON F = 20 MHz, — 4.7 — mA AHB F = 10 MHz APB F = 2.5 MHz, — 810 — µA AHB F = 1.25 MHz APB Power Mode 11,2,3,4—Full speed I F = 49 MHz, — 9.4 12.5 mA BAT AHB with code executing from RAM, F = 24.5 MHz APB peripheral clocks OFF F = 20 MHz, — 3.3 — mA AHB F = 10 MHz APB F = 2.5 MHz, — 630 — µA AHB F = 1.25 MHz APB Power Mode 11,2,3,4—Full speed I F = 49 MHz, — 7.05 — mA BAT AHB with code executing from RAM, F = 24.5 MHz APB LDOs powered by dc-dc at 1.9 V, V = 3.3 V BAT peripheral clocks OFF F = 49 MHz, — 6.3 — mA AHB F = 24.5 MHz APB V = 3.8 V BAT F = 20 MHz, — 2.75 — mA AHB F = 10 MHz APB V = 3.3 V BAT F = 20 MHz, — 2.6 — mA AHB F = 10 MHz APB V = 3.8 V BAT Power Mode 21,2,3,4,5—Core halted I F = 49 MHz, — 7.6 11.3 mA BAT AHB with peripheral clocks ON F = 24.5 MHz APB F = 20 MHz, — 2.75 — mA AHB F = 10 MHz APB F = 2.5 MHz, — 575 — µA AHB F = 1.25 MHz APB Notes: 1. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the BAT functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded I is included in all I PM8 VIO BAT production test measurements. Rev 1.1 10

SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Power Mode 21,2,3,4,5—Core halted I F = 49 MHz, — 4 7.2 mA BAT AHB with only Port I/O clocks on (wake F = 24.5 MHz APB from pin). F = 20 MHz, — 1.47 — mA AHB F = 10 MHz APB F = 2.5 MHz, — 430 — µA AHB F = 1.25 MHz APB Power Mode 31,2,6—Fast-Wake I V = 3.8 V — 320 530 µA BAT BAT Mode (PM3CLKEN = 1) V = 1.8 V — 225 — µA BAT Power Mode 41,2,4,6—Slower clock I F = F = 16 kHz, — 385 640 µA BAT AHB APB speed with code executing from V = 3.8 V BAT flash, peripheral clocks ON F = F = 16 kHz, — 330 — µA AHB APB V = 1.8 V BAT Power Mode 51,2,4,6—Slower clock I F = F = 16 kHz, — 320 490 µA BAT AHB APB speed with code executing from V = 3.8 V BAT RAM, peripheral clocks ON F = F = 16 kHz, — 275 — µA AHB APB V = 1.8 V BAT Power Mode 61,2,4,6—Core halted I F = F = 16 kHz, — 315 490 µA BAT AHB APB with peripheral clocks ON V = 3.8 V BAT F = F = 16 kHz, — 270 — µA AHB APB V = 1.8 V BAT Power Mode 81,2—Low Power I RTC Disabled, — 75 400 nA BAT Sleep, powered through VBAT, T = 25 °C A VIO, and VIORF at 2.4 V, 32kB of RTC w/ 16.4 kHz LFO, — 360 — nA retention RAM T = 25 °C A RTC w/ 32.768 kHz Crystal, — 670 — nA T = 25 °C A Notes: 1. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the BAT functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded I is included in all I PM8 VIO BAT production test measurements. 11 Rev 1.1

SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Power Mode 81,2—Low Power I RTC w/ 16.4 kHz LFO, — 180 — nA BAT Sleep, powered by the low power V = 2.4 V, T = 25 °C BAT A mode charge pump, 32kB of reten- RTC w/ 32.768 kHz Crystal, — 300 — nA tion RAM V = 2.4 V, T = 25 °C BAT A RTC w/ 16.4 kHz LFO, — 245 — nA V = 3.8 V, T = 25 °C BAT A RTC w/ 32.768 kHz Crystal, — 390 — nA V = 3.8 V, T = 25 °C BAT A Unloaded V and V Current10 I — 2 — nA IO IORF VIO Power Mode 8 Peripheral Currents UART0 I V = 3.8 V, T = 25 °C — 195 600 nA UART0 BAT A V = 2.4 V, T = 25 °C — 120 — nA BAT A LCD07, No segments active I V = 3.8 V, T = 25 °C — 495 660 nA LCD0 BAT A V = 2.4 V, T = 25 °C — 395 — nA BAT A LCD07, All (4 x 40) segments active I V = 3.8 V, T = 25 °C — 800 — nA LCD0 BAT A V = 2.4 V, T = 25 °C — 580 — nA BAT A Advanced Capture Counter I V = 2.4 V, T = 25 °C, — 1.11 — nA/Hz ACCTR BAT A (ACCTR0), LC Single-Ended CPMD = 01 Mode, Relative to Sampling Fre- V = 3.8 V, T = 25 °C, — 1.44 — nA/Hz quency9 BAT A CPMD = 01 V = 2.4 V, T = 25 °C, — 1.45 — nA/Hz BAT A CPMD = 10 V = 3.8 V, T = 25 °C, — 1.82 — nA/Hz BAT A CPMD = 10 V = 2.4 V, T = 25 °C, — 2.15 — nA/Hz BAT A CPMD = 11 V = 3.8 V, T = 25 °C, — 2.54 — nA/Hz BAT A CPMD = 11 Notes: 1. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the BAT functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded I is included in all I PM8 VIO BAT production test measurements. Rev 1.1 12

SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Advanced Capture Counter I V = 2.4 V, T = 25 °C, — 1.39 — nA/Hz ACCTR BAT A (ACCTR0), LC Dual or Quadrature CPMD = 01 Mode, Relative to Sampling Fre- V = 3.8 V, T = 25 °C, — 1.89 — nA/Hz quency9 BAT A CPMD = 01 V = 2.4 V, T = 25 °C, — 2.08 — nA/Hz BAT A CPMD = 10 V = 3.8 V, T = 25 °C, — 2.59 — nA/Hz BAT A CPMD = 10 V = 2.4 V, T = 25 °C, — 3.47 — nA/Hz BAT A CPMD = 11 V = 3.8 V, T = 25 °C, — 4.03 — nA/Hz BAT A CPMD = 11 Analog Peripheral Supply Currents PLL0 Oscillator (PLL0OSC) I Operating at 49 MHz — 1.4 1.6 mA PLLOSC Low-Power Oscillator (LPOSC0) I Operating at 20 MHz — 25 — µA LPOSC Operating at 2.5 MHz — 25 — µA Low-Frequency Oscillator I Operating at 16.4 kHz — 190 310 nA LFOSC (LFOSC0) External Oscillator (EXTOSC0) I FREQCN = 111 — 3.8 4.5 mA EXTOSC FREQCN = 110 — 840 960 µA FREQCN = 101 — 185 230 µA FREQCN = 100 — 65 80 µA FREQCN = 011 — 25 30 µA FREQCN = 010 — 10 13 µA FREQCN = 001 — 5 7 µA FREQCN = 000 — 3 5 µA Notes: 1. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the BAT functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded I is included in all I PM8 VIO BAT production test measurements. 13 Rev 1.1

SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit SARADC0 I Sampling at 1 Msps, Internal — 1.2 1.6 mA SARADC VREF used Sampling at 250 ksps, lowest — 390 540 µA power mode settings. Temperature Sensor I — 75 110 µA TSENSE Internal SAR Reference I Normal Power Mode — 680 — µA REFFS Normal Power Mode — 160 — µA VREF0 I — 80 — µA REFP Comparator 0 (CMP0), I CMPMD = 11 — 0.5 2 µA CMP Comparator 1 (CMP1) CMPMD = 10 — 3 8 µA CMPMD = 01 — 10 16 µA CMPMD = 00 — 25 42 µA IDAC08 I — 70 100 µA IDAC Voltage Supply Monitor (VMON0) I — 10 22 µA VMON Flash Current on VBAT Write Operation I — — 8 mA FLASH-W Erase Operation I — — 15 mA FLASH-E Notes: 1. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the BAT functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded I is included in all I PM8 VIO BAT production test measurements. Rev 1.1 14

SiM3L1xx Table 3.3. Power Mode Wake Up Times Parameter Symbol Test Condition Min Typ Max Unit Power Mode 2 or 6 Wake Time t 4 — 5 clocks PM2 Power Mode 3 Fast Wake Time t — 425 — µs PM3FW (using LFO as clock source) Power Mode 8 Wake Time t — 3.8 — µs PM8 Notes: 1. Wake times are specified as the time from the wake source to the execution phase of the first instruction following WFI. This includes latency to recognize the wake event and fetch the first instruction (assuming wait states = 0). Table 3.4. Reset and Supply Monitor Parameter Symbol Test Condition Min Typ Max Unit V High Supply Monitor Threshold V Early Warning — 2.20 — V BAT VBATMH (VBATHITHEN = 1) Reset 1.95 2.05 2.1 V V Low Supply Monitor Threshold V Early Warning — 1.85 — V BAT VBATML (VBATHITHEN = 0) Reset 1.70 1.75 1.77 V Power-On Reset (POR) Threshold V Rising Voltage on V — 1.4 — V POR BAT Falling Voltage on 0.8 1 1.3 V V BAT V Ramp Time t Time to V > 1.8 V 10 — 3000 µs BAT RMP BAT Reset Delay from POR t Relative to V > 3 — 100 ms POR BAT V POR Reset Delay from non-POR source t Time between release — 10 — µs RST of reset source and code execution RESET Low Time to Generate Reset t 50 — — ns RSTL Missing Clock Detector Response t F > 1 MHz — 0.5 1.5 ms MCD AHB Time (final rising edge to reset) Missing Clock Detector Trigger  F — 2.5 10 kHz MCD Frequency V Supply Monitor Turn-On Time t — 2 — µs BAT MON 15 Rev 1.1

SiM3L1xx Table 3.5. On-Chip Regulators Parameter Symbol Test Condition Min Typ Max Unit DC-DC Buck Converter Input Voltage Range V 1.8 — 3.8 V DCIN Input Supply to Output Voltage Differ- V 0.45 — — V DCREG ential (for regulation) Output Voltage Range V 1.25 — 3.8 V DCOUT Output Voltage Accuracy V — ±25 — mV DCACC Output Current I — — 90 mA DCOUT Inductor Value1 L 0.47 0.56 0.68 µH DC Inductor Current Rating I I < 50 mA 450 — — mA LDC load I > 50 mA 550 — — mA load Output Capacitor Value C 1 2.2 10 µF DCOUT Input Capacitor Value2 C — 4.7 — µF DCIN Load Regulation R — 0.03 — mV/mA load Maximum DC Load Current During I — — 5 mA DCMAX Startup Switching Clock Frequency F 1.9 2.9 3.8 MHz DCCLK Local Oscillator Frequency F 2.4 2.9 3.4 MHz DCOSC LDO Regulators Input Voltage Range3 V Sourced from VBAT 1.8 — 3.8 V LDOIN Sourced from VDC 1.9 — 3.8 V Output Voltage Range4 V 0.8 — 1.9 V LDO LDO Output Voltage Accuracy V — ±25 — mV LDOACC Output Settings in PM8 (All LDOs) V 1.8 V < V < 2.9 V 1.5 V LDO BAT 1.95 V < V < 3.5 V 1.8 V BAT 2.0 V < V < 3.8 V 1.9 V BAT Notes: 1. See reference manual for recommended inductors. 2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10 m (@ frequency > 1 MHz). 3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure that the LDO output voltage will remain at a valid level as long as V is at or above the specified minimum. LDOIN 4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO. When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO. 5. Output range represents the programmable output range, and does not reflect the minimum voltage under all conditions. Dropout when the input supply is close to the output setting is normal, and accounted for. 6. Analog peripheral specifications assume a 1.8 V output on the analog LDO. Rev 1.1 16

SiM3L1xx Table 3.5. On-Chip Regulators (Continued) Parameter Symbol Test Condition Min Typ Max Unit Memory LDO Output Setting5 V During Programming 1.8 — 1.9 V LDOMEM During Normal 1.5 — 1.9 V Operation Digital LDO Output Setting V F < 20 MHz 1.0 — 1.9 V LDODIG AHB F > 20 MHz 1.2 — 1.9 V AHB Analog LDO Output Setting During V 1.8 V LDOANA Normal Operation6 Notes: 1. See reference manual for recommended inductors. 2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10 m (@ frequency > 1 MHz). 3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure that the LDO output voltage will remain at a valid level as long as V is at or above the specified minimum. LDOIN 4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO. When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO. 5. Output range represents the programmable output range, and does not reflect the minimum voltage under all conditions. Dropout when the input supply is close to the output setting is normal, and accounted for. 6. Analog peripheral specifications assume a 1.8 V output on the analog LDO. 17 Rev 1.1

SiM3L1xx Table 3.6. Flash Memory Parameter Symbol Test Condition Min Typ Max Unit Write Time1 t One 16-bit Half Word 20 21 22 µs WRITE Erase Time1 t One Page 20 21 22 ms ERASE t Full Device 20 21 22 ms ERALL Endurance (Write/Erase Cycles) N 20k 100k — Cycles WE Retention2 t T = 25 °C, 1k Cycles 10 100 — Years RET A Notes: 1. Does not include sequencing time before and after the write/erase operation, which may take up to 35 µs. During sequential write operations, this extra time is only taken prior to the first write and after the last write. 2. Additional Data Retention Information is published in the Quarterly Quality and Reliability Report. Rev 1.1 18

SiM3L1xx Table 3.7. Internal Oscillators Parameter Symbol Test Condition Min Typ Max Unit Phase-Locked Loop (PLL0OSC) Calibrated Output Frequency f Full Temperature and 48.3 49 49.7 MHz PLL0OSC (Free-running output mode, Supply Range RANGE = 2) Power Supply Sensitivity PSS T = 25 °C, — 300 — ppm/V PLL0OSC A (Free-running output mode, Fout = 49 MHz RANGE = 2) Temperature Sensitivity TS V = 3.3 V, — 50 — ppm/°C PLL0OSC BAT (Free-running output mode, Fout = 49 MHz RANGE = 2) Adjustable Output Frequency f 23 — 50 MHz PLL0OSC Range Lock Time t f = 20 MHz, — 2.75 — µs PLL0LOCK REF f = 50 MHz PLL0OSC M=39, N=99, LOCKTH = 0 f = 2.5 MHz, — 9.45 — µs REF f = 50 MHz PLL0OSC M=19, N=399, LOCKTH = 0 f = 32.768 kHz, — 92 — µs REF f = 50 MHz PLL0OSC M=0, N=1524, LOCKTH = 0 Low Power Oscillator (LPOSC0) Oscillator Frequency f Full Temperature and 19 20 21 MHz LPOSC Supply Range Divided Oscillator Frequency f Full Temperature and 2.375 2.5 2.625 MHz LPOSCD Supply Range Power Supply Sensitivity PSS T = 25 °C — 0.5 — %/V LPOSC A Temperature Sensitivity TS V = 3.3 V — 55 — ppm/°C LPOSC BAT Low Frequency Oscillator (LFOSC0) Oscillator Frequency f Full Temperature and 13.4 16.4 19.7 kHz LFOSC Supply Range T = 25 °C, 15.8 16.4 17.3 kHz A V = 3.3 V BAT Power Supply Sensitivity PSS T = 25 °C — 2.4 — %/V LFOSC A Temperature Sensitivity TS V = 3.3 V — 0.2 — %/°C LFOSC BAT 19 Rev 1.1

SiM3L1xx Table 3.7. Internal Oscillators (Continued) Parameter Symbol Test Condition Min Typ Max Unit RTC0 Oscillator (RTC0OSC) Missing Clock Detector Trigger f — 8 15 kHz RTCMCD Frequency RTC External Input CMOS Clock f 0 — 40 kHz RTCEXTCLK Frequency RTC Robust Duty Cycle Range DC 25 — 55 % RTC Table 3.8. External Oscillator Parameter Symbol Test Condition Min Typ Max Unit External Input CMOS Clock f 0* — 50 MHz CMOS Frequency External Crystal Frequency f 0.01 — 25 MHz XTAL External Input CMOS Clock High Time t 9 — — ns CMOSH External Input CMOS Clock Low Time t 9 — — ns CMOSL Low Power Mode Charge Pump  V 2.4 — 3.8 V BAT Supply Range (input from V ) BAT *Note: Minimum of 10 kHz when debugging. Rev 1.1 20

SiM3L1xx Table 3.9. SAR ADC Parameter Symbol Test Condition Min Typ Max Unit Resolution N 12 Bit Mode 12 Bits bits 10 Bit Mode 10 Bits Supply Voltage Requirements V High Speed Mode 2.2 — 3.8 V ADC (VBAT) Low Power Mode 1.8 — 3.8 V Throughput Rate f 12 Bit Mode — — 250 ksps S (High Speed Mode) 10 Bit Mode — — 1 Msps Throughput Rate f 12 Bit Mode — — 62.5 ksps S (Low Power Mode) 10 Bit Mode — — 250 ksps Tracking Time t High Speed Mode 230 — — ns TRK Low Power Mode 450 — — ns SAR Clock Frequency f High Speed Mode — — 16.24 MHz SAR Low Power Mode — — 4 MHz Conversion Time t 10-Bit Conversion, 762.5 ns CNV SAR Clock = 16 MHz, APB Clock = 40 MHz Sample/Hold Capacitor C Gain = 1 — 5 — pF SAR Gain = 0.5 — 2.5 — pF Input Pin Capacitance C High Quality Inputs — 18 — pF IN Normal Inputs — 20 — pF Input Mux Impedance R High Quality Inputs — 300 —  MUX Normal Inputs — 550 —  Voltage Reference Range V 1 — V V REF BAT Input Voltage Range* V Gain = 1 0 — V V IN REF Gain = 0.5 0 — 2xV V REF Power Supply Rejection Ratio PSRR — 70 — dB ADC DC Performance Integral Nonlinearity INL 12 Bit Mode — ±1 ±1.9 LSB 10 Bit Mode — ±0.2 ±0.5 LSB Differential Nonlinearity  DNL 12 Bit Mode –1 ±0.7 1.8 LSB (Guaranteed Monotonic) 10 Bit Mode — ±0.2 ±0.5 LSB Offset Error (using VREFGND) E 12 Bit Mode, VREF = 2.4 V –2 0 2 LSB OFF 10 Bit Mode, VREF = 2.4 V –1 0 1 LSB 21 Rev 1.1

SiM3L1xx Table 3.9. SAR ADC (Continued) Parameter Symbol Test Condition Min Typ Max Unit Offset Temperature Coefficient TC — 0.004 — LSB/°C OFF Slope Error E –0.07 –0.02 0.02 % M Dynamic Performance (10 kHz Sine Wave Input 1dB below full scale, Max throughput) Signal-to-Noise SNR 12 Bit Mode 62 66 — dB 10 Bit Mode 58 60 — dB Signal-to-Noise Plus Distortion SNDR 12 Bit Mode 62 66 — dB 10 Bit Mode 58 60 — dB Total Harmonic Distortion (Up to THD 12 Bit Mode — 78 — dB 5th Harmonic) 10 Bit Mode — 77 — dB Spurious-Free Dynamic Range SFDR 12 Bit Mode — –79 — dB 10 Bit Mode — –74 — dB *Note: Absolute input pin voltage is limited by the lower of the supply at VBAT and VIO. Rev 1.1 22

SiM3L1xx Table 3.10. IDAC Parameter Symbol Test Condition Min Typ Max Unit Static Performance Resolution N 10 Bits bits Integral Nonlinearity INL — ±0.5 ±2 LSB Differential Nonlinearity (Guaranteed DNL — ±0.5 ±1 LSB Monotonic) Output Compliance Range V — — V – V OCR BAT 1.0 Full Scale Output Current I 2 mA Range, 1.98 2.046 2.1 mA OUT T = 25 °C A 1 mA Range, 0.99 1.023 1.05 mA T = 25 °C A 0.5 mA Range, 491 511.5 525 µA T = 25 °C A Offset Error E — 250 — nA OFF Full Scale Error Tempco TC 2 mA Range — 100 — ppm/°C FS VBAT Power Supply Rejection Ratio 2 mA Range — –220 — ppm/V Test Load Impedance (to V ) R — 1 — k SS TEST Dynamic Performance Output Settling Time to 1/2 LSB min output to max — 1.2 — µs output Startup Time — 3 — µs 23 Rev 1.1

SiM3L1xx Table 3.11. ACCTR (Advanced Capture Counter) Parameter Symbol Test Condition Min Typ Max Unit LC Comparator Response Time, t +100 mV Differential — 100 — ns RESP0 CMPMD = 11 –100 mV Differential — 150 — ns (Highest Speed) LC Comparator Response Time, t +100 mV Differential — 1.4 — µs RESP3 CMPMD = 00 –100 mV Differential — 3.5 — µs (Lowest Power) LC Comparator Positive Hysteresis HYS CMPHYP = 00 — 0.37 — mV CP+ Mode 0 (CPMD = 11) CMPHYP = 01 — 7.9 — mV CMPHYP = 10 — 16.7 — mV CMPHYP = 11 — 32.8 — mV LC Comparator Negative Hysteresis HYS CMPHYN = 00 — 0.37 — mV CP- Mode 0 (CPMD = 11) CMPHYN = 01 — –7.9 — mV CMPHYN = 10 — –16.1 — mV CMPHYN = 11 — –32.7 — mV LC Comparator Positive Hysteresis HYS CMPHYP = 00 — 0.47 — mV CP+ Mode 1 (CPMD = 10) CMPHYP = 01 — 5.85 — mV CMPHYP = 10 — 12 — mV CMPHYP = 11 — 24.4 — mV LC Comparator Negative Hysteresis HYS CMPHYN = 00 — 0.47 — mV CP- Mode 1 (CPMD = 10) CMPHYN = 01 — –6.0 — mV CMPHYN = 10 — –12.1 — mV CMPHYN = 11 — –24.6 — mV LC Comparator Positive Hysteresis HYS CMPHYP = 00 — 0.66 — mV CP+ Mode 2 (CPMD = 01) CMPHYP = 01 — 4.55 — mV CMPHYP = 10 — 9.3 — mV CMPHYP = 11 — 19 — mV LC Comparator Negative Hysteresis HYS CMPHYN = 00 — 0.6 — mV CP- Mode 2 (CPMD = 01) CMPHYN = 01 — –4.5 — mV CMPHYN = 10 — –9.5 — mV CMPHYN = 11 — –19 — mV Rev 1.1 24

SiM3L1xx Table 3.11. ACCTR (Advanced Capture Counter) (Continued) Parameter Symbol Test Condition Min Typ Max Unit LC Comparator Positive Hysteresis HYS CMPHYP = 00 — 1.37 — mV CP+ Mode 3 (CPMD = 00) CMPHYP = 01 — 3.8 — mV CMPHYP = 10 — 7.8 — mV CMPHYP = 11 — 15.6 — mV LC Comparator Negative Hysteresis HYS CMPHYN = 00 — 1.37 — mV CP- Mode 3 (CPMD = 00) CMPHYN = 01 — –3.9 — mV CMPHYN = 10 — –7.9 — mV CMPHYN = 11 — –16 — mV LC Comparator Input Range V –0.25 — V + V IN BAT (ACCTR0_LCIN pin) 0.25 LC Comparator Common-Mode CMRR — 75 — dB CP Rejection Ratio LC Comparator Power Supply Rejec- PSRR — 72 — dB CP tion Ratio LC Comparator Input Offset Voltage V T = 25 °C –10 0 10 mV OFF A LC Comparator Input Offset Tempco TC — 3.5 — µV/°C OFF Reference DAC Offset Error DAC –1 — 1 LSB EOFF Reference DAC Full Scale Output DAC Low Range — V /8 — V FS IO High Range — V — V IO Reference DAC Step Size DAC Low Range (48 steps) — V /384 — V LSB IO High Range (64 steps) — V /64 — V IO LC Oscillator Period T — 25 — ns LCOSC LC Bias Output Impedance R 10 µA Load — 1 — k LCBIAS LC Bias Drive Strength I — — 2 mA LCBIAS Pull-Up Resistor Tolerance R PUVAL[4:2] = 0 to 6 -15 — 15 % TOL PUVAL[4:2] = 7 -10 — 10 % 25 Rev 1.1

SiM3L1xx Table 3.12. Voltage Reference Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Internal Fast Settling Reference Output Voltage V –40 to +85 °C, 1.6 1.65 1.7 V REFFS V = 1.8–3.8 V BAT Temperature Coefficient TC — 50 — ppm/°C REFFS Turn-on Time t — — 1.5 µs REFFS Power Supply Rejection PSRR — 400 — ppm/V REFFS Internal Precision Reference V VREF2X = 0 1.8 — 3.8 V BAT Valid Supply Range VREF2X = 1 2.7 — 3.8 V V 25 °C ambient, 1.17 1.2 1.23 V REFP VREF2X = 0 Output Voltage 25 °C ambient, 2.35 2.4 2.45 V VREF2X = 1 Short-Circuit Current I — — 10 mA SC Temperature Coefficient TC — 35 — ppm/°C VREFP LR Load = 0 to 200 µA to — 4.5 — ppm/µA Load Regulation VREFP VREFGND C Load = 0 to 200 µA to 0.1 — — µF Load Capacitor VREFP VREFGND t 4.7 µF tantalum, 0.1 µF — 3.8 — ms VREFPON Turn-on Time ceramic bypass 0.1 µF ceramic bypass — 200 — µs Power Supply Rejection PSRR VREF2X = 0 — 320 — ppm/V VREFP VREF2X = 1 — 560 — ppm/V External Reference I Sample Rate = 250 ksps; — 5.25 — µA Input Current EXTREF VREF = 3.0 V Table 3.13. Temperature Sensor Parameter Symbol Test Condition Min Typ Max Unit Offset V T = 0 °C — 760 — mV OFF A Offset Error* E T = 0 °C — ±14 — mV OFF A Slope M — 2.77 — mV/°C Slope Error* E — ±25 — µV/°C M Linearity — 1 — °C Turn-on Time — 1.8 — µs *Note: Absolute input pin voltage is limited by the lower of the supply at VBAT and VIO. Rev 1.1 26

SiM3L1xx Table 3.14. Comparator Parameter Symbol Test Condition Min Typ Max Unit Response Time, CMPMD = 00 t +100 mV Differential — 100 — ns RESP0 (Highest Speed) –100 mV Differential — 150 — ns Response Time, CMPMD = 11 t +100 mV Differential — 1.4 — µs RESP3 (Lowest Power) –100 mV Differential — 3.5 — µs Positive Hysteresis HYS CMPHYP = 00 — 0.37 — mV CP+ Mode 0 (CPMD = 00) CMPHYP = 01 — 7.9 — mV CMPHYP = 10 — 16.7 — mV CMPHYP = 11 — 32.8 — mV Negative Hysteresis HYS CMPHYN = 00 — 0.37 — mV CP- Mode 0 (CPMD = 00) CMPHYN = 01 — –7.9 — mV CMPHYN = 10 — –16.1 — mV CMPHYN = 11 — –32.7 — mV Positive Hysteresis HYS CMPHYP = 00 — 0.47 — mV CP+ Mode 1 (CPMD = 01) CMPHYP = 01 — 5.85 — mV CMPHYP = 10 — 12 — mV CMPHYP = 11 — 24.4 — mV Negative Hysteresis HYS CMPHYN = 00 — 0.47 — mV CP- Mode 1 (CPMD = 01) CMPHYN = 01 — –6.0 — mV CMPHYN = 10 — –12.1 — mV CMPHYN = 11 — –24.6 — mV Positive Hysteresis HYS CMPHYP = 00 — 0.66 — mV CP+ Mode 2 (CPMD = 10) CMPHYP = 01 — 4.55 — mV CMPHYP = 10 — 9.3 — mV CMPHYP = 11 — 19 — mV Negative Hysteresis HYS CMPHYN = 00 — 0.6 — mV CP- Mode 2 (CPMD = 10) CMPHYN = 01 — –4.5 — mV CMPHYN = 10 — –9.5 — mV CMPHYN = 11 — –19 — mV 27 Rev 1.1

SiM3L1xx Table 3.14. Comparator (Continued) Parameter Symbol Test Condition Min Typ Max Unit Positive Hysteresis HYS CMPHYP = 00 — 1.37 — mV CP+ Mode 3 (CPMD = 11) CMPHYP = 01 — 3.8 — mV CMPHYP = 10 — 7.8 — mV CMPHYP = 11 — 15.6 — mV Negative Hysteresis HYS CMPHYN = 00 — 1.37 — mV CP- Mode 3 (CPMD = 11) CMPHYN = 01 — –3.9 — mV CMPHYN = 10 — –7.9 — mV CMPHYN = 11 — –16 — mV Input Range (CP+ or CP–) V –0.25 — V + V IN BAT 0.25 Input Pin Capacitance C — 7.5 — pF CP Common-Mode Rejection Ratio CMRR — 75 — dB CP Power Supply Rejection Ratio PSRR — 72 — dB CP Input Offset Voltage V T = 25 °C –10 0 10 mV OFF A Input Offset Tempco TC — 3.5 — µV/°C OFF Reference DAC Resolution N 6 bits Bits Table 3.15. LCD0 Parameter Symbol Test Condition Min Typ Max Unit Charge Pump Output Voltage Error V — ±50 — mV CPERR LCD Clock Frequency F 16 — 33 kHz LCD Rev 1.1 28

SiM3L1xx Table 3.16. Port I/O Parameter Symbol Test Condition Min Typ Max Unit Output High Voltage (PB0, PB1, V Low Drive, I = –1 mA V – 0.7 — — V OH OH IO PB3, or PB4) Low Drive, I = –10 µA V – 0.1 — — V OH IO High Drive, I = –3 mA V – 0.7 — — V OH IO High Drive, I = –10 µA V – 0.1 — — V OH IO Output High Voltage (PB2) V Low Drive, I = –1 mA V – 0.7 — — V OH OH IORF Low Drive, I = –10 µA V – 0.1 — — V OH IORF High Drive, I = –3 mA V – 0.7 — — V OH IORF High Drive, I = –10 µA V – 0.1 — — V OH IORF Output Low Voltage (any Port I/O V Low Drive, I = 1.4 mA — — 0.6 V OL OL pin or RESET1) Low Drive, I = 10 µA — — 0.1 V OL High Drive, I = 8.5 mA — — 0.6 V OL High Drive, I = 10 µA — — 0.1 V OL Input High Voltage (PB0, PB1, V V – 0.6 — — V IH IO PB3, PB4 or RESET) Input High Voltage (PB2) V V – 0.6 — — V IH IORF Input Low Voltage any Port I/O pin V — — 0.6 V IL or RESET) Weak Pull-Up Current2 (per pin) I V or V = 1.8 -6 -3.5 -2 µA PU IO IORF V or V = 3.8 -32 -20 -10 µA IO IORF Input Leakage  I 0 < V < V or V -1 — 1 µA LK IN IO IORF (Pullups off or Analog) Notes: 1. Specifications for RESET V adhere to the low drive setting. OL 2. On the SiM3L1x6 and SiM3L1x4 devices, the SWV pin will have double the weak pull-up current specified whenever the device is held in reset. 29 Rev 1.1

SiM3L1xx 3.2. Thermal Conditions Table 3.17. Thermal Conditions Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance*  TQFP-80 Packages — 40 — °C/W JA QFN-64 Packages — 25 — °C/W TQFP-64 Packages — 30 — °C/W QFN-40 Packages — 30 — °C/W *Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad. Rev 1.1 30

SiM3L1xx 3.3. Absolute Maximum Ratings Stresses above those listed under Table 3.18 may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3.18. Absolute Maximum Ratings Parameter Symbol Test Condition Min Max Unit Ambient Temperature Under Bias T –55 125 °C BIAS Storage Temperature T –65 150 °C STG Voltage on VBAT/VBATDC V V –0.3 4.2 V BAT SS Voltage on VDC V V –0.3 4.2 V DC SSDC Voltage on VDRV V V –0.3 4.2 V DRV SS Voltage on VIO V V –0.3 4.2 V IO SS Voltage on VIORF V V –0.3 4.2 V IORF SS Voltage on VLCD V V –0.3 4.2 V LCD SS Voltage on I/O (PB0, PB1, PB3, PB4) or V V > 3.3 V V –0.3 5.8 V IN IO SS RESET1 V < 3.3 V V –0.3 V +2.5 V IO SS IO Voltage on PB2 I/O Pins1 V V > 3.3 V V –0.3 5.8 V IN IORF SS V < 3.3 V V –0.3 V +2.5 V IORF SS IORF Total Current Sunk into Supply Pins I VBAT/VBATDC, VIO, — 400 mA SUPP VIORF, VDRV, VDC, VLCD Total Current Sourced out of  I V V 400 — mA VSS SS, SSDC Ground Pins2 Current Sourced or Sunk by any I/O Pin I All I/O and RESET –100 100 mA PIO Power Dissipation at T = 85 °C P TQFP-80 Packages — 500 mW A D QFN-64 Packages — 800 mW TQFP-64 Packages — 650 mW QFN-40 Packages — 650 mW Notes: 1. Exceeding the minimum V voltage may cause current to flow through adjacent device pins. IO 2. VSS and VSSDC provide separate return current paths for device supplies, but are not isolated. They must always be connected to the same potential on board. 31 Rev 1.1

SiM3L1xx 4. Precision32™ SiM3L1xx System Overview The SiM3L1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 5.1 for specific product feature selection and part ordering numbers. Core: 32-bit ARM Cortex-M3 CPU. 50 MHz maximum operating frequency. Branch target cache and prefetch buffers to minimize wait states. Memory: 32–256 kB flash; in-system programmable, 8–32 kB SRAM configurable to retention mode in 4 kB blocks. Blocks configured to retention mode preserve state in the low power PM8 mode. Power: Three adjustable low drop-out (LDO) regulators. DC-DC buck converter allows dynamic voltage scaling for maximum efficiency (250 mW output). Power-on reset circuit and brownout detectors. Power Management Unit (PMU). Specialized charge pump reduces power consumption in low power modes. Process/Voltage/Temperature (PVT) Monitor. Register state retention in lowest power mode. I/O: Up to 62 contiguous 5 V tolerant I/O pins and one flexible peripheral crossbar. Clock Sources: Internal oscillator with PLL: 23–50 MHz with ± 1.5% accuracy in free-running mode. Low-power internal oscillator: 20 MHz. Low-frequency internal oscillator: 16.4 kHz. External RTC crystal oscillator: 32.768 kHz. External oscillator: Crystal, RC, C, CMOS clock. Integrated LCD Controller (4x40). Data Peripherals: 10-Channel DMA Controller. 3 x Data Transfer Managers. 128/192/256-bit Hardware AES Encryption. CRC with programmable 16-bit polynomial, one 32-bit polynomial, and bus snooping capability. Encoder / Decoder. Timers/Counters: 3 x 32-bit Timers. 1 x Enhanced Programmable Counter Array (EPCA). Real Time Clock (RTC0). Low Power Timer. Watchdog Timer. Low Power Mode Advanced Capture Counter (ACCTR). Communications Peripherals: 1 x USART with IrDA and ISO7816 SmartCard support. 1 x UART that operates in low power mode (PM8). 2 x SPIs. 1 x I2C. Analog: 1 x 12-Bit Analog-to-Digital Converter (SARADC). 1 x 10-Bit Digital-to-Analog Converter (IDAC). 2 x Low-Current Comparators (CMP). On-Chip Debugging With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillators, the SiM3L1xx devices are truly stand-alone system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non- volatile data storage and allowing field upgrades of the firmware. User firmware has complete control of all Rev 1.1 32

SiM3L1xx peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings. The on-chip debugging interface (SWJ-DP) allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging. Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (–40 to +85 °C). The SiM3L1xx devices are available in 40-pin or 64-pin QFN and 64-pin or 80-pin TQFP packages. All package options are lead-free and RoHS compliant. See Table 5.1 for ordering information. A block diagram is included in Figure 4.1. Watchdog Debug / Timer Programming Core (WDTIMER0) Hardware ARM Cortex M3 B B Analog Power On Reset / AH AP PMU SARADC0 Memory IDAC0 Voltage Supply Monitor (VMON0) 32/64/128/256 kB Flash Comparator 0 Comparator 1 8/16/32 kB configurable retention RAM Power I/O Crossbar Analog Memory Digital LDO0 LDO LDO LDO DMA Standard 5 V Tolerant I/O pins DC-DC Buck Converter (DCDC0) 10-Channel Controller Power Management Unit (PMU) Peripheral Crossbar Digital Low Power Mode Charge Pump USART0 UART0 Data Transfer Manager SPI0 SPI1 DTM0 DTM1 DTM2 I2C0 Clocking AES0 Real-Time Clock Oscillator (RTC0OSC) ECRC0 Low Frequency Oscillator (LFOSC0) ENCDEC0 Low Power Oscillator (LPOSC0) EPCA0 Clock Control External Oscillator Control (EXTOSC0) Timer 0 Timer 1 Timer 2 Phase-Locked Loop (PLL0OSC) Low Power Timer (LPTIMER0) Peripheral Clock Control (CLKCTRL) Advanced Capture Counter (ACCTR0) 4x40 Segment LCD Controller DMA support available for these peripherals Figure 4.1. Precision32™ SiM3L1xx Family Block Diagram 33 Rev 1.1

SiM3L1xx 4.1. Power The SiM3L1xx devices include a dc-dc buck converter that can take an input from 1.8–3.8 V and create an output from 1.25–3.8 V. In addition, SiM3L1xx devices include three low dropout regulators as part of the LDO0 module: one LDO powers the analog subsystems, one LDO powers the flash and SRAM memory at 1.8 V, and one LDO powers the digital and core circuitry. Each of these regulators can be independently powered from the dc-dc converter or directly from the battery voltage, and their outputs are adjustable to conserve system power. SiM3L1xx devices also include a low power charge pump in the PMU module for use in low power modes (PM8) to further reduce the power consumption of the device. Figure 4.2 shows the power system configuration of these devices. SiM3L1xx Device DC-DC IND VBAT/VBATDC Converter VDC VDRV to digital and core VSSDC Digital LDO VSS to memory LDO0 Memory LDO to analog Analog LDO to PM8 Low Power peripherals Mode Charge Pump Figure 4.2. SiM3L1xx Power 4.1.1. DC-DC Buck Converter (DCDC0) SiM3L1xx devices include an on-chip step-down dc-dc converter to efficiently utilize the energy stored in the battery, thus extending the operational life time. The dc-dc converter is a switching buck converter with a programmable output voltage that should be at least 0.45 V lower than the input battery voltage; if this criteria is not met and the converter can no longer operate, the output of the dc-dc converter automatically connects to the battery. The dc-dc converter can supply up to 100 mA and can be used to power the MCU and/or external devices in the system. The dc-dc converter has a built in voltage reference and oscillator and will automatically limit or turn off the switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a secondary power source (when available) in order to preserve battery life. When enabled, the dc-dc converter can source current into the output capacitor, but cannot sink current. The dc-dc converter includes the following features: Efficiently utilizes the energy stored in a battery, extending its operational lifetime. Input range: 1.8 to 3.8 V. Output range: 1.25 to 3.8 V in 50 mV (1.25–1.8 V) or 100 mV (1.8–3.8 V) steps. Supplies up to 100 mA. Includes a voltage reference and an oscillator. Rev 1.1 34

SiM3L1xx Supports synchronizing the regulator switching with the system clock. Automatically limits the peak inductor current if the load current rises beyond a safe limit. Automatically goes into bypass mode if the battery voltage cannot provide sufficient headroom. Sources current, but cannot sink current. 4.1.2. Three Low Dropout LDO Regulators (LDO0) The SiM3L1xx devices include one LDO0 module with three low dropout regulators. Each of these regulators have independent switches to select the battery voltage or the output of the dc-dc converter as the input to each LDO, and an adjustable output voltage. The LDOs consume little power and provide flexibility in choosing a power supply for the system. Each regulator can be independently adjusted between 0.8 and 1.9 V output. 4.1.3. Voltage Supply Monitor (VMON0) The SiM3L1xx devices include a voltage supply monitor that can monitor the main supply voltage. This module includes the following features: Main supply “VBAT Low” (VBAT below the early warning threshold) notification. Holds the device in reset if the main VBAT supply drops below the VBAT Reset threshold. The voltage supply monitor allows devices to function in known, safe operating conditions without the need for external hardware. 4.1.4. Power Management Unit (PMU) The Power Management Unit on the SiM3L1xx manages the power systems of the device. It manages the power- up sequence during power on and the wake up sources for PM8. On power-up, the PMU ensures the core voltages are a proper value before core instruction execution begins. The VDRV pin powers external circuitry from either the VBAT battery input voltage or the output of the dc-dc converter on VDC. The PMU includes an internal switch to select one of these sources for the VDRV pin. The PMU has a specialized VBAT-divided-by-2 charge pump that can power some internal modules while in PM8 to save power. The PMU module includes the following features: Provides the enable or disable for the analog power system, including the three LDO regulators. Up to 14 pin wake inputs can wake the device from Power Mode 8. The Low Power Timer, RTC0 (alarms and oscillator failure), Comparator 0, Advanced Capture Counter, LCD0 VBAT monitor, UART0, low power mode charge pump failure, and the RESET pin can also serve as wake sources for Power Mode 8. Controls which 4 kB RAM blocks are retained while in Power Mode 8. Provides a PMU_Asleep signal to a pin as an indicator that the device is in PM8. Specialized charge pump to reduce power consumption in PM8. Provides control for the internal switch between VBAT and VDC to power the VDRV pin for external circuitry. 4.1.5. Device Power Modes The SiM3L1xx devices feature seven low power modes in addition to normal operating mode. Several peripherals provide wake up sources for these low power modes, including the Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator failure notification), Comparator 0 (CMP0), Advanced Capture Counter (ACCTR0), LCD VBAT monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake. In addition, all peripherals can have their clocks disabled to reduce power consumption whenever a peripheral is not being used using the clock control (CLKCTRL) registers. 4.1.5.1. Normal Mode (Power Mode 0) and Power Mode 4 Normal Mode and Power Mode 4 are fully operational modes with code executing from flash memory. PM4 is the same as Normal Mode, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs. 35 Rev 1.1

SiM3L1xx 4.1.5.2. Power Mode 1 and Power Mode 5 Power Mode 1 and Power Mode 5 are fully operational modes with code executing from RAM. PM5 is the same as PM1, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs. Compared with the corresponding flash operational mode (Normal or PM4), the active power consumption of the device in these modes is reduced. Additionally, at higher speeds in PM1, the core throughput can also be increased because RAMdoesnot require additional wait states that reduce the instruction fetch speed. 4.1.5.3. Power Mode 2 and Power Mode 6 In Power Mode 2 and Power Mode 6, the core halts and the peripherals continue to run at the selected clock speed. PM6 is the same as PM2, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs. To place the device in PM2 or PM6, the core should execute a wait-for-interrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM2 or PM6 must be of a sufficient priority to be recognized by the core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Syncronization Barrier) operation prior to the WFI to ensure all bus accesses complete. When operating from the LFOSC0, PM6 can achieve similar power consumption to PM3, but with faster wake times and the ability to wake on any interrupt. 4.1.5.4. Power Mode 3 In Power Mode 3 the core and peripheral clocks are halted. The available sources to wake from PM3 are controlled by the Power Management Unit (PMU). A special Fast Wake option allows the core to wake faster by keeping the LFOSC0 or RTC0 clock active. Because the current consumption of these blocks is minimal, it is recommended to use the fast wake option. Before entering PM3, the DMA controller should be disabled, and the desired wake source(s) should be configured in the PMU. The SLEEPDEEP bit in the ARM System Control Register should be set, and the PMSEL bit in the CLKCTRL0_CONFIG register should be cleared to indicate that PM3 is the desired power mode. For fast wake, the core clocks (AHB and APB) should be configured to run from the LPOSC, and the PM3 Fast wake option and clock source should be selected in the PM3CN register. The device will enter PM3 on a WFI or WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must be of a sufficient priority to be recognized by the core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete. 4.1.5.5. Power Mode 8 In Power Mode 8, the core and most peripherals are completely powered down, but all registers and selected RAM blocks retain their state. The LDO regulators are disabled, so all active circuitry operates directly from VBAT. Alternatively, the PMU has a specialized VBAT-divided-by-2 charge pump that can power some internal modules while in PM8 to save power. The fully operational functions in this mode are: LPTIMER0 , RTC0, UART0 running from RTC0TCLK, PMU Pin Wake, the advanced capture counter, and the LCD controller. This mode provides the lowest power consumption for the device, but requires an appropriate wake up source or reset to exit. The available wake up or reset sources to wake from PM8 are controlled by the Power Management Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake. The available reset sources are: RESET pin, VBAT supply monitor, Comparator 0, Comparator 1, low power mode charge pump failure, RTC0 oscillator failure, or a PMU wake event. Before entering PM8, the desired wake source(s) should be configured in the PMU. The SLEEPDEEP bit in the ARM System Control Register should be set, and the PMSEL bit in the CLKCTRL0_CONFIG register should be set to indicate that PM8 is the desired power mode. The device will enter PM8 on a WFI or WFE instruction, and remain in PM8 until a reset configured by the PMU occurs. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete. Rev 1.1 36

SiM3L1xx 4.1.5.6. Power Mode Summary The power modes described above are summarized in Table 4.1. Table 3.2 and Table 3.3 provide more information on the power consumption and wake up times for each mode. Table 4.1. SiM3L1xx Power Modes Mode Description Notes  Core operating at full speed  Full device operation Normal  Code executing from flash  Core operating at full speed  Full device operation  Code executing from RAM  Higher CPU bandwidth than PM0 (RAM Power Mode 1 (PM1) can operate with zero wait states at any frequency)  Core halted  Fast wakeup from any interrupt source Power Mode 2 (PM2)  AHB, APB and all peripherals operational at full speed  All clocks to core and peripherals  Wake on any wake source or reset stopped source defined in the PMU Power Mode 3 (PM3)  Faster wake enabled by keeping LFOSC0 or RTC0TCLK active  Core operating at low speed  Same capabilities as PM0, operating at  Code executing from flash lower speed Power Mode 4 (PM4)  Lower clock speed enables lower LDO output settings to save power  Core operating at low speed  Same capabilities as PM1, operating at  Code executing from RAM lower speed Power Mode 5 (PM5)  Lower clock speed enables lower LDO output settings to save power  Core halted  Same capabilities as PM2, operating at  AHB, APB and all peripherals lower speed operational at low speed  Lower clock speed enables lower LDO Power Mode 6 (PM6) output settings to save power  When running from LFOSC0, power is similar to PM3, but the device wakes much faster  Low power sleep  Lowest power consumption  LDO regulators are disabled and all  Wake on any wake source or reset active circuitry operates directly from source defined in the PMU VBAT Power Mode 8 (PM8)  The following functions are available: ACCTR0, RTC0, UART0 running from RTC0TCLK, LPTIMER0, port match, and the LCD controller  Register and RAM state retention 37 Rev 1.1

SiM3L1xx 4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0) The Process/Voltage/Temperature monitor consists of two modules (TIMER2 and PVTOSC0) designed to monitor the digital circuit performance of the SiM3L1xx device. The PVT oscillator (PVTOSC0) consists of two oscillators, one operating from the memory LDO and one operating from the digital LDO. These oscillators have two independent speed options and provide the clocks for two 16-bit timers in the TIMER2 module using the EX input. By monitoring the resulting counts of the TIMER2 timers, firmware can monitor the current device performance and increase the scalable LDO regulator (LDO0) output voltages as needed or decrease the output voltages to save power. The PVT monitor has the following features: Two separate oscillators and timers for the memory and digital logic voltage domains. Two oscillator output divider settings. Provides a method for monitoring digital performance to allow firmware to adjust the scalable LDO regulator output voltages to the lowest level possible, saving power. Rev 1.1 38

SiM3L1xx 4.2. I/O 4.2.1. General Features The SiM3L1xx ports have the following features: 5 V tolerant. Push-pull or open-drain output modes to the VIO or VIORF voltage level. Analog or digital modes. Option for high or low output drive strength. Port Match allows the device to recognize a change on a port pin value. Internal pull-up resistors are enabled or disabled on a port-by-port basis. Two external interrupts with up to 16 inputs each provide monitoring capability for external signals. Internal Pulse Generator Timer (PB0 only) to generate simple square waves and pulses. 4.2.2. Crossbar The SiM3L1xx devices have one crossbar with the following features: Flexible peripheral assignment to port pins. Pins can be individually skipped to move peripherals as needed for design or layout considerations. The crossbar has a fixed priority for each I/O function and assigns these functions to the port pins. When a digital resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. Additionally, the crossbar will skip port pins whose associated bits in the PBSKIPEN registers are set. This provides flexibility when designing a system: pins involved with sensitive analog measurements can be moved away from digital I/O, and peripherals can be moved around the chip as needed to ease layout constraints. 39 Rev 1.1

SiM3L1xx 4.3. Clocking The SiM3L1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is derived from one of seven sources: the RTC timer clock (RTC0TCLK), the Low Frequency Oscillator, the Low Power Oscillator, the divided Low Power Oscillator, the External Oscillator, the PLL0 Oscillator, and the VIORFCLK pin input. In addition, a divider for the AHB clock provides flexible clock options for the device. The APB clock services data peripherals and is synchronized with the AHB clock. The APB clock can be equal to the AHB clock or set to the AHB clock divided by two. The Clock Control module on SiM3L1xx devices allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. Most peripherals have clocks off by default after a power-on reset. Clock Control RAM RTC0TCLK DMA LFOSC0 AHB clock Flash LPOSC0 DTM0 AHB Clock Divider Flash Controller Registers External PBCFG and Oscillator PB0/1/2/3/4 PLL0 APB Clock APB clock USART0 Oscillator Divider UART0 VIORFCLK SPI0 Figure 4.3. SiM3L1xx Clocking Rev 1.1 40

SiM3L1xx 4.3.1. PLL (PLL0) The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in Free-Running mode without a reference frequency, Frequency-Locked to a reference frequency, or Phase-Locked to a reference frequency. The reference frequency for Frequency-Lock and Phase-Lock modes can use one of multiple sources (including the external oscillator) to provide maximum flexibility for different application needs. Because the PLL module generates its own clock, the DCO can be locked to a particular reference frequency and then moved to Free-Running mode to reduce system power and noise. The PLL module includes the following features: Three output ranges with output frequencies ranging from 23 to 50 MHz. Multiple reference frequency inputs, including the RTC0 oscillator, Low Power Oscillator, and external oscillator. Three output modes: Free-Running Digitally-Controlled Oscillator, Frequency-Locked, and Phase-Locked. Able to sense the rising edge or falling edge of the reference source. DCO frequency LSB dithering to provide finer average output frequencies. Spectrum spreading to reduce generated system noise. Low jitter and fast lock times.\ All output frequency updates (including dithering and spectrum spreading) can be temporarily suspended using the STALL bit during noise-sensitive measurements. 4.3.2. Low Power Oscillator (LPOSC0) The Low Power Oscillator is the default AHB oscillator on SiM3L1xx devices and enables or disables automatically, as needed. The default output frequency of this oscillator is factory calibrated to 20 MHz, and a divided 2.5 MHz version of this clock is also available as an AHB clock source. The Low Power Oscillator has the following features: 20 MHz and divided 2.5 MHz frequencies available for the AHB clock. Automatically starts and stops as needed. 4.3.3. Low Frequency Oscillator (LFOSC0) The low frequency oscillator (LFOSC) provides a low power internal clock source for the RTC0 timer and other peripherals on the device. No external components are required to use the low frequency oscillator, and the RTC1 and RTC2 pins do not need to be shorted together. The Low Frequency Oscillator has the following features: 16.4 kHz output frequency. 4.3.4. External Oscillators (EXTOSC0) The EXTOSC0 external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. The external oscillator output may be selected as the AHB clock or used to clock other modules independent of the AHB clock selection. The External Oscillator control has the following features: Support for external crystal, resonator, RC, C, or CMOS oscillators. Support for external CMOS frequencies from 10 kHz to 50 MHz. Support for external crystal frequencies from 10 kHz to 25 MHz. Various drive strengths for flexible crystal oscillator support. Internal frequency divide-by-two option available. 41 Rev 1.1

SiM3L1xx 4.4. Integrated LCD Controller (LCD0) SiM3L1xx devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3-mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast control which is independent of the supply voltage. LCD timing is derived from the RTC timer clock (RTC0TCLK) to allow precise control over the refresh rate. The SiM3L1xx devices use registers to store the enabled/disabled state of individual LCD segments. All LCD waveforms are generated on-chip based on the contents of these registers with flexible waveform control to reduce power consumption wherever possible. An LCD blinking function is also supported on a subset of LCD segments. The LCD0 module has the following features: Up to 40 segment pins and 4 common pins. Supports LCDs with 1/2 or 1/3 bias. Includes an on-chip charge pump with programmable output that allows firmware to control the contrast independent of the supply voltage. The RTC timer clock (RTC0TCLK) determines the LCD timing and refresh rate. All LCD waveforms are generated on-chip based on the contents of the LCD0 registers with flexible waveform control. LCD segments can be placed in a discharge state for a configurable number of RTC clock cycles before switching to the next state to reduce power consumption due to display loading. Includes a VBAT monitor that can serve as a wakeup source for Power Mode 8. Supports four hardware auto-contrast modes: bypass, constant, minimum, and auto-bypass. Supports hardware blinking for up to 8 segments. Rev 1.1 42

SiM3L1xx 4.5. Data Peripherals 4.5.1. 10-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. The DMA controller has the following features: Utilizes ARM PrimeCell uDMA architecture. Implements 10 channels. DMA crossbar supports DTM0, DTM1, DTM2, SARADC0, IDAC0, I2C0, SPI0, SPI1, USART0, AES0, ENCDEC0, EPCA0, external pin triggers, and timers. Supports primary, alternate, and scatter-gather data structures to implement various types of transfers. Access allowed to all AHB and APB memory space. 4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2) The Data Transfer Manager is a module that collects DMA request signals from various peripherals and generates a series of master DMA requests based on a state-driven configuration. This master request drives a set of DMA channels to perform functions such as assembling and transferring communication packets to external devices. This capability saves power by allowing the core to remain in a low power mode during complex transfer operations. A combination of simple and peripheral scatter-gather DMA configurations can be used to perform complex operations while reducing memory requirements. The DTM acts as a side channel for the peripheral’s DMA control signals. When active, it manages the DMA control signals for the peripherals. When the DTMn module is inactive, the peripherals communicate directly to the DMA module. The DTMn module has the following features: State descriptions stored in RAM with up to 15 states supported per module. Supports up to 15 source peripherals and up to 15 destination peripherals per module, in addition to memory or peripherals that do not require a data request. Includes error detection and an optional transfer timeout. Includes notifications for state transitions. 4.5.3. 128/192/256-bit Hardware AES Encryption (AES0) The basic AES block cipher is implemented in hardware. The integrated hardware support for Cipher Block Chaining (CBC) and Counter (CTR) algorithms results in identical performance, memory bandwidth, and memory footprint between the most basic Electronic Codebook (ECB) algorithm and these more complex algorithms. This hardware accelerator translates to more core bandwidth available for other functions or a power savings for low- power applications. The AES module includes the following features: Operates on 4-word (16-byte) blocks. Supports key sizes of 128, 192, and 256 bits for both encryption and decryption. Generates the round key for decryption operations. All cipher operations can be performed without any firmware intervention for multiple 4-word blocks (up to 32 kB). Support for various chained and stream-ciphering configurations with XOR paths on both the input and output. Internal 4-word FIFOs to facilitate DMA operations. Integrated key storage. Hardware acceleration for Electronic Codebook (ECB), Cipher-Block Chaining (CBC), and Counter (CTR) algorithms utilizing integrated counterblock generation and previous-block caching. 43 Rev 1.1

SiM3L1xx 4.5.4. 16/32-bit Enhanced CRC (ECRC0) The ECRC module is designed to provide hardware calculations for flash memory verification and communications protocols. In addition to calculating a result from direct writes from firmware, the ECRC module can automatically snoop the APB bus and calculate a result from data written to or read from a particular peripheral. This allows for an automatic CRC result without directly feeding data through the ECRC module. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3). The 16-bit polynomial is fully programmable. The ECRC module includes the following features: Support for a programmable 16-bit polynomial and one fixed 32-bit polynomial. Byte-level bit reversal for the CRC input. Byte-order reorientation of words for the CRC input. Word or half-word bit reversal of the CRC result. Ability to configure and seed an operation in a single register write. Support for single-cycle parallel (unrolled) CRC computation for 32-, 16-, or 8-bit blocks. Capability to CRC 32 bits of data per peripheral bus (APB) clock. Automatic APB bus snooping. Support for DMA writes using firmware request mode. 4.5.5. Encoder / Decoder (ENCDEC0) The encoder / decoder module supports Manchester and Three-out-of-Six encoding and decoding from either firmware or DMA operations. This module has the following features: Supports Manchester and Three-out-of-Six encoding and decoding. Automatic flag clearing when writing the input or reading the output data registers. Writing to the input data register automatically initiates an encode or decode operation. Optional output in one’s complement format. Hardware error detection for invalid input data during decode operations, which helps reduce power consumption and packet turn-around time. Flexible byte swapping on the input or output data. Rev 1.1 44

SiM3L1xx 4.6. Counters/Timers 4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2) Each timer module is independent, and includes the following features: Operation as a single 32-bit or two independent 16-bit timers. Clocking options include the APB clock, the APB clock scaled using an 8-bit prescaler, the external oscillator, or falling edges on an external input pin (synchronized to the APB clock). Auto-reload functionality in both 32-bit and 16-bit modes. TIMER0 and TIMER1 have the following features: Up/Down count capability, controlled by an external input pin. Rising and falling edge capture modes. Low or high pulse capture modes. Period and duty cycle capture mode. Square wave output mode, which is capable of toggling an external pin at a given rate with 50% duty cycle. 32- or 16-bit pulse-width modulation mode. TIMER2 does not support the standard input/output features of TIMER0 and TIMER1. The TIMER2 EX signal is internally connected to the outputs of the PVTOSC0 oscillators. TIMER2 can use any of the counting modes that use EX as an input, including up/down mode, edge capture mode, and pulse capture mode. The TIMER2 CT signal is disconnected. 4.6.2. Enhanced Programmable Counter Array (EPCA0) The Enhanced Programmable Counter Array (EPCA) module is a timer/counter system allowing for complex timing or waveform generation. Multiple modules run from the same main counter, allowing for synchronous output waveforms. This module includes the following features: Three sets of channel pairs (six channels total) capable of generating complementary waveforms. Center- and edge-aligned waveform generation. Programmable dead times that ensure channel pairs are never active at the same time. Programmable clock divisor and multiple options for clock source selection. Waveform update scheduling. Option to function while the core is inactive. Multiple synchronization triggers. Pulse-Width Modulation (PWM) waveform generation. 45 Rev 1.1

SiM3L1xx 4.6.3. Real-Time Clock (RTC0) The RTC module includes a 32-bit timer that allows up to 36 hours of independent time-keeping when used with a 32.768 kHz watch crystal. The RTC provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on SiM3L1xx devices. The RTC module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wide range of crystals. The RTC timer clock can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. The module also includes a low power internal low frequency oscillator that reduces low power mode current and is available for other modules to use as a clock source. The RTC module includes the following features: 32-bit timer (supports up to 36 hours) with three separate alarms. Option for one alarm to automatically reset the RTC timer. Missing clock detector. Can be used with the internal Low Frequency Oscillator or with an external 32.768 kHz crystal (no additional resistors or capacitors necessary). Programmable internal loading capacitors support a wide range of external 32.768 kHz crystals. The RTC timer clock (RTC0CLK) can be buffered and routed to an I/O pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. The RTC module can be powered from the low power mode charge pump for lowest possible power consumption while in PM8. 4.6.4. Low Power Timer (LPTIMER0) The Low Power Timer (LPTIMER) module runs from the RTC timer clock (RTC0CLK), allowing the LPTIMER to operate even if the AHB and APB clocks are disabled. The LPTIMER counter can increment using one of two clock sources: the clock selected by the RTC0 module, or rising or falling edges of an external signal. The Low Power Timer includes the following features: Runs on low-frequency RTC timer clock (RTC0TCLK). The LPTIMER counter can increment using one of two clock sources: the RTC0TCLK or rising or falling edges of an external signal. Overflow and threshold-match detection. Timer reset on threshold-match allows square-wave generation at a variable output frequency. Supports PWM with configurable period and duty cycle. The LPTIMER module can be powered from the low power mode charge pump for lowest possible power consumption while in PM8. 4.6.5. Watchdog Timer (WDTIMER0) The WDTIMER module includes a 16-bit timer, a programmable early warning interrupt, and a programmable reset period. The timer registers are protected from inadvertent access by an independent lock and key interface. The watchdog timer runs from the low frequency oscillator (LFOSC0). The Watchdog Timer has the following features: Programmable timeout interval. Optional interrupt to warn when the Watchdog Timer is nearing the reset trip value. Lock-out feature to prevent any modification until a system reset. Rev 1.1 46

SiM3L1xx 4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0) The SiM3L1xx devices contain a low-power Advanced Capture Counter module that runs from the RTC0 clock domain and can be used with digital inputs, switch topology circuits (reed switches), or with LC resonant circuits. For switch topology circuits, the module charges one or two external lines by pulsing internal pull-up resistors and detecting whether the reed switch is open or closed. For LC resonant circuits, the inputs are periodically energized to produce a dampened sine wave and configurable discriminator circuits detect the resulting decay time-constant. The advanced capture counter has the following general features: Single or differential inputs supporting single, dual, and quadrature modes of operation. Variety of interrupt and PM8 wake up sources. Provides feedback of the direction history, current and previous states, and condition flags. The advanced capture counter has the following features for switch circuit topologies: Ultra low power input comparators. Supports a wide range of pull-up resistor values with a self-calibration engine. Asymmetrical integrators for low-pass filtering and switch debounce. Two 24-bit counters and two 24-bit digital threshold comparators. Supports switch flutter detection. For LC resonant circuit topologies, the advanced capture counter includes: Separate minimum and maximum count registers and polarity, pulse, and toggle controls. Zone-based programmable timing. Two input comparators with support for a positive side input bias at VIO divided by 2. Supports a configurable excitation pulse width based on a 40 MHz oscillator and timer or an external digital stop signal. Two 8-bit peak counters that saturate at full scale for detecting the number of LC resonant peaks. Two discriminators with programmable thresholds. Supports a sample and hold mode for Wheatstone bridges. All devices in the SiM3L1xx family include the low power mode advanced capture counter (ACCTR0). Table 4.2 lists the supported inputs and outputs for each of the packages. Table 4.2. SiM3L1xx Supported Advanced Capture Counter Inputs and Outputs Input/Output SiM3L1x7 SiM3L1x6 SiM3L1x4 ACCTR0_IN0    ACCTR0_IN1    ACCTR0_LCIN0   ACCTR0_LCIN1    ACCTR0_STOP0    ACCTR0_STOP1    ACCTR0_LCPUL0   ACCTR0_LCPUL1   ACCTR0_LCBIAS0   ACCTR0_LCBIAS1   ACCTR0_DBG0   ACCTR0_DBG1   47 Rev 1.1

SiM3L1xx 4.7. Communications Peripherals 4.7.1. USART (USART0) The USART uses two signals (TX and RX) to communicate serially with an external device. In addition to these signals, the USART module can optionally use a clock (UCLK) or hardware handshaking (RTS and CTS). The USART module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud rate generators. Synchronous or asynchronous transmissions and receptions. Clock master or slave operation with programmable polarity and edge controls. Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX or RX). Individual enables for generated clocks during start, stop, and idle states. Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from 5 to 9 bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the LIN SYNC byte. Automatic parity generation (with enable). Automatic start and stop generation (with separate enables). Transmit and receive hardware flow-control. Independent inversion correction for TX, RX, RTS, and CTS signals. IrDA modulation and demodulation with programmable pulse widths. Smartcard ACK/NACK support. Parity error, frame error, overrun, and underrun detection. Multi-master and half-duplex support. Multiple loop-back modes supported. Multi-processor communications support. 4.7.2. UART (UART0) The low-power UART uses two signals (TX and RX) to communicate serially with an external device. The UART0 module can operate in PM8 mode by taking the clock directly from the RTC0 time clock (RTC0TCLK) and running from the low power mode charge pump. This will allow the system to conserve power while transmitting or receiving UART traffic. The UART supports standard baud-rates of 9600, 4800, 2400 and 1200 in this low power mode. The UART0 module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud rate generators. Asynchronous transmissions and receptions. Up to 5 Mbaud (TX or RX). Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from 5 to 9 bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the LIN SYNC byte. Automatic parity generation (with enable). Automatic start and stop generation (with separate enables). Independent inversion correction for TX and RX signals. Parity error, frame error, overrun, and underrun detection. Half-duplex support. Rev 1.1 48

SiM3L1xx Multiple loop-back modes supported. Multi-processor communications support. Operates at 9600, 4800, 2400, or 1200 baud in Power Mode 8. 4.7.3. SPI (SPI0, SPI1) SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select signal. The SPI0 and SPI1 modules include the following features: Supports 3- or 4-wire master or slave modes. Supports up to 10 MHz clock in master mode and 5 MHz clock in slave mode. Support for all clock phase and slave select (NSS) polarity modes. 16-bit programmable clock rate. Programmable MSB-first or LSB-first shifting. 8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers. Support for multiple masters on the same data lines. In addition, the SPI modules include several features to support autonomous DMA transfers: Hardware NSS control. Programmable FIFO threshold levels. Configurable FIFO data widths. Master or slave hardware flow control for the MISO and MOSI signals. SPI1 is on fixed pins and supports additional flow control options using a fixed input (SPI1CTS). Neither SPI1 nor the flow control input are on the crossbar. 4.7.4. I2C (I2C0) The I2C interface is a two-wire, bi-directional serial bus. The clock and data signals operate in open-drain mode with external pull-ups to support automatic bus arbitration. Reads and writes to the interface are byte oriented with the I2C interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/8th of the APB clock as a master or slave, which can be faster than allowed by the I2C specification, depending on the clock source used. A method of extending the clock- low duration is available to accommodate devices with different speed capabilities on the same bus. The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/ stop control and generation. The I2C0 module includes the following features: Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds. Can operate down to APB clock divided by 32768 or up to APB clock divided by 8. Support for master, slave, and multi-master modes. Hardware synchronization and arbitration for multi-master mode. Clock low extending (clock stretching) to interface with faster masters. Hardware support for 7-bit slave and general call address recognition. Firmware support for 10-bit slave address decoding. Ability to disable all slave states. Programmable clock high and low period. Programmable data setup/hold times. Spike suppression up to 2 times the APB period. 49 Rev 1.1

SiM3L1xx 4.8. Analog 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0) The SARADC0 module on SiM3L1xx devices implements the Successive Approximation Register (SAR) ADC architecture. The key features of the module are as follows: Single-ended 12-bit and 10-bit modes. Supports an output update rate of 250 k samples per second in 12-bit mode or 1 M samples per second in 10-bit mode. Operation in low power modes at lower conversion speeds. Selectable asynchronous hardware conversion trigger with hardware channel select. DC offset cancellation. Automatic result notification with multiple programmable thresholds. Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. Non-burst mode operation can also automatically accumulate multiple conversions, but a conversion start is required for each conversion. Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts supported. Flexible output data formatting. Sequencer allows up to eight sources to be automatically scanned using one of four channel characteristic profiles without software intervention. Eight-word conversion data FIFO for DMA operations. Includes two internal references (1.65 V fast-settling, 1.2/2.4 V precision), support for an external reference, and support for an external signal ground. 4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) The IDAC module takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC module includes the following features: 10-bit current DAC with support for four timer, up to seven external I/O and on demand output update triggers. Ability to update on rising, falling, or both edges for any of the external I/O trigger sources. Supports an output update rate greater than 600 k samples per second. Support for three full-scale output modes: 0.5 mA, 1.0 mA and 2.0 mA. Four-word FIFO to aid with high-speed waveform generation or DMA interactions. Individual FIFO overrun, underrun, and went-empty interrupt status sources. Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per word, or four 8-bit samples per word. Support for left- and right-justified data. 4.8.3. Low Current Comparators (CMP0, CMP1) The Comparators take two analog input voltages and output the relationship between these voltages (less than or greater than) as a digital signal. The low power comparator module includes the following features: Multiple sources for the positive and negative inputs, including VBAT, VREF, and 8 I/O pins. Two outputs available: a digital synchronous latched output and a digital asynchronous raw output. Programmable hysteresis and response time. Falling or rising edge interrupt options on the comparator output. 6-bit programmable reference divider. Rev 1.1 50

SiM3L1xx 4.9. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: The core halts program execution. Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. External port pins are forced to a known state. Interrupts and timers are disabled. AHB peripheral clocks to flash and RAM are enabled. Clocks to all APB peripherals other than the Watchdog Timer and DMAXBAR are disabled. All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For VBAT Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal low- power oscillator. The Watchdog Timer is enabled with the low frequency oscillator as its clock source. Program execution begins at location 0x00000000. All RSTSRC0 registers may be locked against writes by setting the CLKRSTL bit in the LOCK0_PERIPHLOCK0 register to 1. The reset sources can also optionally reset individual modules, including the low power mode charge pump, UART0, LCD0, advanced capture counter (ACCTR0), and RTC0. Reset Sources RESET Supply Monitor Missing Clock Detector Watchdog Timer Software Reset system or module reset Comparator 0 Comparator 1 Low Power Charge Pump Monitor RTC0 Event (Alarm or Osc Fail) Core Reset Figure 4.4. SiM3L1xx Reset Sources Block Diagram 51 Rev 1.1

SiM3L1xx 4.10. Security The peripherals on the SiM3L1xx devices have a register lock and key mechanism that prevents undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A key sequence must be written to the KEY register to modify bits in PERIPHLOCKx. Any subsequent write to KEY will then inhibit accesses of PERIPHLOCKx until it is unlocked again through KEY. Reading the KEY register indicates the current status of the PERIPHLOCKx lock state. If a peripheral’s registers are locked, all writes will be ignored. The registers can be read, regardless of the peripheral’s lock state. Peripheral Lock and Key USART0, UART0 SPI0/1 I2C0 PERIPHLOCK0 EPCA0 KEY PERIPHLOCK1 TIMER0/1 SARADC0 CMP0/1 Figure 4.5. SiM3L1xx Security Block Diagram 4.11. On-Chip Debugging The SiM3L1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for instruction trace. The JTAG interface is supported on SiM3L1x7 devices only, and does not include boundary scan capabilites. The ETM interface is supported on SiM3L1x7, and SiM3L1x6 devices only. The JTAG and ETM interfaces can be optionally enabled to provide more visibility while debugging at the cost of using several Port I/O pins. Additionally, if the core is configured for Serial Wire (SW) mode and not JTAG, then the Serial Wire Viewer (SWV) is available to provide a single pin to send out TPIU messages. Serial Wire Viewer is supported on all SiM3Lxxx devices. Most peripherals on SiM3L1xx devices have the option to halt or continue functioning when the core halts in debug mode. Rev 1.1 52

SiM3L1xx 5. Ordering Information Si M3 L 1 4 4 – B – GM Temperature Grade and Package Type Revision Pin Count – 4 (40 pin), 6 (64 pin), 7 (80 pin) Flash Size – 3 (32 kB), 4 (64 kB), 5 (128 kB), 6 (256 kB) Feature Set – varies by family Family – L (Low Power) Core – M3 (Cortex M3) Silicon Labs Figure 5.1. SiM3L1xx Part Numbering All devices in the SiM3L1xx family have the following features: Core: ARM Cortex-M3 with maximum operating frequency of 50 MHz. PLL. 10-Channel DMA Controller. 128/192/256-bit AES. 16/32-bit CRC. Encoder/Decoder. DC-DC Buck Converter. Timers: 3 x 32-bit (6 x 16-bit). Real-Time Clock. Low-Power Timer. PCA: 1 x 6 channels (Enhanced) ADC: 12-bit 250 ksps (10-bit 1 Msps) SAR. DAC: 10-bit IDAC. Temperature Sensor. Internal VREF. Comparator: 2 x low current. Serial Buses: 2 x USART, 2 x SPI, 1 x I2C Additionally, all devices in the SiM3L1xx family include the low power mode advanced capture counter (ACCTR0), though the smaller packages (SiM3L1x4) only support some of the external inputs and outputs. Rev 1.1 53

SiM3L1xx Table 5.1. Product Selection Guide s -) ut (+/ s utp Ordering Part Number Flash Memory (kB) RAM (kB) LCD Segments Digital Port I/Os Digital Port I/Os on the Crossbar Number of SARADC0 Channels Number of Comparator 0/1 Inputs Number of PMU Pin Wake Source Number of ACCTR0 Inputs and O JTAG Debugging Interface ETM Debugging Interface Serial Wire Debugging Interface Lead-free (RoHS Compliant) Package SiM3L167-C-GQ 256 32 160 (4x40) 62 38 24 15/15 14 12     TQFP-80 SiM3L166-C-GM 256 32 128 (4x32) 51 34 23 14/12 11 12    QFN-64 SiM3L166-C-GQ 256 32 128 (4x32) 51 34 23 14/12 11 12    TQFP-64 SiM3L164-C-GM 256 32 28 26 20 9/10 11 5   QFN-40 SiM3L157-C-GQ 128 32 160 (4x40) 62 38 24 15/15 14 12     TQFP-80 SiM3L156-C-GM 128 32 128 (4x32) 51 34 23 14/12 11 12    QFN-64 SiM3L156-C-GQ 128 32 128 (4x32) 51 34 23 14/12 11 12    TQFP-64 SiM3L154-C-GM 128 32 28 26 20 9/10 11 5   QFN-40 SiM3L146-C-GM 64 16 128 (4x32) 51 34 23 14/12 11 12    QFN-64 SiM3L146-C-GQ 64 16 128 (4x32) 51 34 23 14/12 11 12    TQFP-64 SiM3L144-C-GM 64 16 28 26 20 9/10 11 5   QFN-40 SiM3L136-C-GM 32 8 128 (4x32) 51 34 23 14/12 11 12    QFN-64 SiM3L136-C-GQ 32 8 128 (4x32) 51 34 23 14/12 11 12    TQFP-64 SiM3L134-C-GM 32 8 28 26 20 9/10 11 5   QFN-40 54 Rev 1.1

SiM3L1xx 6. Pin Definitions 6.1. SiM3L1x7 Pin Definitions V W S O / D T 0 1 / T 4 5 6 7 8 9 1 1 E 1 2 D 0 1 2 3 4 5 0. 0. 0. 0. 0. 0. 0. 0. S S C C O C 1. 1. 1. 1. 1. 1. PB PB PB PB PB PB PB PB RE VS RT RT VI VL PB PB PB PB PB PB 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 PB0.3 1 60 PB1.6 / TDI PB0.2 2 59 PB1.7 PB0.1 3 58 PB1.8 PB0.0 4 57 PB1.9 TMS / SWDIO 5 56 PB1.10 TCK / SWCLK 6 55 PB1.11 VIO 7 54 PB2.0 VIORF 8 53 PB2.1 VDRV 9 52 VSS VBAT / VBATDC 10 80-Pin TQFP 51 PB2.4 IND 11 50 PB2.5 VSS / VSSDC 12 49 PB2.6 VDC 13 48 PB2.7 PB4.15 / TRACECLK 14 47 PB3.0 PB4.14 / ETM0 15 46 PB3.1 PB4.13 / ETM1 16 45 PB3.2 PB4.12 / ETM2 17 44 PB3.3 PB4.11 / ETM3 18 43 PB3.4 PB4.10 19 42 PB3.5 PB4.9 20 41 PB3.6 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 B4.8 B4.7 B4.6 B4.5 B4.4 B4.3 B4.2 B4.1 B4.0 VIO VSS 3.15 3.14 3.13 3.12 3.11 3.10 B3.9 B3.8 B3.7 P P P P P P P P P B B B B B B P P P P P P P P P Figure 6.1. SiM3L1x7-GQ Pinout Rev 1.1 55

SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 0) s / 8 t Pin Name Type Pin Numbers (TQFP- I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions VSS Ground 12 31 52 71 VSSDC Ground (DC- 12 DC) VIO Power (I/O) 7 30 68 VIORF Power (RF I/O) 8 VBAT/ 10 VBATDC VDRV 9 VDC 13 VLCD Power (LCD 67 Charge Pump) IND DC-DC Inductor 11 RESET Active-low 72 Reset TCK/ JTAG / Serial 6 SWCLK Wire TMS/ JTAG / Serial 5 SWDIO Wire RTC1 RTC Oscillator 70 Input RTC2 RTC Oscillator 69 Output 56 Rev 1.1

SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 0) s / 8 t Pin Name Type Pin Numbers (TQFP- I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB0.0 Standard I/O 4 VIO    INT0.0 ADC0.20 WAKE.0 VREF CMP0P.0 PB0.1 Standard I/O 3 VIO    INT0.1 ADC0.21 WAKE.1 VREFGND CMP0N.0 PB0.2 Standard I/O 2 VIO    INT0.2 ADC0.22 WAKE.2 CMP1P.0 XTAL2 PB0.3 Standard I/O 1 VIO    INT0.3 ADC0.23 WAKE.3 CMP1N.0 XTAL1 PB0.4 Standard I/O 80 VIO    INT0.4 ADC0.0 WAKE.4 CMP0P.1 IDAC0 PB0.5 Standard I/O 79 VIO    INT0.5 ACCTR0_IN0 WAKE.5 ACCTR0_STOP0 PB0.6 Standard I/O 78 VIO    INT0.6 ACCTR0_IN1 WAKE.6 ACCTR0_STOP1 PB0.7 Standard I/O 77 VIO    INT0.7 ACCTR0_LCIN0 WAKE.7 PB0.8 Standard I/O 76 VIO    LPT0T0 ACCTR0_LCIN1 LPT0OUT0 INT0.8 WAKE.8 Rev 1.1 57

SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 0) s / 8 t Pin Name Type Pin Numbers (TQFP- I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB0.9 Standard I/O 75 VIO    LPT0T1 ADC0.1 INT0.9 CMP0N.1 WAKE.9 ACCTR0_LCPUL0 PB0.10 Standard I/O 74 VIO    LPT0T2 ADC0.2 INT0.10 CMP1P.1 WAKE.10 ACCTR0_LCPUL1 PB0.11/ Standard I/O / 73 VIO    LPT0T3 ADC0.3 TDO/SWV JTAG / Serial LPT0OUT1 CMP1N.1 Wire Viewer INT0.11 WAKE.11 PB1.0 Standard I/O 66 VIO   LCD0.39 LPT0T4 CMP0P.2 INT0.12 ACCTR0_LCBIAS0 PB1.1 Standard I/O 65 VIO   LCD0.38 LPT0T5 CMP0N.2 INT0.13 ACCTR0_LCBIAS1 PB1.2 Standard I/O 64 VIO   LCD0.37 LPT0T6 CMP1P.2 INT0.14 UART0_TX PB1.3 Standard I/O 63 VIO   LCD0.36 LPT0T7 CMP1N.2 INT0.15 UART0_RX PB1.4 Standard I/O 62 VIO   LCD0.35 ACCTR0_DBG0 ADC0.4 PB1.5 Standard I/O 61 VIO   LCD0.34 ACCTR0_DBG1 ADC0.5 PB1.6/TDI Standard I/O / 60 VIO   LCD0.33 ADC0.6 JTAG PB1.7 Standard I/O 59 VIO   LCD0.32 RTC0TCLK_OUT ADC0.7 58 Rev 1.1

SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 0) s / 8 t Pin Name Type Pin Numbers (TQFP- I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB1.8 Standard I/O 58 VIO   LCD0.31 CMP0P.3 PB1.9 Standard I/O 57 VIO   LCD0.30 CMP0N.3 PB1.10 Standard I/O 56 VIO   LCD0.29 CMP1P.3 PB1.11 Standard I/O 55 VIO   LCD0.28 CMP1N.3 PB2.0 Standard I/O 54 VIORF   LPT0T8 ADC0.8 INT1.0 CMP0P.4 WAKE.12 SPI1_CTS PB2.1 Standard I/O 53 VIORF   LPT0T9 ADC0.9 INT1.1 CMP0N.4 WAKE.13 VIORFCLK PB2.4 Standard I/O 51 VIORF   LPT0T12 ADC0.10 INT1.4 CMP0P.5 SPI1_SCLK PB2.5 Standard I/O 50 VIORF   LPT0T13 ADC0.11 INT1.5 CMP0N.5 SPI1_MISO PB2.6 Standard I/O 49 VIORF   LPT0T14 ADC0.12 INT1.6 CMP1P.5 SPI1_MOSI PB2.7 Standard I/O 48 VIORF   INT1.7 ADC0.13 SPI1_NSS CMP1N.5 PB3.0 Standard I/O 47 VIO   LCD0.27 INT1.8 ADC0.14 PB3.1 Standard I/O 46 VIO   LCD0.26 INT1.9 ADC0.15 PB3.2 Standard I/O 45 VIO   LCD0.25 INT1.10 ADC0.16 PB3.3 Standard I/O 44 VIO   LCD0.24 INT1.11 ADC0.17 Rev 1.1 59

SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 0) s / 8 t Pin Name Type Pin Numbers (TQFP- I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB3.4 Standard I/O 43 VIO   LCD0.23 INT1.12 CMP0P.6 PB3.5 Standard I/O 42 VIO   LCD0.22 INT1.13 CMP0N.6 PB3.6 Standard I/O 41 VIO   LCD0.21 INT1.14 CMP1P.6 PB3.7 Standard I/O 40 VIO   LCD0.20 INT1.15 CMP1N.6 PB3.8 Standard I/O 39 VIO  LCD0.19 CMP0P.7 PB3.9 Standard I/O 38 VIO  LCD0.18 CMP0N.7 PB3.10 Standard I/O 37 VIO  LCD0.17 CMP1P.7 PB3.11 Standard I/O 36 VIO  LCD0.16 CMP1N.7 PB3.12 Standard I/O 35 VIO  LCD0.15 ADC0.18 PB3.13 Standard I/O 34 VIO  LCD0.14 ADC0.19 PB3.14 Standard I/O 33 VIO  COM0.3 PB3.15 Standard I/O 32 VIO  COM0.2 PB4.0 Standard I/O 29 VIO  COM0.1 PB4.1 Standard I/O 28 VIO  COM0.0 PB4.2 Standard I/O 27 VIO  LCD0.13 PB4.3 Standard I/O 26 VIO  LCD0.12 PB4.4 Standard I/O 25 VIO  LCD0.11 PB4.5 Standard I/O 24 VIO  LCD0.10 PB4.6 Standard I/O 23 VIO  LCD0.9 PMU_Asleep PB4.7 Standard I/O 22 VIO  LCD0.8 PB4.8 Standard I/O 21 VIO  LCD0.7 60 Rev 1.1

SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 0) s / 8 t Pin Name Type Pin Numbers (TQFP- I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB4.9 Standard I/O 20 VIO  LCD0.6 PB4.10 Standard I/O 19 VIO  LCD0.5 PB4.11/ Standard I/O / 18 VIO  LCD0.4 ETM3 ETM PB4.12/ Standard I/O / 17 VIO  LCD0.3 ETM2 ETM PB4.13/ Standard I/O / 16 VIO  LCD0.2 ETM1 ETM PB4.14/ Standard I/O / 15 VIO  LCD0.1 ETM0 ETM PB4.15/ Standard I/O / 14 VIO  LCD0.0 TRACE- ETM CLK Rev 1.1 61

SiM3L1xx 6.2. SiM3L1x6 Pin Definitions V W S 3 4 5 6 7 8 9 / ET 1 2 D 0 1 2 3 4 0. 0. 0. 0. 0. 0. 0. S C C C 1. 1. 1. 1. 1. B B B B B B B E T T L B B B B B P P P P P P P R R R V P P P P P 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 PB0.2 1 48 PB1.5 PB0.1 2 47 PB1.6 PB0.0 3 46 PB1.7 SWDIO 4 45 PB1.8 SWCLK 5 44 PB1.9 VIO 6 43 PB1.10 VIORF / VDRV 7 42 PB2.0 VBAT / VBATDC 8 64 Pin TQFP 41 VSS IND 9 40 PB2.4 VSS / VSSDC 10 39 PB2.5 VDC 11 38 PB2.6 PB4.12 / TRACECLK 12 37 PB2.7 PB4.11 / ETM0 13 36 PB3.0 PB4.10 / ETM1 14 35 PB3.1 PB4.9 / ETM2 15 34 PB3.2 PB4.8 / ETM3 16 33 PB3.3 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 B4. B4. B4. B4. B4. B4. B4. B4. 3.1 3.1 B3. B3. B3. B3. B3. B3. P P P P P P P P B B P P P P P P P P Figure 6.2. SiM3L1x6-GQ Pinout 62 Rev 1.1

SiM3L1xx V W S 3 4 5 6 7 8 9 / ET 1 2 D 0 1 2 3 4 0. 0. 0. 0. 0. 0. 0. S C C C 1. 1. 1. 1. 1. B B B B B B B E T T L B B B B B P P P P P P P R R R V P P P P P 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 PB0.2 1 48 PB1.5 PB0.1 2 47 PB1.6 PB0.0 3 46 PB1.7 SWDIO 4 45 PB1.8 SWCLK 5 44 PB1.9 VIO 6 43 PB1.10 VIORF / VDRV 7 42 PB2.0 VBAT / VBATDC 8 64 pin QFN 41 VSS IND 9 (TopView) 40 PB2.4 VSS / VSSDC 10 39 PB2.5 VDC 11 38 PB2.6 PB4.12 / TRACECLK 12 37 PB2.7 PB4.11 / ETM0 13 36 PB3.0 PB4.10 / ETM1 14 VSS 35 PB3.1 PB4.9 / ETM2 15 34 PB3.2 PB4.8 / ETM3 16 33 PB3.3 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 B4. B4. B4. B4. B4. B4. B4. B4. 3.1 3.1 B3. B3. B3. B3. B3. B3. P P P P P P P P B B P P P P P P P P Figure 6.3. SiM3L1x6-GM Pinout Rev 1.1 63

SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions VSS Ground 10 41 VSSDC Ground (DC-DC) 10 VIO Power (I/O) 6 VIORF / Power (RF I/O) 7 VDRV VBAT / 8 VBATDC VDC 11 VLCD Power (LCD 54 Charge Pump) IND DC-DC Inductor 9 RESET Active-low Reset 57 SWCLK Serial Wire 5 SWDIO Serial Wire 4 RTC1 RTC Oscillator 56 Input RTC2 RTC Oscillator 55 Output PB0.0 Standard I/O 3 VIO XBR   INT0.0 ADC0.20 0 WAKE.0 VREF CMP0P.0 PB0.1 Standard I/O 2 VIO XBR   INT0.1 ADC0.22 0 WAKE.2 CMP0N.0 CMP1P.0 XTAL2 64 Rev 1.1

SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB0.2 Standard I/O 1 VIO XBR   INT0.2 ADC0.23 0 WAKE.3 CMP1N.0 XTAL1 PB0.3 Standard I/O 64 VIO XBR   INT0.3 ADC0.0 0 WAKE.4 CMP0P.1 IDAC0 PB0.4 Standard I/O 63 VIO XBR   INT0.4 ACCTR0_IN0 0 WAKE.5 ACCTR0_STOP0 PB0.5 Standard I/O 62 VIO XBR   INT0.5 ACCTR0_IN1 0 WAKE.6 ACCTR0_STOP1 PB0.6 Standard I/O 61 VIO XBR   INT0.6 ACCTR0_LCIN0 0 WAKE.7 PB0.7 Standard I/O 60 VIO XBR   LPT0T0 ACCTR0_LCIN1 0 LPT0OUT0 INT0.7 WAKE.8 PB0.8 Standard I/O 59 VIO XBR   LPT0T1 ADC0.1 0 INT0.8 CMP0N.1 WAKE.9 ACCTR0_LCPUL0 PB0.9/SWV Standard I/O 58 VIO XBR   LPT0T2 ADC0.2 /Serial Wire 0 INT0.9 CMP1P.1 Viewer WAKE.10 LPT0OUT1 ACCTR0_LCPUL1 PB1.0 Standard I/O 53 VIO XBR  LCD0.31 LPT0T4 CMP0P.2 0 INT0.12 ACCTR0_LCBIAS0 Rev 1.1 65

SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB1.1 Standard I/O 52 VIO XBR  LCD0.30 LPT0T5 CMP0N.2 0 INT0.13 ACCTR0_LCBIAS1 PB1.2 Standard I/O 51 VIO XBR  LCD0.29 LPT0T6 CMP1P.2 0 INT0.14 UART0_TX PB1.3 Standard I/O 50 VIO XBR  LCD0.28 LPT0T7 CMP1N.2 0 INT0.15 UART0_RX PB1.4 Standard I/O 49 VIO XBR  LCD0.27 ACCTR0_DBG0 ADC0.3 0 PB1.5 Standard I/O 48 VIO XBR  LCD0.26 ACCTR0_DBG1 ADC0.4 0 PB1.6 Standard I/O 47 VIO XBR  LCD0.25 RTC0TCLK_OUT ADC0.5 0 PB1.7 Standard I/O 46 VIO XBR  LCD0.24 CMP0P.3 0 PB1.8 Standard I/O 45 VIO XBR  LCD0.23 CMP0N.3 0 PB1.9 Standard I/O 44 VIO XBR  LCD0.22 CMP1P.3 0 PB1.10 Standard I/O 43 VIO XBR  LCD0.21 CMP1N.3 0 PB2.0 Standard I/O 42 VIOR XBR  LPT0T8 ADC0.6 F 0 INT1.0 CMP0P.4 WAKE.12 SPI1_CTS PB2.4 Standard I/O 40 VIOR XBR  LPT0T12 ADC0.7 F 0 INT1.4 CMP0P.5 SPI1_SCLK 66 Rev 1.1

SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB2.5 Standard I/O 39 VIOR XBR  LPT0T13 ADC0.8 F 0 INT1.5 CMP0N.5 SPI1_MISO PB2.6 Standard I/O 38 VIOR XBR  LPT0T14 ADC0.9 F 0 INT1.6 CMP1P.5 SPI1_MOSI PB2.7 Standard I/O 37 VIOR XBR  INT1.7 ADC0.10 F 0 SPI1_NSS CMP1N.5 PB3.0 Standard I/O 36 VIO XBR  LCD0.20 INT1.8 ADC0.11 0 PB3.1 Standard I/O 35 VIO XBR  LCD0.19 INT1.9 ADC0.12 0 PB3.2 Standard I/O 34 VIO XBR  LCD0.18 INT1.10 CMP0P.6 0 PB3.3 Standard I/O 33 VIO XBR  LCD0.17 INT1.11 CMP0N.6 0 PB3.4 Standard I/O 32 VIO XBR  LCD0.16 INT1.12 CMP0P.7 0 PB3.5 Standard I/O 31 VIO XBR  LCD0.15 INT1.13 CMP0N.7 0 PB3.6 Standard I/O 30 VIO XBR  LCD0.14 INT1.14 CMP1P.7 0 PB3.7 Standard I/O 29 VIO XBR  LCD0.13 INT1.15 CMP1N.7 0 PB3.8 Standard I/O 28 VIO  LCD0.12 ADC0.13 PB3.9 Standard I/O 27 VIO  LCD0.11 ADC0.14 PB3.10 Standard I/O 26 VIO  COM0.3 PB3.11 Standard I/O 25 VIO  COM0.2 Rev 1.1 67

SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match LCD Interface Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB4.0 Standard I/O 24 VIO  COM0.1 PB4.1 Standard I/O 23 VIO  COM0.0 PB4.2 Standard I/O 22 VIO  LCD0.10 ADC0.19 PB4.3 Standard I/O 21 VIO  LCD0.9 PB4.4 Standard I/O 20 VIO  LCD0.8 PB4.5 Standard I/O 19 VIO  LCD0.7 PB4.6 Standard I/O 18 VIO  LCD0.6 PMU_Asleep PB4.7 Standard I/O 17 VIO  LCD0.5 PB4.8/ETM3 Standard I/O / 16 VIO  LCD0.4 ETM PB4.9/ETM2 Standard I/O / 15 VIO  LCD0.3 ETM PB4.10/ Standard I/O / 14 VIO  LCD0.2 ETM1 ETM PB4.11/ Standard I/O / 13 VIO  LCD0.1 ETM0 ETM PB4.12/ Standard I/O / 12 VIO  LCD0.0 TRACECLK ETM 68 Rev 1.1

SiM3L1xx 6.3. SiM3L1x4 Pin Definitions V W S 2 3 4 5 6 / ET 1 2 7 8 0. 0. 0. 0. 0. S C C 0. 0. B B B B B E T T B B P P P P P R R R P P 0 9 8 7 6 5 4 3 2 1 4 3 3 3 3 3 3 3 3 3 PB0.1 1 30 PB0.9 PB0.0 2 29 PB2.0 SWDIO 3 28 PB2.1 SWCLK 4 27 PB2.2 VIO 5 40 pin QFN 26 PB2.3 (Top View) VIORF / VDRV 6 25 VSS VBAT / VBATDC 7 24 PB2.4 IND 8 23 PB2.5 VSS / VSSDC 9 22 PB2.6 VSS VDC 10 21 PB2.7 1 2 3 4 5 6 7 8 9 0 1 1 1 1 1 1 1 1 1 2 9 8 7 6 5 4 3 2 1 0 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. B B B B B B B B B B P P P P P P P P P P Figure 6.4. SiM3L1x4-GM Pinout Rev 1.1 69

SiM3L1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions VSS Ground 9 25 VSSDC Ground (DC-DC) 9 VIO Power (I/O) 5 VIORF / Power (RF I/O) 6 VDRV VBAT / 7 VBATDC VDC 10 IND DC-DC Inductor 8 RESET Active-low Reset 35 SWCLK Serial Wire 4 SWDIO Serial Wire 3 RTC1 RTC Oscillator Input 34 RTC2 RTC Oscillator 33 Output PB0.0 Standard I/O 2 VIO XBR0   INT0.0 ADC0.20 WAKE.0 VREF CMP0P.0 PB0.1 Standard I/O 1 VIO XBR0   INT0.1 ADC0.22 WAKE.2 CMP0N.0 CMP1P.0 XTAL2 70 Rev 1.1

SiM3L1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB0.2 Standard I/O 40 VIO XBR0   INT0.2 ADC0.23 WAKE.3 CMP0N.1 CMP1N.0 XTAL1 PB0.3 Standard I/O 39 VIO XBR0   INT0.3 ADC0.0 WAKE.4 CMP0P.1 IDAC0 PB0.4 Standard I/O 38 VIO XBR0   INT0.4 ACCTR0_IN0 WAKE.5 PB0.5 Standard I/O 37 VIO XBR0   INT0.5 ACCTR0_IN1 WAKE.6 PB0.6/SWV Standard I/O 36 VIO XBR0   LPT0T0 /Serial Wire Viewer LPT0OUT0 INT0.6 WAKE.8 PB0.7 Standard I/O 32 VIO XBR0   LPT0T6 CMP1P.2 INT0.7 UART0_TX PB0.8 Standard I/O 31 VIO XBR0   LPT0T7 CMP1N.2 INT0.8 UART0_RX PB0.9 Standard I/O 30 VIO XBR0   LPT0T1 ADC0.1 INT0.9 RTC0TCLK_OUT PB2.0 Standard I/O 29 VIORF XBR0  LPT0T8 ADC0.2 INT1.0 CMP0P.4 WAKE.12 SPI1_CTS Rev 1.1 71

SiM3L1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB2.1 Standard I/O 28 VIORF XBR0  LPT0T9 ADC0.3 INT1.1 CMP0N.4 WAKE.13 VIORFCLK PB2.2 Standard I/O 27 VIORF XBR0  LPT0T10 ADC0.4 INT1.2 CMP1P.4 WAKE.14 PB2.3 Standard I/O 26 VIORF XBR0  LPT0T11 ADC0.5 INT1.3 CMP1N.4 WAKE.15 PB2.4 Standard I/O 24 VIORF XBR0  LPT0T12 ADC0.6 INT1.4 CMP0P.5 SPI1_SCLK PB2.5 Standard I/O 23 VIORF XBR0  LPT0T13 ADC0.7 INT1.5 CMP0N.5 SPI1_MISO PB2.6 Standard I/O 22 VIORF XBR0  LPT0T14 ADC0.8 INT1.6 CMP1P.5 SPI1_MOSI PB2.7 Standard I/O 21 VIORF XBR0  INT1.7 ADC0.9 SPI1_NSS CMP1N.5 PB3.0 Standard I/O 20 VIO XBR0  INT1.8 CMP0N.7 PB3.1 Standard I/O 19 VIO XBR0  INT1.9 CMP1P.7 PB3.2 Standard I/O 18 VIO XBR0  INT1.10 CMP1N.7 PB3.3 Standard I/O 17 VIO XBR0  INT1.11 ADC0.10 PB3.4 Standard I/O 16 VIO XBR0  INT1.12 ADC0.11 PB3.5 Standard I/O 15 VIO XBR0  INT1.13 ADC0.12 72 Rev 1.1

SiM3L1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) s / t Pin Name Type Pin Numbers I/O Voltage Domain Crossbar Capability Port Match Output Toggle Logic External Trigger Inpu Digital Functions Analog Functions PB3.6 Standard I/O 14 VIO XBR0  INT1.14 ADC0.13 PB3.7 Standard I/O 13 VIO XBR0  INT1.15 ADC0.14 PB3.8 Standard I/O 12 VIO  ADC0.15 PB3.9 Standard I/O 11 VIO  ADC0.16 Rev 1.1 73

SiM3L1xx 6.4. TQFP-80 Package Specifications Figure 6.5. TQFP-80 Package Drawing Rev 1.1 74

SiM3L1xx Table 6.4. TQFP-80 Package Dimensions Dimension Min Nominal Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 b 0.17 0.20 0.27 c 0.09 — 0.20 D 14.00 BSC D1 12.00 BSC e 0.50 BSC E 14.00 BSC E1 12.00 BSC L 0.45 0.60 0.75 L1 1.00 Ref  0° 3.5° 7° aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ADD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 75 Rev 1.1

SiM3L1xx   Figure 6.6. TQFP-80 Landing Diagram Table 6.5. TQFP-80 Landing Diagram Dimensions Dimension Min Max C1 13.30 13.40 C2 13.30 13.40 E 0.50 BSC X 0.20 0.30 Y 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Rev 1.1 76

SiM3L1xx 6.4.1. TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.4.2. TQFP-80 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.4.3. TQFP-80 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 77 Rev 1.1

SiM3L1xx 6.5. QFN-64 Package Specifications Figure 6.7. QFN-64 Package Drawing Table 6.6. QFN-64 Package Dimensions Dimension Min Nominal Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 9.00 BSC D2 3.95 4.10 4.25 e 0.50 BSC E 9.00 BSC E2 3.95 4.10 4.25 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 78

SiM3L1xx   Figure 6.8. QFN-64 Landing Diagram Table 6.7. QFN-64 Landing Diagram Dimensions Dimension mm C1 8.90 C2 8.90 E 0.50 X1 0.30 Y1 0.85 X2 4.25 Y2 4.25 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. 79 Rev 1.1

SiM3L1xx 6.5.1. QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.5.2. QFN-64 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.0 mm square openings on a 1.5 mm pitch should be used for the center ground pad. 6.5.3. QFN-64 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 80

SiM3L1xx 6.6. TQFP-64 Package Specifications Figure 6.9. TQFP-64 Package Drawing Rev 1.1 81

SiM3L1xx Table 6.8. TQFP-64 Package Dimensions Dimension Min Nominal Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 — 0.20 D 12.00 BSC D1 10.00 BSC e 0.50 BSC E 12.00 BSC E1 10.00 BSC L 0.45 0.60 0.75  0° 3.5° 7° aaa — — 0.20 bbb — — 0.20 ccc — — 0.08 ddd — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ACD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 82 Rev 1.1

SiM3L1xx   Figure 6.10. TQFP-64 Landing Diagram Table 6.9. TQFP-64 Landing Diagram Dimensions Dimension Min Max C1 11.30 11.40 C2 11.30 11.40 E 0.50 BSC X 0.20 0.30 Y 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Rev 1.1 83

SiM3L1xx 6.6.1. TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.6.2. TQFP-64 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.6.3. TQFP-64 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 84 Rev 1.1

SiM3L1xx 6.7. QFN-40 Package Specifications Figure 6.11. QFN-40 Package Drawing Table 6.10. QFN-40 Package Dimensions Dimension Min Nominal Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 6.00 BSC D2 4.35 4.50 4.65 e 0.50 BSC E 6.00 BSC E2 4.35 4.5 4.65 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 85

SiM3L1xx Figure 6.12. QFN-40 Landing Diagram Table 6.11. QFN-40 Landing Diagram Dimensions Dimension mm C1 5.90 C2 5.90 E 0.50 X1 0.30 Y1 0.85 X2 4.65 Y2 4.65 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. 86 Rev 1.1

SiM3L1xx 6.7.1. QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.7.2. QFN-40 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.1 mm square openings on a 1.6 mm pitch should be used for the center ground pad. 6.7.3. QFN-40 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 87

SiM3L1xx 7. Revision Specific Behavior This chapter describes any differences between released revisions of the device. 7.1. Revision Identification The Lot ID Code on the top side of the device package can be used for decoding device revision information. Figures 7.1, 7.2, and 7.3 show how to find the Lot ID Code on the top side of the device package. In addition, firmware can determine the revision of the device by checking the DEVICEID registers. QFN-40 SiM3L 164 CCS701 1221 This character identifies the device revision Figure 7.1. SiM3L1x7-GQ Revision Information TQFP-64 QFN-64 SiM3L166 SiM3L166 C-GQ C-GM 1221CCS701 1221CCS701 e3 TW e3 TW These characters identify the device revision Figure 7.2. SiM3L1x6-GM and SiM3L1x6-GQ Revision Information Rev 1.1 88

SiM3L1xx QFN-40 SiM3L 164 CCS701 1221 This character identifies the device revision Figure 7.3. SiM3L1x4-GM Revision Information 89 Rev 1.1

SiM3L1xx DOCUMENT CHANGE LIST Revision 0.5 to Revision 1.0  Updated Electrical Specifications Tables with latest characterization data and production test limits.  Added missing signal ACCTR0_LCPUL1 to Table 6.2, “Pin Definitions and Alternate Functions for SiM3L1x6,” on page 64.  Removed ACCTR0_LCIN1 and ACCTR0_STOP0/1 signals from Table 6.3, “Pin Definitions and Alternate Functions for SiM3L1x4,” on page 70.  Updated Figure 6.8, “TFBGA-80 Package Drawing,” on page 79. Revision 1.0 to Revision 1.1  Removed all references to BGA-80 and the parts SiM3L167-C-GL and SiM3L157-C-GL. Rev 1.1 90

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