SiHP18N50C www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • Low figure-of-merit R x Q TO-220AB on g • 100 % avalanche tested Available • High peak current capability Available G • dv/dt ruggedness • Improved t /Q rr rr S • Improved gate charge D G S • High power dissipations capability N-Channel MOSFET • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 PRODUCT SUMMARY Note * This datasheet provides information about parts that are VDS (V) at TJ max. 560 RoHS-compliant and / or parts that are non RoHS-compliant. For RDS(on) () VGS = 10 V 0.225 example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details Q max. (nC) 76 g  Q (nC) 21 gs Q (nC) 29 gd Configuration Single ORDERING INFORMATION Package TO-220AB Lead (Pb)-free and halogen-free SiHP18N50C-E3 ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) C PARAMETER SYMBOL LIMIT UNIT Drain-source voltage V 500 DS V Gate-source voltage V ± 30 GS T = 25 °C 18 Continuous drain current (T = 150 °C) a V at 10 V C I J GS D T = 100 °C 11 A C Pulsed drain current b I 72 DM Linear derating factor 1.8 W/°C Single pulse avalanche energy c E 361 mJ AS Maximum power dissipation P 223 W D Reverse diode dv/dt d dv/dt 5 V/ns Operating junction and storage temperature range T , T -55 to +150 J stg °C Soldering recommendations (peak temperature) d For 10 s 300 Notes a. Drain current limited by maximum junction temperature b. Repetitive rating; pulse width limited by maximum junction temperature c. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 , IAS = 17 A d. ISD  18 A, di/dt  380 A/μs, VDD  VDS, TJ  150 °C e. 1.6 mm from case THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum junction-to-ambient R - 62 thJA °C/W Maximum junction-to-case (drain) R - 0.56 thJC S17-1726-Rev. E, 20-Nov-17 1 Document Number: 91374 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHP18N50C www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 °C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage V V = 0 V, I = 250 μA 500 - - V DS GS D VDS temperature coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.6 - V/°C Gate-source threshold voltage (N) V V = V , I = 250 μA 3.0 - 5.0 V GS(th) DS GS D Gate-source leakage I V = ± 30 V - - ± 100 nA GSS GS V = 500 V, V = 0 V - - 25 DS GS Zero gate voltage drain current I μA DSS V = 400 V, V = 0 V, T = 125 °C - - 250 DS GS J Drain-source on-state resistance RDS(on) VGS = 10 V ID = 10 A - 0.225 0.270  Forward transconductance a g V = 50 V, I = 10 A - 6.4 - S fs DS D Dynamic Input capacitance C - 2451 2942 iss V = 0 V, GS Output capacitance C V = 25 V, - 300 360 pF oss DS f = 1 MHz Reverse transfer capacitance C - 26 32 rss Total gate charge Q - 65 76 g Gate-source charge Q V = 10 V I = 18 A, V = 400 V - 21 - nC gs GS D DS Gate-drain charge Q - 29 - gd Turn-on delay time t - 80 - d(on) Rise time tr VDD = 250 V, ID = 18 A, - 27 - ns Turn-off delay time td(off) VGS = 10 V, Rg = 7.5  - 32 - Fall time t - 44 - f Gate input resistance Rg f = 1 MHz, open drain - 1.1 -  Drain-Source Body Diode Characteristics MOSFET symbol Continuous source-drain diode current IS showing the  D - - 18 integral reverse A G Pulsed diode forward current I p - n junction diode - - 72 SM S Diode forward voltage V T = 25 °C, I = 18 A, V = 0 V - - 1.5 V SD J S GS Reverse recovery time t - 503 - ns rr T = 25 °C, I = I , Reverse recovery charge Q J F S - 6.7 - μC rr di/dt = 100 A/μs, V = 35 V R Reverse recovery current I - 30 - A RRM Notes a. Repetitive rating; pulse width limited by maximum junction temperature      The information shown here is a preliminary product proposal, not a commercial product datasheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products. S17-1726-Rev. E, 20-Nov-17 2 Document Number: 91374 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHP18N50C www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 70 e 3 V c GS T = 25 °C n , Drain Current (A)D 2345600000 BToo p t t o m 11111198765 543210..... 00000 VVVVVV VVVVV J ain-to-Source On Resista(Normalized) 12..2155 ID = 17 A VGS = 10 V I Dr 10 7.0 V , on) 0.5 S( 0 RD 0 0 6 12 18 24 30 - 60- 40- 20 0 20 40 60 80 100120140160 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics, T = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature C 40 105 V Top 111 543G VVVS TJ = 150 °C VCCGirssSss === C0C ggVsd, +f =C 1gd ,M CHdzs shorted Current (A) 2300 1119876 210.... 0000 VVV VVVV ance (pF) 110034 Coss = Cds + Cgd Ciss ain Bottom 5.0 V acit Dr 7.0 V ap I, D 10 C 102 Coss C 0 10 rss 0 6 12 18 24 30 1 10 100 1000 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, T = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage C 100 20 I = 17 A V) D TJ = 150 °C ge ( 16 VVDS == 420500 VV ent (A) 10 e Volta 12 VDDSS = 100 V Curr 1 TJ = 25 °C ourc n S ai o- 8 Dr e-t I, D 0.1 , GatS 4 G V 0.01 0 5 6 7 8 9 10 0 30 60 90 120 VGS, Gate-to-Source Voltage (V) QG, Total Gate Charge (nC) Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S17-1726-Rev. E, 20-Nov-17 3 Document Number: 91374 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHP18N50C www.vishay.com Vishay Siliconix 100 103 A) Operation in this area limited Current ( 10 TJ = 150 °C TJ = 25 °C nt (A) 102 by RDS(on) ain urre Dr C 10 100 µs se ain er 1 Dr 1 ms I, RevSD I, D 1 TTSCJin =g= l 1e25 5p0 u° °ClsCe 10 ms V = 0 V GS 0.1 0.1 0.2 0.5 0.8 1.1 1.4 10 102 103 104 V , Source-to-Drain Voltage (V) V , Drain-to-Source Voltage (V) SD DS Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area 20 A) 15 nt ( e Curr 10 n ai Dr , D 5 I 0 25 50 75 100 125 150 T , Case Temperature (°C) C Fig. 9 - Maximum Drain Current vs. Case Temperature 1 nt Duty Cycle = 0.5 e si ne e Tradanc 0.2 ve ectimp 0.1 0.1 Effal I 0.05 d m zeer 0.02 aliTh m or N Single Pulse 0.01 10-4 10-3 10-2 0.1 1 Pulse Time (s) Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case S17-1726-Rev. E, 20-Nov-17 4 Document Number: 91374 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHP18N50C www.vishay.com Vishay Siliconix R D V DS Q VGS 10 V G D.U.T. R G +-VDD QGS QGD 10 V V Pulse width ≤ 1 µs G Duty factor ≤ 0.1 % Fig. 11 - Switching Time Test Circuit Charge Fig. 15 - Basic Gate Charge Waveform VDS Current regulator 90 % Same type as D.U.T. 50 kΩ 12 V 0.2 µF 0.3 µF 10 % V + GS V t t t t D.U.T. - DS d(on) r d(off) f V Fig. 12 - Switching Time Waveforms GS 3 mA I I G D L Current sampling resistors V DS Fig. 16 - Gate Charge Test Circuit Vary t to obtain p required I AS RG D.U.T + V - DD I AS 10 V t 0.01 Ω p Fig. 13 - Unclamped Inductive Test Circuit V DS t p V DD V DS I AS Fig. 14 - Unclamped Inductive Waveforms S17-1726-Rev. E, 20-Nov-17 5 Document Number: 91374 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHP18N50C www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations D.U.T. (cid:129) Low stray inductance (cid:129) Ground plane (cid:129) Low leakage inductance current transformer - + - + - Rg (cid:129) dV/dt controlled by Rg + (cid:129) Driver same type as D.U.T. V - DD (cid:129) ISD controlled by duty factor “D” (cid:129) D.U.T. - device under test Driver gate drive Period D = P.W. P.W. Period V = 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt V DD Re-applied voltage Body diode forward drop Inductor current Ripple ≤ 5 % ISD Note a. V = 5 V for logic level devices GS Fig. 17 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91374. S17-1726-Rev. E, 20-Nov-17 6 Document Number: 91374 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix TO-220-1 A MILLIMETERS INCHES E DIM. MIN. MAX. MIN. MAX. F A 4.24 4.65 0.167 0.183 Ø P b 0.69 1.02 0.027 0.040 Q b(1) 1.14 1.78 0.045 0.070 1) H( c 0.36 0.61 0.014 0.024 D 14.33 15.85 0.564 0.624 E 9.96 10.52 0.392 0.414 D e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 F 1.14 1.40 0.045 0.055 H(1) 6.10 6.71 0.240 0.264 1 2 3 J(1) 2.41 2.92 0.095 0.115 L 13.36 14.40 0.526 0.567 1) L(1) 3.33 4.04 0.131 0.159 L( M* Ø P 3.53 3.94 0.139 0.155 Q 2.54 3.00 0.100 0.118 b(1) L ECN: X15-0364-Rev. C, 14-Dec-15 DWG: 6031 Note • M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM C b e J(1) e(1) Package Picture ASE Xi’an Revison: 14-Dec-15 1 Document Number: 66542 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information Vishay Siliconix TO-220 FULLPAK (HIGH VOLTAGE) E A Ø P A1 n d1 d3 D u L1 V L b3 A2 b2 c b e MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 4.570 4.830 0.180 0.190 A1 2.570 2.830 0.101 0.111 A2 2.510 2.850 0.099 0.112 b 0.622 0.890 0.024 0.035 b2 1.229 1.400 0.048 0.055 b3 1.229 1.400 0.048 0.055 c 0.440 0.629 0.017 0.025 D 8.650 9.800 0.341 0.386 d1 15.88 16.120 0.622 0.635 d3 12.300 12.920 0.484 0.509 E 10.360 10.630 0.408 0.419 e 2.54 BSC 0.100 BSC L 13.200 13.730 0.520 0.541 L1 3.100 3.500 0.122 0.138 n 6.050 6.150 0.238 0.242 Ø P 3.050 3.450 0.120 0.136 u 2.400 2.500 0.094 0.098 v 0.400 0.500 0.016 0.020 ECN: X09-0126-Rev. B, 26-Oct-09 DWG: 5972 Notes 1. To be used only for process drawing. 2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads. 3. All critical dimensions should C meet C > 1.33. pk 4. All dimensions include burrs and plating thickness. 5. No chipping or package damage. Document Number: 91359 www.vishay.com Revision: 26-Oct-09 1

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