SiHG25N40D www.vishay.com Vishay Siliconix D Series Power MOSFET FEATURES PRODUCT SUMMARY • Halogen-free According to IEC 61249-2-21 VDS (V) at TJ max. 450 Definition RDS(on) max. at 25 °C () VGS = 10 V 0.17 • Optimal Design Q max. (nC) 88 g - Low Area Specific On-Resistance Qgs (nC) 12 - Low Input Capacitance (Ciss) Qgd (nC) 23 - Reduced Capacitive Switching Losses Configuration Single - High Body Diode Ruggedness - Avalanche Energy Rated (UIS) D • Optimal Efficiency and Operation TO-247AC - Low Cost - Simple Gate Drive Circuitry - Low Figure-of-Merit (FOM): R x Q on g G - Fast Switching • Compliant to RoHS Directive 2011/65/EU S D APPLICATIONS G S • Consumer Electronics N-Channel MOSFET - Displays (LCD or Plasma TV) • Lighting • Industrial - Welding - Induction Heating - Motor Drives - Battery Chargers • SMPS ORDERING INFORMATION Package TO-247AC Lead (Pb)-free SiHG25N40D-E3 Lead (Pb)-free and Halogen-free SiHG25N40D-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) C PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 400 DS Gate-Source Voltage ± 30 V V GS Gate-Source Voltage AC (f > 1 Hz) 30 T = 25 °C 25 C Continuous Drain Current (T = 150 °C) V at 10 V I J GS D T = 100 °C 16 A C Pulsed Drain Currenta I 78 DM Linear Derating Factor 2.2 W/°C Single Pulse Avalanche Energyb E 556 mJ AS Maximum Power Dissipation P 278 W D Operating Junction and Storage Temperature Range T , T - 55 to + 150 °C J stg Drain-Source Voltage Slope T = 125 °C 24 J dV/dt V/ns Reverse Diode dV/dtd 0.6 Soldering Recommendations (Peak Temperature) for 10 s 300c °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 17 A. c. 1.6 mm from case. d. ISD  ID, starting TJ = 25 °C. S12-0625-Rev. B, 26-Mar-12 1 Document Number: 91484 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHG25N40D www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum Junction-to-Ambient R - 40 thJA °C/W Maximum Junction-to-Case (Drain) R - 0.45 thJC SPECIFICATIONS (T = 25 °C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage V V = 0 V, I = 250 μA 400 - - V DS GS D VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 250 μA - 0.5 - V/°C Gate-Source Threshold Voltage (N) V V = V , I = 250 μA 3 - 5 V GS(th) DS GS D Gate-Source Leakage I V = ± 30 V - - ± 100 nA GSS GS V = 400 V, V = 0 V - - 1 DS GS Zero Gate Voltage Drain Current I μA DSS V = 320 V, V = 0 V, T = 125 °C - - 10 DS GS J Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 13 A - 0.14 0.17  Forward Transconductance g V = 50 V, I = 13 A - 7.4 - S fs DS D Dynamic Input Capacitance C - 1707 - iss V = 0 V, GS Output Capacitance C V = 100 V, - 177 - pF oss DS f = 1 MHz Reverse Transfer Capacitance C - 19 - rss Total Gate Charge Q - 44 88 g Gate-Source Charge Q V = 10 V I = 13 A, V = 320 V - 12 - nC gs GS D DS Gate-Drain Charge Q - 23 - gd Turn-On Delay Time t - 21 42 d(on) Rise Time t - 57 86 r VDD = 320 V, ID = 13 A, ns Turn-Off Delay Time td(off) VGS = 10 V, Rg = 24.6  - 40 80 Fall Time t - 37 74 f Gate Input Resistance Rg f = 1 MHz, open drain - 1.8 -  Drain-Source Body Diode Characteristics MOSFET symbol Continuous Source-Drain Diode Current IS showing the D - - 24 A integral reverse G Pulsed Diode Forward Current ISM p - n junction diode S - - 78 Diode Forward Voltage V T = 25 °C, I = 13 A, V = 0 V - - 1.2 V SD J S GS Reverse Recovery Time t - 353 - ns rr T = 25 °C, I = I = 13 A, Reverse Recovery Charge Q J F S - 4.4 - μC rr dI/dt = 100 A/μs, V = 20 V R Reverse Recovery Current I - 24 - A RRM S12-0625-Rev. B, 26-Mar-12 2 Document Number: 91484 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHG25N40D www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 80 3 TOP 15 V A) 1143 VV TJ = 25 °C nt ( 1121 VV eed) 2.5 ID = 13 A urce Curre 4600 BOTTOM 1 059876 VVVVVV n-to-Source (Normaliz 1.25 , Drain-to-SoD 20 R, DraiDS(on)On Resistanc 0.15 VGS = 10 V I 0 0 0 5 10 15 20 25 30 - 60- 40- 20 0 20 40 60 80 100120140160 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 60 10 000 e Current (A) 4500 BTOOTPT O M 111111 5432109876 VVVVVVVVVV TJ = 150 °C ce (pF) 1000 CoCssiss CCVCGirssSss = === 0 CCC gVgsd, +f+ = CC 1gd M, CHdzs Shorted o-Sourc 30 pacitan 100 Crss oss ds gd n-t 20 Ca ai 10 Dr , D 10 I 5 V 0 1 0 5 10 15 20 25 30 0 100 200 300 400 V , Drain-to-Source Voltage (V) DS V , Drain-to-Source Voltage (V) DS Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 100 24 V = 320 V nt (A) 80 ge (V) 20 VVDDDSSS == 28000 V V e a e Curr 60 ce Volt 16 urc our 12 o S I, Drain-to-SD 2400 TJ = 150 °C TJ = 25 °C V, Gate-to-GS 48 0 0 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 VDS, Drain-to-Source Voltage (V) Qg, Total Gate Charge (nC) Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S12-0625-Rev. B, 26-Mar-12 3 Document Number: 91484 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHG25N40D www.vishay.com Vishay Siliconix 100 30 A) Current ( 10 TJ = 150 °C TJ = 25 °C nt (A) 24 ain urre 18 Dr C se ain 12 er 1 Dr , RevD I, D 6 S I V = 0 V GS 0.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 50 75 100 125 150 VSD, Source-Drain Voltage (V) TJ, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature 1000 500 Operation in this Area Limited by R DS(on) I = Limited 475 ain Current (A) 110001 Limited by RDS(on)* DM 1110 0m0 m sμss Drain-to-Sourceown Voltage (V) 442550 I, DrD V, DSBrakd 400 0.1 T = 25 °C C 375 T = 150 °C J Single Pulse BVDSS Limited 0.01 350 1 10 100 1000 - 60- 40- 20 0 20 40 60 80 100120140160 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C) * V > minimum V at which R is specified GS GS DS(on) Fig. 8 - Maximum Safe Operating Area Fig. 10 - Temperature vs. Drain-to-Source Voltage 1 nt sie Duty Cycle = 0.5 n Trace 0.2 e an d Effectival Imped 0.1 00S..0i1n5gle Pulse 0.02 em alizher mT or N 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S12-0625-Rev. B, 26-Mar-12 4 Document Number: 91484 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHG25N40D www.vishay.com Vishay Siliconix R D V DS Q G 10 V V GS D.U.T. RG + QGS QGD -VDD V 10 V G Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 12 - Switching Time Test Circuit Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. V DS 90 % 50 kΩ 12 V 0.2 µF 0.3 µF + 10 % D.U.T. -VDS V GS td(on) tr td(off) tf VGS 3 mA Fig. 13 - Switching Time Waveforms I I G D Current sampling resistors Fig. 17 - Gate Charge Test Circuit L V DS Vary t to obtain p required I AS RG D.U.T + V - DD I AS 10 V t 0.01 Ω p Fig. 14 - Unclamped Inductive Test Circuit V DS t p V DD V DS I AS Fig. 15 - Unclamped Inductive Waveforms S12-0625-Rev. B, 26-Mar-12 5 Document Number: 91484 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiHG25N40D www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations D.U.T. (cid:129) Low stray inductance (cid:129) Ground plane (cid:129) Low leakage inductance current transformer - + - + - Rg (cid:129) dV/dt controlled by Rg + (cid:129) Driver same type as D.U.T. V - DD (cid:129) ISD controlled by duty factor “D” (cid:129) D.U.T. - device under test Driver gate drive Period D = P.W. P.W. Period V = 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt V DD Re-applied voltage Body diode forward drop Inductor current Ripple ≤ 5 % ISD Note a. V = 5 V for logic level devices GS Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91484. S12-0625-Rev. B, 26-Mar-12 6 Document Number: 91484 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) VERSION 1: FACILITY CODE = 9 MILLIMETERS MILLIMETERS DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES A 4.83 5.21 D1 16.25 16.85 5 A1 2.29 2.55 D2 0.56 0.76 A2 1.50 2.49 E 15.50 15.87 4 b 1.12 1.33 E1 13.46 14.16 5 b1 1.12 1.28 E2 4.52 5.49 3 b2 1.91 2.39 6 e 5.44 BSC b3 1.91 2.34 L 14.90 15.40 b4 2.87 3.22 6, 8 L1 3.96 4.16 6 b5 2.87 3.18 Ø P 3.56 3.65 7 c 0.55 0.69 6 Ø P1 7.19 ref. c1 0.55 0.65 Q 5.31 5.69 D 20.40 20.70 4 S 5.54 5.74 Notes (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 19-Oct-2020 1 Document Number: 91360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = Y 4 A A B E 7 ØP (Datum B) E/2 S A2 Ø kMDBM 3 R/2 ØP1 A D2 Q 2 x R 4 4 (2) D D1 1 2 3 D 4 Thermal pad 5 L1 C L 4 E1 See view B A 0.01MDBM 2 x b2 C View A - A 2 x e 3 x b b4 A1 0.10MCAM (b1, b3, b5) Planting Base metal Lead Assignments 1. Gate D DE E 2. Drain 3. Source C C (c) c1 4. Drain (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS MILLIMETERS DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES A 4.58 5.31 D2 0.51 1.30 A1 2.21 2.59 E 15.29 15.87 A2 1.17 2.49 E1 13.72 - b 0.99 1.40 e 5.46 BSC b1 0.99 1.35 Ø k 0.254 b2 1.53 2.39 L 14.20 16.25 b3 1.65 2.37 L1 3.71 4.29 b4 2.42 3.43 Ø P 3.51 3.66 b5 2.59 3.38 Ø P1 - 7.39 c 0.38 0.86 Q 5.31 5.69 c1 0.38 0.76 R 4.52 5.49 D 19.71 20.82 S 5.51 BSC D1 13.08 - Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 19-Oct-2020 2 Document Number: 91360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix VERSION 3: FACILITY CODE = N A B R/2 E A D2 P1 P N A2 Q S M R B D 1 D D M D K 1 L C L C b4 E1 b2 e A1 b 0.01M DBM 0.10M CAM b1, b3, b5 Base metal c c1 b, b2, b4 Plating MILLIMETERS MILLIMETERS DIM. MIN. MAX. DIM. MIN. MAX. A 4.65 5.31 D2 0.51 1.35 A1 2.21 2.59 E 15.29 15.87 A2 1.17 1.37 E1 13.46 - b 0.99 1.40 e 5.46 BSC b1 0.99 1.35 k 0.254 b2 1.65 2.39 L 14.20 16.10 b3 1.65 2.34 L1 3.71 4.29 b4 2.59 3.43 N 7.62 BSC b5 2.59 3.38 P 3.56 3.66 c 0.38 0.89 P1 - 7.39 c1 0.38 0.84 Q 5.31 5.69 D 19.71 20.70 R 4.52 5.49 D1 13.08 - S 5.51 BSC ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971 Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 19-Oct-2020 3 Document Number: 91360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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