SiC403 Vishay Siliconix microBUCK® SiC403 6 A, 28 V Integrated Buck Regulator with Programmable LDO DESCRIPTION FEATURES The Vishay Siliconix SiC403 is an advanced stand-alone • High efficiency > 95 % synchronous buck regulator featuring integrated power (cid:129) 6 A continuous output current capability MOSFETs, bootstrap switch, and a programmable LDO in a (cid:129) Integrated bootstrap switch space-saving MLPQ 5 x 5 - 32 pin package. (cid:129) Programmable 200 mA LDO with bypass logic The SiC403 is capable of operating with all ceramic solutions (cid:129) Temperature compensated current limit and switching frequencies up to 1 MHz. The programmable (cid:129) Pseudo fixed-frequency adaptive on-time control frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full (cid:129) All ceramic solution enabled range of load current. The internal LDO may be used to (cid:129) Programmable input UVLO threshold supply 5 V for the gate drive circuits or it may be bypassed (cid:129) Independent enable pin for switcher and LDO with an external 5 V for optimum efficiency and used to drive (cid:129) Selectable ultra-sonic power-save mode external n-channel MOSFETs or other loads. Additional (cid:129) Programmable soft-start features include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable (cid:129) Soft-shutdown over-current protection, soft shutdown and selectable (cid:129) 1 % internal reference voltage power-save. The Vishay Siliconix SiC403 also provides an (cid:129) Power good output enable input and a power good output. (cid:129) Under and over voltage protection (cid:129) Material categorization: For definitions of compliance PRODUCT SUMMARY please see www.vishay.com/doc?99912 Input Voltage Range 3 V to 28 V APPLICATIONS Output Voltage Range 0.75 V to 5.5 V (cid:129) Notebook, desktop, and server computers Operating Frequency 200 kHz to 1 MHz (cid:129) Digital HDTV and digital consumer applications Continuous Output Current 6 A (cid:129) Networking and telecommunication equipment Peak Efficiency 95 % at 300 kHz (cid:129) Printers, DSL, and STB applications Package MLPQ 5 mm x 5 mm (cid:129) Embedded applications (cid:129) Point of load power supplies TYPICAL APPLICATION CIRCUIT 3.3 V EN/PSV (Tri-State) LDO_EN PGOOD VOUT V ENL TONAGND EN\PS LX ILIM PGOODLX 32 31 30 29 28 27 26 25 FB LX VOUT 1 24 VOUT PAD 1 LX 2 23 VDD 3 AGND 22 PGND AGND PAD 3 PGND 4 21 FBL 5 LX 20 PGND VIN VIN 6 PAD 2 19 PGND SS 7 VIN 18 PGND BST 8 17 PGND 9 10 11 12 13 14 15 16 N N N CX C D D VI VI VI NL N GN GN PP SiC403 (MLP 5 x 5-32L) Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vishay.com www.vishay.com S12-0628-Rev. C, 19-Mar-12 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix PIN CONFIGURATION (TOP VIEW) V ENL TON AGND EN\PS LX ILIM PGOOD LX 32 31 30 29 28 27 26 25 FB 1 24 LX PAD 1 VOUT 2 23 LX VDD 3 AGND 22 PGND AGND 4 PAD 3 21 PGND FBL 5 LX 20 PGND PAD 2 VIN 6 19 PGND SS 7 VIN 18 PGND BST 8 17 PGND 9 10 11 12 13 14 15 16 N N N C X C D D VI VI VI N L N GN GN P P PIN DESCRIPTION Pin Number Symbol Description Feedback input for switching regulator. Connect to an external resistor divider from output to program 1 FB output voltage. 2 V Output voltage input to the controller. Additionally may be used to by pass LDO to supply V directly. OUT DD Bias for internal logic circuitry and gate drivers. Connect to external 5V power supply or configure 3 V DD the internal LDO for 5 V. 4, 30, PAD 1 A Analog ground GND Feedback input for internal LDO. Connect to an external resistor divider from V to A to program 5 FBL DD GND LDO output. 6, 9-11, PAD 2 V Power stage input (HS FET Drain) IN 7 SS Connect to an external capacitor to A to program softstart ramp GND 8 BST Bootstrap pin. A capacitor is connected between BST and LX to provide HS driver voltage. 12 NC Not internally connected 13, 23-25, 28, PAD 3 LX Switching node (HS FET Source and LS FET Drain) 14 NC Not internally connected 15-22 P Power ground (LS FET Source) GND 26 P Open-drain power good indicator. Externally pull-up resistor is required. GOOD 27 I Connect to an external resistor between I and LX to program over current limit LIM LIM Tri-state pin. Pull low to A to disable the regulator. Float to enable forced continuous current 29 EN/PSV GND mode. Pull high to V to enable power save mode. DD 31 T Connect to an external resistor to A program on-time ON GND 32 ENL Enable input for internal LDO. Pull down to A to disable internal LDO. GND ORDERING INFORMATION Part Number Package SiC403CD-T1-GE3 MLPQ55-32 SiC403DB Evaluation board www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 2 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM 26 29 6, 9-11, PAD 2 AGND VDD PGOOD EN/PSV VIN VIN 4, 30, PAD 1 VDD BST Reference Control and Status 8 DL SS 7 Soft Start LX 13, 23 to 25, FB + On-Time Gate Drive 28, PAD 3 1 - Generator Control VDD TON FB Comparator PGND 31 15 to 22 Zero Cross VOUT Detector 2 ILIM Bypass Comparator Valley1-Limit 27 VDD VDD A VIN 3 Y B LDO MUX FBL ENL 5 32 ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) A Parameter Symbol Min. Max. Unit LX to P Voltage V - 0.3 + 30 GND LX LX to P Voltage (transient - 100 ns) V - 2 + 30 GND LX V to P Voltage V - 0.3 + 30 IN GND IN EN/PSV, P , I , to A - 0.3 V + 0.3 GOOD LIM GND DD BST Bootstrap to LX; V to P - 0.3 + 6 V DD GND A to P V - 0.3 + 0.3 GND GND AG-PG EN/PSV, P , I , V , V , FB, FBL to GND - 0.3 + (V + 0.3) GOOD LIM OUT LDO DD t to P - 0.3 + (V - 1.5) ON GND DD BST to P - 0.3 + 35 GND Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min. Typ. Max. Unit Input Voltage V 3 28 IN V to P V 3 5.5 V DD GND DD V to P V 0.75 5.5 OUT GND OUT Note: For proper operation, the device should be used within the recommended conditions. THERMAL RESISTANCE RATINGS Parameter Symbol Min. Typ. Max. Unit Storage Temperature T - 40 + 150 STG Maximum Junction Temperature T - 150 °C J Operation Junction Temperature T - 25 + 125 J Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vishay.com www.vishay.com S12-0628-Rev. C, 19-Mar-12 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol Min. Typ. Max. Unit Thermal Resistance, Junction-to-Ambientb High-Side MOSFET 25 °C/W Low-Side MOSFET 20 PWM Controller and LDO Thermal Resistance 50 Peak IR Reflow Temperature T - 260 °C Reflow Notes: a. This device is ESD sensitive. Use of standard ESD handling precautions is required. b. Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specififed in the Electrical Characteristics section is not recommended. ELECTRICAL SPECIFICATIONS Test Conditions Unless Specified V = 12 V, V = 5 V, T = + 25 °C for typ., Parameter Symbol IN DD A Min. Typ. Max. Unit - 40 °C to + 85 °C for min. and max., T = < 125 °C J Input Supplies V Sensed at ENL pin, rising edge 2.4 2.6 2.95 V UVLO Threshold Voltagea IN_UV+ IN V Sensed at ENL pin, falling edge 2.235 2.4 2.565 IN_UV- V UVLO Hysteresis V EN/PSV = High 0.2 IN IN_UV_HY V V Measured at V pin, rising edge 2.5 2.8 3 V UVLO Threshold Voltage DD_UV+ DD DD V Measured at V pin, falling edge 2.4 2.6 2.9 DD_UV- DD V UVLO Hysteresis V 0.2 DD DD_UV_HY EN/PSV, ENL = 0 V, V = 28 V 8.5 20 IN VIN Supply Current IIN Standby mode: 130 µA ENL = V , EN/PSV = 0 V DD EN/PSV, ENL = 0 V 3 7 EN/PSV = V , no load (f = 25 kHz), DD SW 2 VDD Supply Current IVDD VFB > 750 mV mA f = 250 kHz, EN/PSV = floating, no loadb SW 10 25°C bench testing Controller FB On-Time Threshold V Static V and load, - 40 °C to + 85 °C 0.7425 0.750 0.7599 V FB-TH IN Frequency Rangeb F continuous mode, 25°C bench testing 200 1000 kHz PWM Bootstrap Switch Resistance 10  Timing Continuous mode operation V = 15 V, On-Time t IN 2386 2650 2915 ON V = 5 V, R = 300 k OUT ton ns Minimum On-Timeb t 25°C bench testing 80 ON Minimum Off-Timeb t 25°C bench testing 320 OFF Soft Start Soft Start Currentb ISS IOUT = ILIM/2, 25°C bench testing 2.75 µA Analog Inputs/Outputs V Input Resistance R 500 k OUT O-IN Current Sense Zero-Crossing Detector Threshold Voltage V LX-P - 3.5 0.5 + 3.5 mV Sense-th GND Power Good Power Good Threshold Voltage PG_VTH_UPPER VFB > internal reference 750 mV + 20 % Power Good Threshold Voltage PG_VTH_LOWER VFB < internal reference 750 mV - 10 Start-Up Delay Time PG_T C = 10 nF 12 ms d ss Fault (noise-immunity) Delay Timeb PG_I V = 0 V, 25°C bench testing 5 µs CC EN Power Good Leakage Current PG_I V = 0 V 1 µA LK EN Power Good On-Resistance PG_R V = 0 V 10  DS-ON EN www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 4 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix ELECTRICAL SPECIFICATIONS Test Conditions Unless Specified V = 12 V, V = 5 V, T = + 25 °C for typ., Parameter Symbol IN DD A Min. Typ. Max. Unit - 40 °C to + 85 °C for min. and max., T = < 125 °C J Fault Protection I Source Current I 8 µA LIM LIM R = 6 kV = 5 V, Valley Current Limit ILIM DD 4.5 6 7.2 A 25°C bench testing V with respect to Internal 500 mV Output Under-Voltage Fault V FB - 25 % OUV_Fault reference, 8 consecutive clocks Smart Power-Save Protection V with respect to internal 500 mV P FB + 10 Threshold Voltageb SAVE_VTH reference, 25°C bench testing % V with respect to internal 500 mV Over-Voltage Protection Threshold FB + 20 reference Over-Voltage Fault Delayb tOV-Delay 25°C bench testing 5 µs Over Temperature Shutdownb TShut 10 °C hysteresis, 25°C bench testing 150 °C Logic Inputs/Outputs Logic Input High Voltage VIH 1 EN, ENL, PSV V Logic Input Low Voltage VIL 0.4 EN/PSV Input Bias Current IEN EN/PSV = VDD or AGND - 10 + 10 ENL Input Bias Current IENL VIN = 28 V 11 18 µA FBL, FB Input Bias Current FBL_ILK FBL, FB = VDD or AGND - 1 + 1 Linear Dropout Regulator FBL Accuracy FBL V load = 10 mA 0.735 0.750 0.765 V ACC LDO Start-up and foldback, V = 12 V 115 LDO Current Limit LDO_I IN mA LIM Operating current limit, V = 12 V 134 200 IN VLDO to VOUT Switch-Over Thresholdc VLDO-BPS - 130 + 130 mV VLDO to VOUT Non-Switch-Over Thresholdc VLDO-NBPS - 500 + 500 VLDO to VOUT Switch-Over Resistance RLDO VOUT = 5 V 2  From V to V , V = + 5 V, LDO Drop Out Voltaged IN VLDO VLDO 1.2 V I = 100 mA VLDO Notes: a.V is programmable using a resistor divider from V to ENL to A . The ENL voltage is compared to an internal reference. IN UVLO IN GND b.Guaranteed by design. c. The switch-over threshold is the maximum voltage diff erential between the V and V pins which ensures that V will internally LDO OUT LDO switch-over to V . The non-switch-over threshold is the minimum voltage diff erential between the V and V pins which ensures that OUT LDO OUT V will not switch-over to V . LDO OUT d.The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point. Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vishay.com www.vishay.com S12-0628-Rev. C, 19-Mar-12 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix ELECTRICAL CHARACTERISTICS 90 90 80 80 70 70 60 60 %) %) ncy ( 50 cy ( 50 e n fici 40 cie 40 Ef Effi 30 30 20 20 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz VIN = 12 V, VOUT = 1 V, FSW = 500 kHz 10 10 0 0 0.01 0.1 1 10 0.01 0.1 1 10 IOUT (A) IOUT (A) Efficiency vs. I Efficiency vs. I OUT OUT (in Continuous Conduction Mode) (in Power-Save-Mode) 1.006 1.008 1.004 1.006 1.004 1.002 V) VIN = 12 V, VOUT = 1 V, FSW = 500 kHz 1.002 V (OUT 1 (V)UT 1 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz 0.998 VO 0.998 0.996 0.996 0.994 0.994 0.992 0.992 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 IOUT (A) IOUT (A) V vs. I V vs. I OUT OUT OUT OUT (in Continuous Conduction Mode) (in Power-Save-Mode) 1.012 1.05 1.04 1.010 1.03 1.008 1.02 1.01 V) 1.006 V) V (OUT1.004 V (OUT 0.919 V = 1 V, FSW = 500 kHz, 1.002 VOUT = 1 V, FSW = 500 kHz, 0.98 COoUnTtinuous Conduction Mode Continuous Conduction Mode 0.97 1 0.96 0.998 0.95 5 7 9 11 13 15 17 19 21 23 5 7 9 11 13 15 17 19 21 23 VIN (V) VIN (V) V vs. V at I = 0 A V vs. V at I = 6 A OUT IN OUT OUT IN OUT (in Continuous Conduction Mode, FSW = 500 kHz) (in Continuous Conduction Mode, FSW = 500 kHz) www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 6 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix ELECTRICAL CHARACTERISTICS 1.1 40 35 1.05 30 mV) 25 VOUT = 1 V, IOUT = 6 A, FSW = 500 kHz (V)OUT 1 Ripple ( 20 V VOUT = 1 V, FSW = 500 kHz, Power Saving Mode OUT 15 V 0.95 10 5 0.9 0 6 8 10 12 14 16 18 20 22 24 0 5 10 15 20 25 V (V) V (V) IN IN V vs. V V Ripple vs. V OUT IN OUT IN (I = 0 A in Power-Save-Mode) (I = 6 A in Continuous Conduction Mode) OUT OUT 35 40 30 35 30 25 V) V) m m 25 V = 1 V, I = 0 A, FSW = 500 kHz ple ( 20 VOUT =1 V, IOUT = 0 A, FSW = 500 kHz ple ( OUT OUT p p 20 Ri Ri V OUT 15 V OUT 15 10 10 5 5 0 0 0 5 10 15 20 25 6 8 10 12 14 16 18 20 VIN (V) VIN (V) V Ripple vs. V V Ripple vs. V OUT IN OUT IN (I = 0 A in Continuous Conduction Mode) (I = 0 A in Power-Save-Mode) OUT OUT 550 600 530 500 510 490 400 Hz) 470 Hz) W (k 450 W (k 300 S S F 430 F 200 410 V = 12 V, V = 1 V IN OUT 390 V = 12 V, V = 1 V 100 IN OUT 370 350 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 IOUT (A) IOUT (A) FSW vs. I FSW vs. I OUT OUT (in Continuous Conduction Mode) (in Power-Save-Mode) Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix ELECTRICAL CHARACTERISTICS Ch2: Output ripple Voltage (20mV/div) Ch2: Output ripple Voltage (20mV/div) Ch1: LX Switching Node (5V/div) Ch1: LX Switching Node (5V/div) Time: 20 μs/div Time: 2 μs/div V Ripple in Power Save Mode (No Load) V Ripple in Continuous Conduction Mode (No Load) OUT OUT (V = 12 V, V = 1 V) (V = 12 V, V = 1 V, FSW = 500 kHz) IN OUT IN OUT Ch3: Output Current (2A/div) Ch3: Output Current (2A/div) Ch2: Output Voltage (50mV/div) Ch2: Output Voltage (50mV/div) Time: 5 μs/div Time: 5 μs/div Transient Response in Continuous Conduction Mode Transient Response in Continuous Conduction Mode (6 A to 0.2 A) (0.2 A to 6 A) (V = 12 V, V = 1 V, FSW = 500 kHz) (V = 12 V, V = 1 V, FSW = 500 kHz) IN OUT IN OUT Ch3: Output Current (2A/div) Ch3: Output Current (2A/div) Ch2: Output Voltage (50mV/div) Ch2: Output Voltage (50mV/div) Time: 10 μs/div Time: 10 μs/div Transient Response in Power Save Mode Transient Response in Power Save Mode (6 A to 0.2 A) (0.2 A to 6 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A) www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 8 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix ELECTRICAL CHARACTERISTICS Ch4: Vin (5V/div) Ch4: Iout (10A/div) Ch2: Vout (500mV/div) Ch2: Vout (1V/div) Ch3: Power Good (5V/div) Ch3: Power good (5V/div) Ch1: Switching Node (5V/div) Ch1: Switching Node (10V/div) Time: 10 ms/div Time: 10 ms/div Start-up with V Ramping up Over-Current Protection IN (V = 12 V, V = 1 V, FSW = 500 kHz) (V = 12 V, V = 1 V, FSW = 500 kHz ) IN OUT IN OUT 100 95 90 %) y ( VIN = 12 V, VOUT = 5 V, FSW = 300 kHz c n 85 e ci fi Ef 80 75 70 0 1 2 3 4 5 6 7 I (A) OUT Efficiency with 12 V , 5 V , 300 kHz IN OUT Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 9 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix APPLICATIONS INFORMATION SiC403 Synchronous Buck Converter The SiC403 is a step down synchronous buck DC/DC VIN tON converter with integrated power FETs and programmable VLX LDO. The SiC403 is capable of 6 A operation at very high efficiency in a tiny 5 mm x 5 mm - 32 pin package. The CIN programmable operating frequency range of 200 kHz to Q1 VFB FB threshold 1 MHz, enables the user to optimize the solution for minimum board space and optimum efficiency. VLX VOUT The buck controller employs pseudo-fixed frequency L adaptive on-time control. This control scheme allows fast ESR transient response thereby lowering the size of the power Q2 components used in the system. FB + COUT Input Voltage Range The SiC403 requires two input supplies for normal operation: V and V . V operates over the wide range from 3 V to IN DD IN 28 V. V requires a supply voltage between 3 V to 5 V that DD Figure 1 - Output Ripple and PWM Control Method can be an external source or the internal LDO configured from V . IN The adaptive on-time control has significant advantages over traditional control methods used in the controllers today. Power Up Sequence (cid:129) Reduced component count by eliminating DCR sense or The SIC403 initiates a start up when V , V , and EN/PSV IN DD current sense resistor as no need of a sensing inductor pins are above the applicable thresholds. When using an current. external bias supply for the V voltage, it is recommended DD (cid:129) Reduced saves external components used for that the V is applied to the device only after the V voltage DD IN compensation by eliminating the no error amplifier and is present because V cannot exceed V at any time. A 10 DD IN other components. resistor must be placed between the external V supply and DD (cid:129) Ultra fast transient response because of fast loop, the V pin to avoid damage to the device during power-up DD absence of error amplifier speeds up the transient and or shutdown situations where V could exceed V DD IN response. unexpectedly. (cid:129) Predictable frequency spread because of constant on-time architecture. Shut-Down (cid:129) Fast transient response enables operation with minimum The SIC403 can be shut-down by pulling either V or DD output capacitance EN/PSV pin below its threshold. When using an external Overall, superior performance compared to fixed frequency supply voltage for V , the V pin must be deactivated DD DD architectures. while the V voltage is still present. A 10 resistor must be IN placed between the external V supply and the V pin to DD DD avoid damage to the device. On-Time One-Shot Generator (tON) and Operating When the V pin is active and EN/PSV is at low logic level, Frequency DD the output voltage discharges through an internal FET. The SiC403 have an internal on-time one-shot generator which is a comparator that has two inputs. The FB Pseudo-Fixed Frequency Adaptive On-Time Control Comparator output goes high when VFB is less than the The PWM control method used for the SiC403 is internal 750 mV reference. This feeds into the gate drive and pseudo-fixed frequency, adaptive on-time, as shown in turns on the high-side MOSFET, and also starts the one-shot figure 1. The ripple voltage generated at the output capacitor timer. The one-shot timer uses an internal comparator and a ESR is used as a PWM ramp signal. This ripple is used to capacitor. One comparator input is connected to VOUT, the trigger the on-time of the controller. other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts The adaptive on-time is determined by an internal oneshot through a current which is proportional to V . When the timer. When the one-shot is triggered by the output ripple, the IN capacitor voltage reaches V , the on-time is completed device sends a single on-time pulse to the highside OUT and the high-side MOSFET turns off. The figure 2 shows the MOSFET. The pulse period is determined by V and V ; OUT IN on-chip implementation of on-time generation. the period is proportional to output voltage and inversely proportional to input voltage. With this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate V for the present V OUT IN condition and at the selected frequency. www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 10 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix Gate R V 1 + (RωC )2 FB comparator drives V = 0.75 x 1 + 1 + RIPPLE x 1 TOP F75B0 mV -+ QQ11 OUT R2 2 1 + RR2 x+ RR1ωCTOP 2 DH VLX L VOUT 2 1 Enable and Power-Save Inputs VOUT ESR FB VIN Ontiem-sehrot DL Q2 COUT + Tabhlee EthNe/ PsSwVitc ahnindg E rNeLg uinlaptuotrs a anrde tuhsee dL DtoO e. nable or dis- Rton On-time = K x Rton x (VOUT/VIN) When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off, the output of the Figure 2 - On-Time Generation switching regulator soft-discharges the output into a 15  internal resistor via the V pin. OUT This method automatically produces an on-time that is When EN/PSV is allowed to float, the pin voltage will float to proportional to V and inversely proportional to V . 1.5 V. The switching regulator turns on with power-save OUT IN disabled and all switching is in forced continuous mode. Under steady-state conditions, the switching frequency can When EN/PSV is high (above 2 V), the switching regulator be determined from the on-time by the following equation. turns on with ultra-sonic power-save enabled. The SiC403 ultra-sonic power-save operation maintains a minimum fsw = VOUT switching frequency of 25 kHz, for applications with stringent tON x VIN audio requirements. The ENL input is used to control the internal LDO. This input The SiC403 uses an external resistor to set the ontime serves a second function by acting as a V sensor for IN UVLO which indirectly sets the frequency. The on-time can be pro- the switching regulator. grammed to provide operating frequency from 200 kHz to 1 The LDO is off when ENL is low (grounded). When ENL is a MHz using a resistor between the t pin and ground. The ON logic high but below the V threshold (2.6 V typical), IN UVLO resistor value is selected by the following equation. then the LDO is on and the switcher is off. When ENL is above the V threshold, the LDO is enabled and the Rton = (tON - 10 ns) x VIN switcher is alIsNo U eVnLOabled if the EN/PSV pin is not grounded. 25 pF x VOUT Forced Continuous Mode Operation The maximum R value allowed is shown by the following tON The SiC403 operates the switcher in Forced Continuous equation. Mode (FCM) by floating the EN/PSV pin (see figure 4). In this Rton_MAX = V1I5N _µMAIN mintoedneti oonnael doef atdh eti mpoew oethr eMr OthSaFnE toT sa viso ida lwcraoysss -ocno,n dwuitchti onno. This feature results in uniform frequency across the full load V Voltage Selection range with the trade-off being poor efficiency at light loads OUT The switcher output voltage is regulated by comparing V due to the high-frequency switching of the MOSFETs. OUT as seen through a resistor divider at the FB pin to the internal 750 mV reference voltage, see figure 3. FB ripple voltage (VFB) FB threshold (750 mV) V to FB pin OUT R 1 R Inductor DC load current 2 current On-time DH on-time is triggered when Figure 3 - Output Voltage Selection (tON) VFB reaches the FB threshold As the control method regulates the valley of the output ripple DH voltage, the DC output voltage V is off set by the output OUT ripple according to the following equation. DL R V V = 0.75 x 1 + 1 + RIPPLE OUT R 2 2 DL drives high when on-time is completed. DL remains high until VFB falls to the FB threshold. When a large capacitor is placed in parallel with R1 (C ) TOP V is shown by the following equation. Figure 4 - Forced Continuous Mode Operation OUT Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix Ultrasonic Power-Save Operation The SiC403 provides ultra-sonic power-save operation at light loads, with the minimum operating frequency fixed at 25 kHz. This is accomplished using an internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds 40 µs, DL drives high to turn the low-side MOSFET on. This draws current from V through the OUT inductor, forcing both V and V to fall. When V drops OUT FB FB to the 750 mV threshold, the next DH on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the low-side MOSFET turns on, the low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. minimum fSW ~ 25 kHz FB ripple Figure 6 - Ultrasonic Power-Save Operation Mode voltage (VFB) FB threshold (750 mV) Figure 6 shows the behavior under power-save and continuous conduction mode at light loads. Inductor (0A) Smart Power-Save Protection current Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with DH on-time is triggered when power-save-power-save enabled, this can force V to On-time OUT (tON) VFB reaches the FB threshold slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. Smart power-save prevents this condition. DH When the FB voltage exceeds 10 % above nominal (exceeds 825 mV), the device immediately disables power-save, and DL drives high to turn on the low-side MOSFET. This draws DL current from V through the inductor and causes V to OUT OUT fall. When V drops back to the 750 mV trip point, a normal FB After the 40 µs time-out, DL drives high if VFB tON switching cycle begins. has not reached the FB threshold. This method prevents a hard OVP shutdown and also cycles energy from V back to V . It also minimizes operating Figure 5 - Ultrasonic power-save Operation OUT IN power by avoiding forced conduction mode operation. Figure 7 shows typical waveforms for the smart power-save Because the on-times are forced to occur at intervals no feature. greater than 40 µs, the frequency will not fall below ~ 25 kHz. Figure 5 shows ultra-sonic power-save operation. VOUT drifts up to due to leakage current flowing into COUT VOUT discharges via inductor Benefits of Ultrasonic Power-Save Smart power save and low-side MOSFET threshold (825 mV) Having a fixed minimum frequency in power-save has some FB Normal VOUT ripple significant advantages as below: threshold (cid:129) The minimum frequency of 25 kHz is outside the audible DH and DL off range of human ear. This makes the operation of the High-side SiC403 very quiet. drive (DH) (cid:129) The output voltage ripple seen in power-save mode is Single DH on-time pulse after DL turn-off significant lower than conventional power-save, which improves efficiency at light loads. Low-side drive (DL) (cid:129) Lower ripple in power-save also makes the power DL turns on when smart Normal DL pulse after DH component selection easier. PSAVE threshold is reached on-time pulse DL turns off FB threshold is reached Figure 7 - Smart Power-Save Current Limit Protection The SiC403 features programmable current limit capability, which is accomplished by using the R of the lower DS(ON) www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 12 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix MOSFET for current sensing. The current limit is set by R pulse when the voltage at the FB pin is less than 50 % of the ILIM resistor. The R resistor connects from the I pin to the SS pin. As result, the output voltage follows the SS start volt- ILIM LIM LX pin which is also the drain of the low-side MOSFET. age. The output voltage reaches and maintains regulation When the low-side MOSFET is on, an internal ~ 10 µA when the soft start voltage is > 1.5 V. The time between the current flows from the ILIM pin and the RILIM resistor, creating first LX pulse and when VOUT meets regulation is the soft a voltage drop across the resistor. While the low-side start time (tSS). The calculation for the soft-start time is MOSFET is on, the inductor current flows through it and shown by the following equation: creates a voltage across the R . The voltage across the DS(ON) MOSFET is negative with respect to ground. t = C x 1.5 V SS SS 2.75 μA If this MOSFET voltage drop exceeds the voltage across R , the voltage at the I pin will be negative and current ILIM LIM Power Good Output limit will activate. The current limit then keeps the low-side The power good (P ) output is an open-drain output MOSFET on and will not allow another high-side on-time, GOOD until the current in the low-side MOSFET reduces enough to which requires a pull-up resistor. When the output voltage is bring the ILIM voltage back up to zero. This method regulates 10 % below the nominal voltage, PGOOD is pulled low. It is the inductor valley current at the level shown by I in held low until the output voltage returns above - 8 % of nom- LIM figure 8. inal. P is held low during start-up and will not be allowed GOOD to transition high until soft-start is completed (when V FB IPEAK reaches 750 mV) and typically 2 ms has passed. Current ILOAD PnoGmOOinDa lw, willh tircahn sisit iaolns olo twhe i fo tvheer -VvoFlBta pgien sehxuctedeodwsn + t h2r0e s%ho oldf uctor ILIM (900 mV). PGOOD also pulls low if the EN/PSV pin is low Ind when VDD is present. Time Output Over-Voltage Protection Figure 8 - Valley Current Limit Over-voltage protection becomes active as soon as the device is enabled. The threshold is set at 750 mV + 20 % Setting the valley current limit to 6 A results in a 6 A peak (900 mV). When V exceeds the OVP threshold, DL latches FB inductor current plus peak ripple current. In this situation, the high and the low-side MOSFET is turned on. DL remains average (load) current through the inductor is 6 A plus high and the controller remains off , until the EN/PSV input is one-half the peak-to-peak ripple current. toggled or V is cycled. There is a 5 µs delay built into the DD OVP detector to prevent false transitions. P is also low GOOD The internal 10 µA current source is temperature after an OVP event. compensated at 4100 ppm in order to provide tracking with the RDS(ON). The RILIM value is calculated by the following Output Under-Voltage Protection equation. When V falls 25 % below its nominal voltage (falls to FB 562.5 mV) for eight consecutive clock cycles, the switcher is RILIM = 1176 x ILIM x [0.088 x (5V - VDD) + 1] () shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN/PSV is where ILIM is in A. toggled or VDD is cycled. When selecting a value for RILIM do not exceed the absolute V UVLO, and POR DD maximum voltage value for the ILIM pin. Under-voltage lock-out (UVLO) circuitry inhibits switching and tri-states the DH/DL drivers until V rises above 3 V. DD Note that because the low-side MOSFET with low RDS(ON) is An internal Power-On Reset (POR) occurs when VDD used for current sensing, the PCB layout, solder exceeds 3 V, which resets the fault latch and soft-start connections, and PCB connection to the LX node must be counter to prepare for soft-start. The SiC403 then begins a done carefully to obtain good results. Refer to the layout soft-start cycle. The PWM will shut off if V falls below DD guidelines for information. 2.4 V. Soft-Start of PWM Regulator LDO Regulator SiC403 has a programmable soft-start time that is controlled SIC403 has an option to bias the switcher by using an by an external capacitor at the SS pin. After the controller internal LDO from V . The LDO output is connected to V IN DD meets both UVLO and EN/PSV thresholds, the controller has internally. The output of the LDO is programmable by using an internal current source of 2.75 µA flowing through the external resistors from the V pin to A . The feedback DD GND SS pin to charge the capacitor. During the start up process, pin (FBL) for the LDO is regulated to 750 mV (see figure 9). 50 % of the voltage at the SS pin is used as the reference for the FB comparator. The PWM comparator issues an on-time Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix V to FBL pin DD R LDO1 R LDO2 Figure 9 - LDO Voltage Divider The LDO output voltage is set by the following equation. ( ) VLDO = 750 mV x 1 + RLDO1 RLDO2 Figure 10 - ENL Threshold A minimum 0.1 µF capacitor referenced to A is equired GND Before start-up, the LDO checks the status of the following along with a minimum 1 µF capacitor referenced to P to GND signals to ensure proper operation can be maintained. filter the gate drive pulses. Refer to the layout guidelines section for component placement suggestions. (cid:129) ENL pin . (cid:129) V input voltage IN LDO ENL Functions The ENL input is used to control the internal LDO. When ENL When the ENL pin is high and V is above the UVLO point, is low (grounded), the LDO is off. When ENL is above the V IN IN the LDO will begin start-up. During the initial phase, when the UVLO threshold, the LDO is enabled and the switcher is also V voltage (which is the LDO output voltage) is less than enabled if EN/PSV and V meet the thresholds. DD DD 0.75 V, the LDO initiates a current-limited start-up (typically The ENL pin also acts as the switcher UVLO (undervoltage 65 mA) to charge the output capacitors while protecting from lockout) for the V supply. The V UVLO voltage is IN IN a short circuit event. When V is greater than 0.75 V but still DD programmable via a resistor divider at the V , ENL and IN less than 90 % of its final value (as sensed at the FBL pin), A pins. GND the LDO current limit is increased to ~ 115mA. When V DD If the ENL pin transitions from high to low within 2 switching has reached 90 % of the final value (as sensed at the FBL cycles and is less than 1 V, then the LDO will turn off but the pin), the LDO current limit is increased to ~ 200 mA and the switcher remains on. If the ENL goes below the VIN UVLO LDO output is quickly driven to the nominal value by the threshold and stays above 1 V, then the switcher will turn off internal LDO regulator. It is recommended that during LDO but the LDO remains on. The VIN UVLO function has a typical start-up to hold the PWM switching off until the LDO has threshold of 2.6 V on the VIN rising edge. The falling edge reached 90 % of the final value. This prevents overloading threshold is 2.4 V. the current-limited LDO output during the LDO start-up. Note that it is possible to operate the switcher with the LDO Due to the initial current limitations on the LDO during power disabled, but the ENL pin must be below the logic low up (figure 11), any external load attached to the V pin must DD threshold (0.4 V max.). In this case, the UVLO function for be limited to 20 mA before the LDO has reached 90 % of it the input voltage cannot be used. The table below final regulation value. summarizes the function of the ENL and EN pins, with respect to the rising edge of ENL. LDO Switcher EN ENL Status Status Low Low, < 0.4 V Off Off High Low, < 0.4 V Off On Low High, < 2.6 V On Off Figure 11 - LDO Start-Up High High, < 2.6 V On Off LDO Switchover Function Low High, > 2.6 V On Off The SiC403 includes a switch-over function for the LDO. The High High, > 2.6 V On On switch-over function is designed to increase efficiency by using the more efficient DC/DC converter to power the LDO Figure 10 shows the ENL voltage thresholds and their effect output, avoiding the less efficient LDO regulator when on LDO and switcher operation. possible. The switch-over function connects the V pin LDO directly to the V pin using an internal switch. When the OUT switch-over is complete the LDO is turned off, which results www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 14 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix in a power savings and maximizes efficiency. If the LDO It is not recommended to use the switch-over feature for an output is used to bias the SiC403, then after switch-over the output voltage less than 3 V since this does not provide device is self-powered from the switching regulator with the sufficient voltage for the gate-source drive to the internal LDO turned off. p-channel switch-over MOSFET. The switch-over logic waits for 32 switching cycles before it starts the switch-over. There are two methods that determine Switch-Over MOSFET Parasitic Diodes the switch-over of V to V . The switch-over MOSFET contains parasitic diodes that are LDO OUT In the first method, the LDO is already in regulation and the inherent to its construction, as shown in figure 12. DC/DC converter is later enabled. As soon as the P GOOD output goes high, the 32 cycles are started. The voltages at Scownittcrohlover Switchover the V and V pins are then compared; if the two MOSFET LDO OUT voltages are within ± 300 mV of each other, the VLDO pin VLDO VOUT connects to the V pin using an internal switch, and the OUT LDO is turned off. In the second method, the DC/DC converter is already running and the LDO is enabled. In this case the 32 cycles are started as soon as the LDO reaches 90 % of its final Parastic diode Parastic diode value. At this time, the V and V pins are compared, LDO OUT V5V and if within ± 300 mV the switch-over occurs and the LDO is turned off. Figure 12- Switch-over MOSFET Parasitic Diodes Benefits of having a switchover circuit There are some important design rules that must be followed The switchover function is designed to get maximum to prevent forward bias of these diodes. The following two efficiency out of the DC/DC converter. The efficiency for an conditions need to be satisfied in order for the parasitic LDO is very low especially for high input voltages. Using the diodes to stay off. switchover function we tie any rails connected to V LDO (cid:129) V  V through a switch directly to V . Once switchover is DD LDO OUT (cid:129) V  V complete LDO is turned off which saves power. This gives us DD OUT If either V or V is higher than V , then the respective the maximum efficiency out of the SiC403. LDO OUT DD diode will turn on and the SiC403 operating current will flow If the LDO output is used to bias the SiC403, then after through this diode. This has the potential of damaging the switchover the V self biases the SiC403 and operates in OUT device. self-powered mode. Steps to follow when using the on chip LDO to bias the ENL Pin and V UVLO IN SiC403: The ENL pin also acts as the switcher under-voltage lockout (cid:129) Always tie the VDD to VLDO before enabling the LDO for the VIN supply. The VIN UVLO voltage is programmable (cid:129) Enable the LDO before enabling the switcher via a resistor divider at the V , ENL and A pins. IN GND (cid:129) LDO has a current limit of 40 mA at start-up, so do not ENL is the enable/disable signal for the LDO. In order to connect any load between VLDO and ground implement the VIN UVLO there is also a timing requirement (cid:129) The current limit for the LDO goes up to 200 mA once the that needs to be satisfied. VLDO reaches 90 % of its final values and can easily supply If the ENL pin transitions low within 2 switching cycles and is the required bias current to the IC. < 0.4 V, then the LDO will turn off but the switcher remains on. If ENL goes below the V UVLO threshold and stays IN Switch-over Limitations on VOUT and VLDO above 1 V, then the switcher will turn off but the LDO remains Because the internal switch-over circuit always compares on. the VOUT and VLDO pins at start-up, there are limitations on The VIN UVLO function has a typical threshold of 2.6 V on the permissible combinations of VOUT and VLDO. Consider the VIN rising edge. The falling edge threshold is 2.4 V. case where VOUT is programmed to 1.5 V and VLDO is Note that it is possible to operate the switcher with the LDO programmed to 1.8 V. After start-up, the device would disabled, but the ENL pin must be below the logic low connect VOUT to VLDO and disable the LDO, since the two threshold (0.4 V maximum). voltages are within the ± 300 mV switch-over window. To avoid unwanted switch-over, the minimum difference ENL Logic Control of PWM Operation between the voltages for VOUT and VLDO should be When the ENL input is driven above 2.6 V, it is impossible to ± 500 mV. determine if the LDO output is going to be used to power the device or not. In self-powered operation where the LDO will power the device, it is necessary during the LDO start-up to hold the PWM switching off until the LDO has reached 90 % of the final value. This is to prevent overloading the Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 15 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix current-limited LDO output during the LDO start-up. Frequency Selection However, if the switcher was previously operating (with EN/ Selection of the switching frequency requires making a PSV high but ENL at ground, and V supplied externally), trade-off between the size and cost of the external filter DD then it is undesirable to shut down the switcher. components (inductor and output capacitor) and the power To prevent this, when the ENL input is taken above 2.6 V conversion efficiency. (above the V UVLO threshold), the internal logic checks the The desired switching frequency is 250 kHz which results IN P signal. If P is high, then the switcher is already from using component selected for optimum size and cost. GOOD GOOD running and the LDO will run through the start-up cycle A resistor (R ) is used to program the on-time (indirectly TON without affecting the switcher. If PGOOD is low, then the LDO setting the frequency) using the following equation. will not allow any PWM switching until the LDO output has reached 90 % of it's final value. (tON - 10 ns) x VIN Rton = 25 pF x VOUT On-Chip LDO Bias the SiC403 To select R , use the maximum value for V , and for t The following steps must be followed when using the onchip TON IN ON use the value associated with maximum V . LDO to bias the device. IN (cid:129) Connect V to V before enabling the LDO. (cid:129) The LDO hDaDs an LinDiOtial current limit of 40 mA at start-up, tON = VOUT VINMAX. x fSW therefore, do not connect any external load to V during LDO start-up. t = 318 ns at 13.2 V , 1.05 V , 250 kHz ON IN OUT (cid:129) When VLDO reaches 90 % of its final value, the LDO Substituting for RTON results in the following solution current limit increases to 200 mA. At this time the LDO may R = 154.9 k, use R = 154 k. TON TON be used to supply the required bias current to the device. Attempting to operate in self-powered mode in any other Inductor Selection configuration can cause unpredictable results and may In order to determine the inductance, the ripple current must damage the device. first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Design Procedure Higher inductor values will reduce the ripple current and When designing a switch mode power supply, the input voltage and for a given DC resistance are more efficient. voltage range, load current, switching frequency, and However, larger inductance translates directly into larger inductor ripple current must be specified. packages and higher cost. Cost, size, output ripple, and The maximum input voltage (V ) is the highest specified efficiency are all used in the selection process. INMAX input voltage. The minimum input voltage (VINMIN) is The ripple current will also set the boundary for power-save determined by the lowest input voltage after evaluating the operation. The switching will typically enter power-save voltage drops due to connectors, fuses, switches, and PCB mode when the load current decreases to 1/2 of the ripple traces. current. For example, if ripple current is 4 A then power-save The following parameters define the design: operation will typically start for loads less than 2 A. If ripple (cid:129) Nominal output voltage (V ) current is set at 40 % of maximum load current, then OUT (cid:129) Static or DC output tolerance power-save will start for loads less than 20 % of maximum current. (cid:129) Transient response The inductor value is typically selected to provide a ripple (cid:129) Maximum load current (I ) OUT current that is between 25 % to 50 % of the maximum load There are two values of load current to evaluate - continuous current. This provides an optimal trade-off between cost, load current and peak load current. Continuous load current efficiency, and transient performance. relates to thermal stresses which drive the selection of the During the DH on-time, voltage across the inductor is inductor and input capacitors. Peak load current determines (V - V ). The equation for determining inductance is instantaneous component stresses and filtering IN OUT shown next. requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design: L =(VIN - VOUT) x tON IRIPPLE (cid:129) V = 12 V ± 10 % IN Example (cid:129) V = 1.05 V ± 4 % OUT In this example, the inductor ripple current is set equal to (cid:129) f = 250 kHz SW 50 % of the maximum load current. Thus ripple current will be (cid:129) Load = 6 A maximum 50 % x 6 A or 3 A. To find the minimum inductance needed, use the V and T values that correspond to V IN ON INMAX. (13.2 - 1.05) x 318 ns L = = 1.28 µH 3 A www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 16 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix A slightly larger value of 1.3 µH is selected. This will If the load release is relatively slow, the output capacitance decrease the maximum I to 2.9 A. can be reduced. At heavy loads during normal switching, RIPPLE Note that the inductor must be rated for the maximum DC when the FB pin is above the 750 mV reference, the DL load current plus 1/2 of the ripple current. The ripple current output is high and the low-side MOSFET is on. During this under minimum VIN conditions is also checked using the time, the voltage across the inductor is approximately - VOUT. following equations. This causes a down-slope or falling di/dt in the inductor. If the load dI/dt is not much faster than the - dI/dt in the inductor, TON_VINMIN =25 pF x RTON x VOUT then the inductor current will tend to track the falling load VINMIN current. This will reduce the excess inductive energy that IRIPPLE = (VIN - VOUT) x TON must be absorbed by the output capacitor, therefore a L smaller capacitance can be used. (10.8 - 1.05) x 384 ns The following can be used to calculate the needed IRIPPLE_VIN = 1.3 µH = 2.88 A capacitance for a given dILOAD/dt: Peak inductor current is shown by the next equation. Capacitor Selection I = I + 1/2 x I The output capacitors are chosen based on required ESR LPK MAX RIPPLEMAX I = 6 + 1/2 x 2.9 = 7.45 A and capacitance. The maximum ESR requirement is LPK Rate of change of load current = dI /dt controlled by the output ripple requirement and the DC LOAD tolerance. The output voltage has a DC value that is equal to IMAX = maximum load release = 6 A the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a L x I L P K - I M A X x dt change in DC voltage at the output. COUT = ILPK x V2O (UVTPK -d VlLOOUATD) The design goal is that the output voltage regulation be ± 4 % under static conditions. The internal 500 mV reference Example tolerance is 1 %. Allowing 1 % tolerance from the FB resistor divider, this allows 2 % tolerance due to V ripple. Load dlLOAD =2.5 A OUT dt µs Since this 2 % error comes from 1/2 of the ripple voltage, the allowable ripple is 4 %, or 42 mV for a 1.05 V output. This would cause the output current to move from 10 A to The maximum ripple current of 4.4 A creates a ripple voltage zero in 4 µs as shown by the following equation. across the ESR. The maximum ESR value allowed is shown by the following equations. 7.45 6 1.3 µH x - x 1 µs 1.05 2.5 VRIPPLE 42 mV COUT = 7.45 x 2 (1.15 - 1.05) ESRMAX = = IRIPPLEMAX 2.9 A COUT = 254 µF ESRMAX = 9.5 mΩ Note that C is much smaller in this example, 254 µF OUT compared to 328 µF based on a worst-case load release. To The output capacitance is usually chosen to meet transient meet the two design criteria of minimum 254 µF and requirements. A worst-case load release, from maximum maximum 9 m ESR, select two capacitors rated at 150 µF load to no load at the exact moment when inductor current is and 18 m ESR. at the peak, determines the required capacitance. If the load It is recommended that an additional small capacitor be release is instantaneous (load changes from maximum to placed in parallel with C in order to filter high frequency OUT zero in < 1 µs), the output capacitor must absorb all the switching noise. inductor's stored energy. This will cause a peak voltage on the capacitor according to the following equation. Stability Considerations 1 L (IOUT + 2 x IRIPPLEMAX)2 Unstable operation is possible with adaptive on-time COUT_MIN = controllers, and usually takes the form of double-pulsing or (VPEAK)2 - (VOUT)2 ESR loop instability. Assuming a peak voltage V of 1.150 (100 mV rise upon Double-pulsing occurs due to switching noise seen at the FB PEAK load release), and a 10 A load release, the required input or because the FB ripple voltage is too low. This causes capacitance is shown by the next equation. the FB comparator to trigger prematurely after the 250 ns minimum off-time has expired. In extreme cases the noise 1 can cause three or more successive on-times. 1.3 µH (6 + x 2.9)2 COUT_MIN = 2 Double-pulsing will result in higher ripple voltage at the (1.15)2 - (1.05)2 output, but in most applications it will not affect operation. COUT_MIN = 328 µF Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 17 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix This form of instability can usually be avoided by providing For applications using ceramic output capacitors, the ESR is the FB pin with a smooth, clean ripple signal that is at least normally too small to meet the above ESR criteria. In these 10 mV , which may dictate the need to increase the ESR of applications it is necessary to add a small virtual ESR p-p the output capacitors. It is also imperative to provide a proper network composed of two capacitors and one resistor, as PCB layout as discussed in the Layout Guidelines section. shown in figure 14. This network creates a ramp voltage across C , analogous to the ramp voltage generated across L CTOP the ESR of a standard capacitor. This ramp is then capacitive-coupled into the FB pin via capacitor C . C L VOUT R1 To FB pin High- side R2 RL CL R1 CC Low- COUT side Figure 13 - Capacitor Coupling to FB Pin Another way to eliminate doubling-pulsing is to add a small R2 FB (~ 10 pF) capacitor across the upper feedback resistor, as pin shown in figure 13. This capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. Adding the C capacitor will couple more ripple into FB to help TOP eliminate the problem. An optional connection on the PCB Figure 14 - Virtual ESR Ramp Current should be available for this capacitor. Dropout Performance ESR loop instability is caused by insufficient ESR. The The output voltage adjusts range for continuous-conduction details of this stability issue are discussed in the ESR operation is limited by the fixed 250 ns (typical) minimum Requirements section. The best method for checking off-time of the one-shot. When working with low input stability is to apply a zero-to-full load transient and observe voltages, the duty-factor limit must be calculated using the output voltage ripple envelope for overshoot and ringing. worst-case values for on and off times. The duty-factor Ringing for more than one cycle after the initial step is an limitation is shown by the next equation. indication that the ESR should be increased. One simple way to solve this problem is to add trace TON(MIN) resistance in the high current output path. A side effect of DUTY = adding trace resistance is output decreased load regulation. TON(MIN) x TOFF(MAX) The inductor resistance and MOSFET on-state voltage drops ESR Requirements must be included when performing worst-case dropout A minimum ESR is required for two reasons. One reason is duty-factor calculations. to generate enough output ripple voltage to provide10 mV p-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the following equation. 3 ESRMIN = 2 x π x COUT x fSW www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 18 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix System DC Accuracy (V Controller) Switching Frequency Variations OUT Three factors affect V accuracy: the trip point of the FB The switching frequency will vary depending on line and load OUT error comparator, the ripple voltage variation with line and conditions. The line variations are a result of fixed load, and the external resistor tolerance. The error propagation delays in the on-time one-shot, as well as comparator off set is trimmed so that under static conditions unavoidable delays in the external MOSFET switching. As it trips when the feedback pin is 750 mV, 1 %. V increases, these factors make the actual DH on-time IN The on-time pulse from the SiC403 in the design example is slightly longer than the ideal on-time. The net effect is that calculated to give a pseudo-fixed frequency of 250 kHz. frequency tends to falls slightly with increasing input voltage. Some frequency variation with line and load is expected. The switching frequency also varies with load current as a This variation changes the output ripple voltage. Because result of the power losses in the MOSFETs and the inductor. constant on-time converters regulate to the valley of the For a conventional PWM constant-frequency converter, as output ripple, ½ of the output ripple appears as a DC load increases the duty cycle also increases slightly to regulation error. For example, if the output ripple is 50 mV compensate for IR and switching losses in the MOSFETs with V = 6 V, then the measured DC output will be 25 mV and inductor. IN above the comparator trip point. If the ripple increases to A constant on-time converter must also compensate for the 80 mV with VIN = 25 V, then the measured DC output will be same losses by increasing the effective duty cycle (more 40 mV above the comparator trip. The best way to minimize time is spent drawing energy from V as losses increase). IN this effect is to minimize the output ripple. The on-time is essentially constant for a given V /V OUT IN To compensate for valley regulation, it may be desirable to combination, to off set the losses the off-time will tend to use passive droop. Take the feedback directly from the reduce slightly as load increases. The net effect is that output side of the inductor and place a small amount of trace switching frequency increases slightly with increasing load. resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1 % feedback resistors contributes up to 1 % error. If tighter DC accuracy is required, 0.1 % resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 19 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix SIC403 EVALUATION BOARD SCHEMATIC VoVo VO_GNDVO_GND B3B3 1 1 B4B4 P5P5 VCTLVCTL P11P11VO_GNDVO_GND 1 1 P10P10VOUTVOUT 1 C4C422uF22uF C3C322uF22uF R10R1010K10K R23R237k157k15 C2C222uF22uF C1C122uF22uF C25C2568pF68pF R5R5100K100K C7C70.1uF0.1uF Q1Q1Si4812BDYSi4812BDY C17C17C18C18220uF220uF220uF220uF(cid:0)(cid:0)(cid:0)(cid:0) P3P31 Step_I_SenseStep_I_Sense R41R01R41R01P4P41 LDTRGLDTRG VOUT (cid:0)(cid:0)C16C16C21C21C15C15 220uF220uF10uF10uF10uF10uF C14C14 0.1uF0.1uF 1u *1u * C19C19 J5J5Probe Test PinProbe Test Pin L10.78uHL10.78uH R9R9** C24C2410n *10n * R1310KR1310K 5 R51R511R1R C36C361nF1nF 234 1 R15R151.5K1.5K R14100R14100 0R0RC6C60.1uF0.1uF tsb13xl 33LX252423R810KR810K28 27ILIM1FB 26PGDC30C3031100pF100pF NOT R30R30154K154K 1VDD P7P7PGOODPGOOD C5C50.1uF0.1uFC37C37P6P610nF10nFENLENL 1R5231K6R5231K6 VSPR7R7ENL_TNSoR6100KR6100KVBE4229831122 TCCLTV6VINNSUSNNVINLXBSTBEOP9/VVINN10EVINLX11C13C13VINLX340.01uF0.01uFLXVINU1U1LX3VDDSiC401/2/3SiC401/2/3VDDLXS7SOFTSOFTILIMFBDDDDDDDDDDD5FBLFBLPGDNNNNNNNNNNNGGGGGGGGGGGTONAPPPPPPPPAA 02109876554C29C29322211111322nF22nF R390RR390R 1 R1R1300K300K R2R2300K300K C11C110.1uF0.1uF R29R2910K10K M4M4 1 R12R1257.6K57.6K VDD 1P2P2EN_PSVEN_PSV C10C10C22C22C20C20220uF220uF220uF220uF220uF220uF(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0) C28C28C27C270.1uF0.1uF4.7uF4.7uF M3M3 111 P9P9VIN_GNDVIN_GND 1 (cid:0)(cid:0) C12C12150uF150uF C26C264.7uF4.7uF M2M2 1 P8P8VINVIN 1 1 1 1 1 M1M1 1 B1B1VINVIN B2B2VIN_GNDVIN_GND P1P1VDDVDD Figure 15. Evaluation Board Schematic www.vishay.com For technical support, please contact: analogswitchtechsupport@vishay.com Document Number: 66550 20 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix BILL OF MATERIALS Item Qty. Reference Value Voltage PCB Footprint Part Number Manufacturer 1 1 B1 VIN SOLDER-BANANA 575-4 Keystone 2 1 B2 VIN_GND SOLDER-BANANA 575-4 Keystone 3 1 B3 Vo SOLDER-BANANA 575-4 Keystone 4 1 B4 VO_GND SOLDER-BANANA 575-4 Keystone 5 4 C1, C2, C3, C4 22 µF 16 V SM/C_1210 GRM32ER71C226ME18L Murata 6 1 C5 0.1 µF 16 V SM/C_0402 EMK105BJ104KV-F Taiyo Yuden 7 1 C6 0.1 µF 50 V SM/C_0603 VJ0603Y104KXACW1BC Murata 8 3 C7, C11, C14 0.1 µF 50 V SM/C_0603 VJ0603Y104KXACW1BC Vishay 9 3 C10, C20, C22 220 µF 25 V 595D-D 593D227X0010E2TE3 Vishay 10 1 C12 150 µF 35 V D8X11.5-D0.6X3.5 EEU-FM1V151 Panasonic 11 1 C13 0.01 µF 50 V SM/C_0402 VJ0402Y103KXACW1BC Vishay 12 2 C15, C21 10 µF 16 V SM/C_1206 C3216X7R1C106M TDK 13 3 C16, C17, C18 220 µF 10 V 595D-D 593D227X0010E2TE3 Vishay 14 1 C19 1 µ SM/C_0603 15 1 C24 10 n SM/C_0603 16 1 C25 68 pF 50 V SM/C_0402 0402YA680JAT2A AVX TAIYO 17 2 C26, C27 4.7 µF 10 V SM/C_0805 LMK212B7475KG-T YUDEN 18 1 C28 0.1 µF 10 V SM/C_0603 GRM155R61A105KE19D Murata 19 1 C29 22 nF 16 V SM/C_0603 Murata 20 1 C30 100 pF 50 V SM/C_0402 VJ0402Y101KXACW1BC Vishay 21 1 C36 1 nF 50 V SM/C_0402 C0402C102K3RA Vishay 22 1 C37 10 nF 50 V SM/C_0402 VJ0402A103KXACW1BC Vishay 23 1 J5 Probe Test Pin LECROY PROBE PIN PK007-015 24 1 L1 0.78 µH IHLP4040 IHLP4040DZERR78M11 Vishay 25 4 M1, M2, M3, M4 M HOLE2 STACKING SPACER 8834 Keystone 26 1 P1 VDD Probe Hook - d76 1573-3 Keystone 27 1 P2 EN_PSV Probe Hook - d76 1573-3 Keystone 28 1 P3 Step_I_Sense Probe Hook - d76 1573-3 Keystone 29 1 P4 LDTRG Probe Hook - d76 1573-3 Keystone 30 1 P5 VCTL Probe Hook - d76 1573-3 Keystone 31 1 P6 ENL Probe Hook - d76 1573-3 Keystone 32 1 P7 PGOOD Probe Hook - d76 1573-3 Keystone 33 1 P8 VIN Probe Hook - d76 1573-3 Keystone 34 1 P9 VIN_GND Probe Hook - d76 1573-3 Keystone 35 1 P10 VOUT Probe Hook - d76 1573-3 Keystone 36 1 P11 VO_GND Probe Hook - d76 1573-3 Keystone 37 1 Q1 Si4812BDY 30 V SO-8 Si4812BDY Vishay 38 1 R1 300K 50 V SM/C_0603 CRCW060310K0FKEA Vishay 39 1 R2 300K 50 V SM/C_0603 CRCW06030000FKEA Vishay 40 1 R4 1R01 200 V C_2512 CRCW25121R00FKTA Vishay 41 2 R5, R6 100K 50 V SM/C_0603 CRCW0603100KFKEA Vishay 42 1 R7 0R 50 V SM/C_0603 CRCW06030000Z0EA Vishay Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 21 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Semiconductors New Product BILL OF MATERIALS 43 3 R8, R10, R29 10K 50 V SM/C_0603 CRCW060310K0FKEA Vishay 44 1 R9  SM/C_0603 45 1 R12 57.6K 50 V SM/C_0603 CRCW060357K6FKEA Vishay 46 1 R13 10K 50 V SM/C_0402 CRCW040210K0FKED Vishay 47 1 R14 100 50 V SM/C_0402 CRCW040210K0FKED Vishay 48 1 R15 1.5K SM/C_0603 CRCW06031K50FKEA Vishay 49 1 R23 7k15 SM/C_0603 CRCW06037K15FKEA Vishay 50 1 R30 154K SM/C_0603 CRCW0603154KFKEA Vishay 51 1 R39 0R SM/C_0402 CRCW04020000Z0ED Vishay 52 1 R51 1R SM/C_0805 CRCW08051R00FNEA Vishay 53 1 R52 31K6 50 V SM/C_0603 CRCW060331K6FKEA Vishay 54 1 U1 SiC401/2/3 MLPQ5x5-32L Vishay www.vishay.com Document Number: 66550 22 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Siliconix PCB LAYOUT OF THE EVALUATION BOARD Figure 14. Top Layer Figure 15. Middle Layer 1 Figure 16. Middle Layer 2 Figure 17. Bottom Layer Figure 15. Top Component Figure 17. Bottom Component Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vi- www.vishay.com S12-0628-Rev. C, 19-Mar-12 23 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403 Vishay Semiconductors New Product PACKAGE DIMENSIONS AND MARKING INFO C C 0 5.000 ± 0.075 B 0.1 0.09.0005 0± 0.100 3.480 ± 0.100 A 0.000 17 R Full 24 ± 0.075 1.970 ± 0.100 C1L6 25 0.400 ± 0.100 050 ± 0.100 0 1. 00 0.460 5. + 9 32 R0.200 Bare Copper 8 CL Pin 1 I.D. C Pin # 1 (Laser Marked) 8 1.485 ± 0.100 1.660 ± 0.100 0 0. Top View 0.250 ± 0.050 0.500 0.10 CAB 0.460 Bottom View 0.200 ref. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66550. www.vishay.com Document Number: 66550 24 S12-0628-Rev. C, 19-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information Vishay Siliconix PowerPAK® MLP55-32L CASE OUTLINE 0.08C 5 6 2x A bPyin m 1a drkoitng A 0.10CA A1 D2 - 1 2x D A2 0.360 D2 - 2 Pin #1 identification 0.10CB 25 32 R0.200 24 1 e 2 E (5 3m2mL Tx/ S5 LmPm) A10BC E2 - 1 0.45 E2 - Nd-1) XeRef. 40. 2 - 3 ( E 17 8 B 16 9 b D2 - 4 D2 - 3 C (Nd-1) Xe L Ref. 0.36 D4 Top View Side View Bottom View MILLIMETERS INCHES DIM MIN. NOM. MAX. MIN. NOM. MAX. A 0.80 0.85 0.90 0.031 0.033 0.035 A1(8) 0.00 - 0.05 0.000 - 0.002 A2 0.20 REF. 0.008 REF. b(4) 0.20 0.25 0.30 0.078 0.098 0.011 D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC E 5.00 BSC 0.196 BSC L 0.35 0.40 0.45 0.013 0.015 0.017 N(3) 32 32 Nd(3) 8 8 Ne(3) 8 8 D2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 D2 - 2 1.00 1.05 1.10 0.039 0.041 0.043 D2 - 3 1.00 1.05 1.10 0.039 0.041 0.043 D2 - 4 1.92 1.97 2.02 0.075 0.077 0.079 E2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 E2 - 2 1.61 1.66 1.71 0.063 0.065 0.067 E2 - 3 1.43 1.48 1.53 0.056 0.058 0.060 ECN: T-08957-Rev. A, 29-Dec-08 DWG: 5983 Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. Document Number: 64714 www.vishay.com Revision: 29-Dec-08 1

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