SiC402A, SiC402BCD www.vishay.com Vishay Siliconix 10 A microBUCK® SiC402A/B Integrated Buck Regulator with Programmable LDO DESCRIPTION FEATURES The Vishay Siliconix SiC402A/B an advanced stand-alone • High efficiency > 95 % synchronous buck regulator featuring integrated power • 10 A continuous output current capability MOSFETs, bootstrap switch, and a programmable LDO in a • Integrated bootstrap switch space-saving PowerPAK MLP55-32L pin packages. • Programmable 200 mA LDO with bypass logic The SiC402A/B are capable of operating with all ceramic • Temperature compensated current limit solutions and switching frequencies up to 1 MHz. The • All ceramic solution enabled programmable frequency, synchronous operation and • Pseudo fixed-frequency adaptive on-time control selectable power-save allow operation at high efficiency • Programmable input UVLO threshold across the full range of load current. The internal LDO may • Independent enable pin for switcher and LDO be used to supply 5 V for the gate drive circuits or it may be • Selectable ultra-sonic power-save mode (SiC402A) bypassed with an external 5 V for optimum efficiency and • Selectable power-save mode (SiC402B) used to drive external n-channel MOSFETs or other loads. • Programmable soft-start and soft-shutdown Additional features include cycle-by-cycle current limit, • 1 % internal reference voltage voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable • Power good output power-save. The Vishay Siliconix SiC402A/B also provides • Over-voltage and under-voltage protections an enable input and a power good output. • PowerCAD simulation software available at www.vishay.com/power-ics/powercad-list/ • Material categorization: for definitions of compliance PRODUCT SUMMARY please see www.vishay.com/doc?99912 Input Voltage Range 3 V to 28 V APPLICATIONS Output Voltage Range 0.6 V to V x 0.75 a IN • Notebook, desktop, and server computers Operating Frequency 200 kHz to 1 MHz • Digital HDTV and digital consumer applications Continuous Output Current 10 A • Networking and telecommunication equipment Peak Efficiency 95 % • Printers, DSL, and STB applications Package PowerPAK MLP55-32L • Embedded applications Note • Point of load power supplies a. See “High Output Voltage Operation” section TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS 3.3 V EN/PSV (Tri-State) LDO_EN PGOOD VOUT V ENL TONAGND EN\PS LX ILIM PGOODLX 32 31 30 29 28 27 26 25 FB LX VOUT 1 24 VOUT PAD 1 LX 2 23 VDD 3 AGND 22 PGND AGND PAD 3 PGND 4 21 FBL 5 LX 20 PGND VIN VIN 6 PAD 2 19 PGND SS 7 VIN 18 PGND BST 8 17 PGND 9 10 11 12 13 14 15 16 N N N CX C D D VI VI VI NL N GN GN PP Typical Application Circuit for SiC402A/B (PowerPAK MLP55-32L) S14-2048-Rev. C, 13-Oct-14 1 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix PIN CONFIGURATION (Top View) V ENL tON AGND EN\PS LX ILIM PGOOD LX 32 31 30 29 28 27 26 25 FB 1 24 LX PAD 1 VOUT 2 23 LX VDD 3 AGND 22 PGND AGND 4 PAD 3 21 PGND FBL 5 LX 20 PGND PAD 2 VIN 6 19 PGND SS 7 VIN 18 PGND BST 8 17 PGND 9 10 11 12 13 14 15 16 N N N C X C D D VI VI VI N L N GN GN P P SiC402A/B Pin Configuration (Top View) PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION Feedback input for switching regulator used to program the output voltage - connect to an external 1 FB resistor divider from V to A . OUT GND Switcher output voltage sense pin - also the input to the internal switch-over between V and 2 V OUT OUT V . The voltage at this pin must be less than or equal to the voltage at the V pin. LDO DD Bias supply for the IC - when using the internal LDO as a bias power supply, V is the LDO output. 3 V DD DD When using an external power supply as the bias for the IC, the LDO output should be disabled. 4, 30, PAD 1 A Analog ground GND Feedback input for the internal LDO - used to program the LDO output. Connect to an external 5 FBL resistor divider from V to A . DD GND 6, 9 to 11, PAD 2 V Input supply voltage IN 7 SS The soft start ramp will be programmed by an internal current source charging a capacitor on this pin. Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply 8 BST for the high-side gate drive. 12, 14 NC No connection 13 LXBST LX Boost - connect to the BST capacitor. 23 to 25, PAD 3 LX Switching (phase) node 15 to 22 P Power ground GND Open-drain power good indicator - high impedance indicates power is good. An external pull-up 26 P GOOD resistor is required. 27 I Current limit sense pin - used to program the current limit by connecting a resistor from I to LXS. ILIM LIM 28 LXS LX sense - connects to R ILIM Enable/power-save input for the switching regulator - connect to A to disable the switching GND 29 EN/PSV regulator, connect to V to operate with power-save mode and float to operate in forced DD continuous mode. 31 t On-time programming input - set the on-time by connecting through a resistor to A . ON GND Enable input for the LDO - connect ENL to A to disable the LDO. Drive with logic signal for logic 32 ENL GND control, or program the V UVLO with a resistor divider between V , ENL, and A . IN IN GND ORDERING INFORMATION P/N MARKING PART NUMBER PACKAGE (LINE 1: P/N) II SiC402ACD-T1-GE3 PowerPAK SiC402A SiC402BCD-T1-GE3 MLP55-32L SiC402B Format: Fyww SiC402DB Reference Board Line 1: Dot Line 2: P/N Line 3: Siliconix Logo + LOT Code + ESD Symbol Line 4: Factory Code + Year Code + Work Week Code S14-2048-Rev. C, 13-Oct-14 2 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM NC NC SiC402A/B Functional Block Diagram ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) A ELECTRICAL PARAMETER CONDITIONS LIMITS UNIT V to P -0.3 to +30 IN GND V to V -0.4 max. IN DD LX to P -0.3 to +30 GND LX (transient < 100 ns) to P -2 to +30 GND V to P -0.3 to +6 DD GND EN/PSV, P , I , SS, V , FB, FBL Reference to A -0.3 to +(V + 0.3) V GOOD LIM OUT GND DD t to P -0.3 to +(V - 1.5) ON GND DD to LX -0.3 to +6 BST to P -0.3 to +35 GND ENL -0.3 to V IN A to P -0.3 to +0.3 GND GND Temperature Maximum Junction Temperature 150 °C Storage Temperature -65 to 150 Power Dissipation Junction to Ambient Thermal Impedance (R ) b IC section 50 °C/W thJA Ambient temperature = 25 °C 3.4 Maximum Power Dissipation W Ambient temperature = 100 °C 1.3 ESD Protection HBM 2 kV CDM 1   Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. S14-2048-Rev. C, 13-Oct-14 3 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V) PARAMETER MIN. TYP. MAX. UNIT V 3 - 28 IN V to P 3 - 5.5 V DD GND V 0.6 - V x 0.75 OUT IN Temperature Operating Junction Temperature -40 to 125 °C Recommended Ambient Temperature -40 to 85 ELECTRICAL SPECIFICATIONS TEST CONDITIONS UNLESS SPECIFIED LIMITS V = 12 V, T = +25 °C for typ., IN A UNIT PARAMETER SYMBOL -40 °C to +85 °C for min. and max., T = < 125 °C, V = +5 V, MIN. TYP. MAX. J DD typical application circuit Input Supplies Input Supply Voltage V 3 - 28 IN V V 3 - 5.5 DD DD Sensed at ENL pin, rising 2.4 2.6 2.95 V UVLO Threshold a V IN UVLO Sensed at ENL pin, falling 2.23 2.4 2.57 V V UVLO Hysteresis V - 0.25 - IN UVLO, HYS Measured at V pin, rising 2.5 - 3 DD V UVLO Threshold V DD UVLO Measured at V pin, falling 2.4 - 2.9 DD V UVLO Hysteresis V - 0.2 - DD UVLO, HYS EN/PSV, ENL = 0 V, V = 28 V - 10 20 IN V Supply Current I IN IN Standby mode: ENL = V , EN/PSV = 0 V - 160 - μA DD EN/PSV, ENL = 0 V - 190 300 SiC402A, EN/PSV = V5V, no load - 0.3 - (f = 25 kHz), V > 0.6 V b SW FB SiC402B, EN/PSV = V5V, no load - 0.7 - V Supply Current I V > 0.6 V b DD DD FB mA V = 5 V, f = 250 kHz, DD SW - 8 - EN/PSV = floating, no load b V = 3 V, f = 250 kHz, DD SW - 5 - EN/PSV = floating, no load b FB On-Time Threshold Static V and load 0.594 0.600 0.606 V IN Continuous mode operation - 1000 Frequency Range f kHz sw Minimum f , (SiC402A only) - 25 - SW Bootstrap Switch Resistance - 10 -  Timing Continuous mode operation V = 15 V, On-Time t IN 999 1110 1220 ON VOUT = 5 V, fSW = 300 kHz, RtON = 133 k Minimum On-Time b tON min. - 80 - ns V = 5 V - 250 - Minimum Off-Time b t DD OFF min. V = 3 V - 370 - DD Soft Start Soft Start Current b I - 3 - μA SS Soft Start Voltage b V When V reaches regulation - 1.5 - V SS OUT Analog Inputs/Outputs VOUT Input Resistance - 500 - k Current Sense Zero-Crossing Detector Threshold Voltage LX-P -3 - +3 mV GND S14-2048-Rev. C, 13-Oct-14 4 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS TEST CONDITIONS UNLESS SPECIFIED LIMITS V = 12 V, T = +25 °C for typ., IN A UNIT PARAMETER SYMBOL -40 °C to +85 °C for min. and max., T = < 125 °C, V = +5 V, MIN. TYP. MAX. J DD typical application circuit Power Good Upper limit, V > internal 600 mV PG_V FB - +20 - TH_UPPER reference Power Good Threshold Voltage % Lower limit, V < internal 600 mV PG_V FB - -10 - TH_LOWER reference Start-Up Delay Time PG_T VDD = 5 V, Css = 10 nF - 12 - ms (between PWM enable and PGOOD high) d VDD = 3 V, Css = 10 nF - 7 - Fault (noise-immunity) Delay Time b PG_I - 5 - μs CC Leakage Current PG_I - - 1 μA LK Power Good On-Resistance PG_RDS-ON - 10 -  Fault Protection V = 5 V, R = 4460, DD ILIM 8.5 10 11.5 Vally Current Limit c ILIM TJ = 0 °C to +125 °C A V = 3 V, R = 4460 - 8.5 - DD ILIM I Source Current - 10 - μA LIM I Comparator Offset Voltage V With respect to A -10 0 +10 mV LIM ILM-LK GND V with respect to Internal 600 mV Output Under-Voltage Fault V FB - -25 - OUV_Fault reference, 8 consecutive clocks Smart Power-Save Protection P VFB with respect to internal 600 mV - +10 - % Threshold b SAVE_VTH reference V with respect to internal 600 mV Over-Voltage Protection Threshold FB - +20 - reference Over-Voltage Fault Delay b t - 5 - μs OV-Delay Over Temperature Shutdown b T 10 °C hysteresis - 150 - °C Shut Logic Inputs / Outputs Logic Input High Voltage V 1 - - IH Logic Input Low Voltage V - - 0.4 IL EN/PSV Input for P Operation b V = 5 V 2.2 - 5 SAVE DD V EN/PSV Input for Forced Continuous 1 - 2 Operation b EN/PSV Input for Disabling Switcher 0 - 0.4 EN/PSV Input Bias Current I EN/PSV = V or A -10 - +10 EN DD GND ENL Input Bias Current ENL = V = 28 V - 10 18 μA IN FBL, FB Input Bias Current FBL_I FBL, FB = V or A -1 - +1 LK DD GND Linear Dropout Regulator FBL b V - 0.75 - V LDO ACC Short-circuit protection, - 65 - V =12 V, V < 0.75 V IN DD Start-up and foldback, V = 12 V, LDO Current Limit LDO_I IN - 115 - mA LIM 0.75 < V < 90 % of final V value DD DD Operating current limit, V = 12 V, IN 135 200 - V > 90 % of final V value DD DD V to V Switch-Over Threshold d V -130 - +130 LDO OUT LDO-BPS mV V to V Non-Switch-Over Threshold d V -500 - +500 LDO OUT LDO-NBPS VLDO to VOUT Switch-Over Resistance RLDO VOUT = 5 V - 2 -  From V to V V = +5 V, LDO Drop Out Voltage e IN DD, DD - 1.2 - V I = 100 mA VLDO Notes a. V UVLO is programmable using a resistor divider from V to ENL to A . The ENL voltage is compared to an internal reference. IN IN GND b. Typical value measured on standard evaluation board. c. SiC402A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout. d. The switch-over threshold is the maximum voltage differential between the V and V pins which ensures that V will internally DD OUT LDO switch-over to V . The non-switch-over threshold is the minimum voltage differential between the V and V pins which ensures that OUT LDO OUT V will not switch-over to V . LDO OUT e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point. S14-2048-Rev. C, 13-Oct-14 5 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 100 100 95 95 90 90 85 85 %) 80 %) 80 (ency 75 ncy ( 75 PSM Effici 6750 VIN = 5 V Efficie 6750 CCM 60 VIN = 12 V 60 55 55 50 50 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) IOUT (A) Fig. 1 - PSM Efficiency - V vs. Load Fig. 4 - Efficiency - PSM vs. CCM IN (V = 3.3 V, V = 1.5 V) (V = 3.3 V, V = 1.5 V, V = 12 V) DD OUT DD OUT IN 100 100 95 95 90 90 85 85 %) 80 %) 80 Efficiency ( 677505 VVVIIINNN === 1518 2V VV Efficiency ( 677505 PCSCMM 60 60 55 55 50 50 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) IOUT (A) Fig. 2 - PSM Efficiency - V vs. Load Fig. 5 - Efficiency - PSM vs. CCM IN (V = 5 V, V = 1.5 V) (V = 5 V, V = 1.5 V, V = 12 V) DD OUT DD OUT IN 100 100 95 95 90 90 85 85 %) Effency (ici 67785050 VVVIIINNN === 511 28V VV Efficiency (%) 67785050 VDD = 3.3 V VDD = 5 V 60 60 55 55 50 50 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) IOUT (A) Fig. 3 - PSM Efficiency - V vs. Load Fig. 6 - PSM Efficiency - V 3.3 V vs. 5 V IN DD (V = 5 V, V = 1.5 V) (V = 1.5 V, V = 12 V) DD OUT OUT IN S14-2048-Rev. C, 13-Oct-14 6 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix 1.53 1.54 VIN = 18 V VIN = 12 V 1.53 1.52 VIN = 12 V VIN = 5 V VIN = 5 V 1.52 1.51 V)V) V)V) 1.51 V ( (OUTOUT 1.50 V ( (OUTOUT 1.50 1.49 1.49 1.48 1.48 1.47 1.47 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 IOOUUTT ((AA)) IOOUUTT ((AA)) Fig. 7 - Load Regulation - FCM Fig. 10 - Load Regulation - FCM (V = 5 V, V = 1.5 V) (V = 3.3 V, V = 1.5 V) DD OUT DD OUT 1.53 1.54 VIN = 18 V VIN = 12 V 1.53 1.52 VIN = 12 V VIN = 5 V VIN = 5 V 1.52 1.51 V (V) (V)OUTOUT 1.50 V (V) (V)OUTOUT 11..5501 1.49 1.49 1.48 1.48 1.47 1.47 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 IOOUUTT ((AA)) IOOUUTT ((AA)) Fig. 8 - Load Regulation - PSM Fig. 11 - Load Regulation - PSM (V = 5 V, V = 1.5 V) (V = 3.3 V, V = 1.5 V) DD OUT DD OUT 40 0 100 350 95 300 cy (K)Hz 2205 00 ncy (%) 90 n e Freueq 15 0 FCM Effici 85 VVOOUUTT == 35 . 3V V 100 VOUT =2 . 5 V PSM 80 50 VOUT =1 . 5 V VOUT = 1 V 0 75 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) I (A) OUT OUT Fig. 9 - Switching Frequency - PSM vs. FCM Fig. 12 - Switching Frequency - PSM vs. FCM (V = 5 V, V = 1.5 V, V = 12 V) (V = 5 V, V = 12 V) DD OUT IN DD IN S14-2048-Rev. C, 13-Oct-14 7 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix Fig. 13 - Start-Up - EN/PSV Fig. 16 - Shutdown - EN/PSV (V = 5 V, V = 12 V, V = 1.5 V, I = 0 A) (V = 5 V, V = 1.5 V, I = 0 A) DD IN OUT OUT DD IN OUT Fig. 14 - Start-Up (Pre-Bias) - EN/PSV Fig. 17 - Ultra-sonic PSM - SiC402ACD (V = 5 V, V = 12 V, V = 1.5 V, I = 0 A) (V = 5 V, V = 12 V, V = 1.5 V, I = 0 A) DD IN OUT OUT DD IN OUT OUT Fig. 15 - Start-Up (Pre-Bias) - EN/PSV Fig. 18 - Forced Continuous Mode - SiC402ACD (V = 5 V, V = 1.5 V, I = 0 A) (V = 5 V, V = 12 V, V = 1.5 V, I = 10 A) DD IN OUT DD IN OUT OUT S14-2048-Rev. C, 13-Oct-14 8 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix Fig. 19 - Transient Response - PSM Rising (V = 5 V, Fig. 21 - Transient Response - PSM Falling (V = 5 V, DD DD V = 12 V, V = 1.5 V, I = 0.5 A to 8.5 A, dI/dt = 1 A/μs) V = 12 V, V = 1.5 V, I = 8.5 A to 0.5 A, dI/dt = 1 A/μs) IN OUT OUT IN OUT OUT Fig. 20 - Transient Response - FCM (V = 5 V, Fig. 22 - Thermal Shutdown - 146 °C DD V = 12 V, V = 1.5 V, I = 2.5 A to 10 A, dI/dt = 1 A/μs) (V = 12 V, V = 2.5 A to 10 A, dI/dt = 1 A/μs) IN OUT OUT IN OUT S14-2048-Rev. C, 13-Oct-14 9 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix OPERATIONAL DESCRIPTION Device Overview The SiC402A/B is a step down synchronous DC/DC buck VIN tON converter with integrated power MOSFETs and a 200 mA capable programmable LDO. The device is capable of VLX 10 A operation at very high efficiency. A space saving CIN 5 x 5 (mm) 32-pin package is used. The programmable Q1 VFB FB threshold operating frequency of up to 1 MHz enables optimizing the configuration for PCB area and efficiency. VLX VOUT The buck controller uses a pseudo-fixed frequency adaptive L on-time control. This control method allows fast transient ESR response which permits the use of smaller output Q2 capacitors. FB + Input Voltage Requirements COUT The SiC402A/B requires two input supplies for normal operation: V and V . V operates over a wide range from IN DD IN 3 V to 28 V. V requires a 3 V to 5.5 V supply input that can DD be an external source or the internal LDO configured to Fig. 23 - PWM Control Method, V Ripple OUT supply 3 V to 5.5 V from V . IN  Power Up Sequence The adaptive on-time is determined by an internal one-shot timer. When the one-shot is triggered by the output ripple, When the SiC402A/B uses an external power source at the the device sends a single on-time pulse to the highside V pin, the switching regulator initiates the start up when DD MOSFET. The pulse period is determined by V and V ; V , V and EN/PSV are above their respective thresholds. OUT IN IN DD the period is proportional to output voltage and inversely When EN/PSV is at logic high, V needs to be applied after DD proportional to input voltage. With this adaptive on-time V rises. It is also recommended to use a 10  resistor IN arrangement, the device automatically anticipates the between an external power source and the V pin. To start DD on-time needed to regulate V for the present V up by using the EN/PSV pin when both V and V are OUT IN DD IN condition and at the selected frequency. above their respective thresholds, apply EN/PSV to enable the start-up process. For SiC402A/B in self-biased mode, The advantages of adaptive on-time control are: refer to the LDO section for a full description. • Predictable operating frequency compared to other variable frequency methods. Shutdown • Reduced component count by eliminating the error The SiC402A/B can be shut-down by pulling either V or DD amplifier and compensation components. EN/PSV below its threshold. When using an external power source, it is recommended that the V voltage ramps down • Reduced component count by removing the need to DD before the V voltage. When V is active and EN/PSV at sense and control inductor current. IN DD logic low, the output voltage discharges into the VOUT pin • Fast transient response - the response time is controlled through an internal FET. by a fast comparator instead of a typically slow error Pseudo-Fixed Frequency Adaptive On-Time Control amplifier. The PWM control method used for the SiC402A/B is • Reduced output capacitance due to fast transient pseudo-fixed frequency, adaptive on-time, as shown in response. figure 23. The ripple voltage generated at the output One-Shot Timer and Operating Frequency capacitor ESR is used as a PWM ramp signal. This ripple is The one-shot timer operates as shown in figure 24. The FB used to trigger the on-time of the controller. comparator output goes high when V is less than the FB internal 600 mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to V , the other input is connected to the OUT capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to V . When the capacitor voltage reaches IN V , the on-time is completed and the high-side MOSFET OUT turns off. S14-2048-Rev. C, 13-Oct-14 10 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix V is shown by the following equation. OUT Gate FB comparator drives VIN FVBREP -+ DH QQVL11X L VOUT VOUT = 0.6 x 1 + RR12 + VRI2PPLE x 1 +1 R+ 2( Rx1 Rω1CωTOCP)2 2 R + R TOP 2 1 VOUT ESR FB VIN Ontiem-sehrot DL Q2 COUT + Enable and Power-Save Inputs Rton On-time = K x Rton x (VOUT/VIN) The EN/PSV input is used to enable or disable the switching regulator. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off, the Fig. 24 - On-Time Generation output of the switching regulator soft-discharges the output This method automatically produces an on-time that is into a 500 k internal resistor via the V pin. When proportional to V and inversely proportional to V . Under OUT OUT IN EN/PSV is allowed to float, the pin voltage will float to 33 % steady-state conditions, the switching frequency can be of the voltage at V . The switching regulator turns on with determined from the on-time by the following equation. DD power-save disabled and all switching is in forced fSW = VOUT continuous mode. tON x VIN When EN/PSV is high (above 44 % of the voltage at V ), the DD The SiC402A/B uses an external resistor to set the on-time switching regulator turns on with power-save enabled. The which indirectly sets the frequency. The on-time can be SiC402A/B P operation reduces the switching SAVE programmed to provide an operating frequency up to 1 MHz frequency according to the load for increased efficiency at using a resistor between the t pin and ground. The ON light load conditions. resistor value is selected by the following equation. k Forced Continuous Mode Operation R = ton 25 pF x fsw The SiC402A/B operates the switcher in FCM (Forced The constant, k, equals 1, when V is greater than 3.6 V. Continuous Mode) by floating the EN/PSV pin (see DD If V is less than 3.6 V and V is greater than figure 26). In this mode one of the power MOSFETs is always DD IN (V - 1.75) x 10, k is shown by the following equation. on, with no intentional dead time other than to avoid DD (V - 1.75) x 10 cross-conduction. This feature results in uniform frequency k = DD V across the full load range with the trade-off being poor IN The maximum R value allowed is shown by the following efficiency at light loads due to the high-frequency switching tON equation. of the MOSFETs. DH is gate signal to drive upper MOSFET. Rton_MAX. = VIN_MIN. DL is lower gate signal to drive lower MOSFET. 15 µA V Voltage Selection OUT The switcher output voltage is regulated by comparing V FB ripple OUT as seen through a resistor divider at the FB pin to the internal voltage (VFB) FB threshold 600 mV reference voltage, see figure 25. VOUT to FB pin Inductor DC load current current R 1 R 2 On-time DH on-time is triggered when (tON) VFB reaches the FB threshold Fig. 25 - Output Voltage Selection DH Note that this control method regulates the valley of the output ripple voltage, not the DC value. The DC output voltage V is offset by the output ripple according to the DL OUT following equation. DL drives high when on-time is completed. R V DL remains high until VFB falls to the FB threshold. V = 0.6 x 1 + 1 + RIPPLE OUT R 2 2 Fig. 26 - Forced Continuous Mode Operation When a large capacitor is placed in parallel with R (C ) . 1 TOP S14-2048-Rev. C, 13-Oct-14 11 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix Ultrasonic Power-Save Operation (SiC402A) The SiC402A provides ultrasonic power-save operation at light loads, with the minimum operating frequency fixed at slightly under 25 kHz. This is accomplished by using an internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds 40 μs, DL drives high to turn the low-side MOSFET on. This draws current from V through the inductor, forcing both V and V OUT OUT FB to fall. When V drops to the 600 mV threshold, the next DH FB (the drive signal for the high side FET) on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the low-side MOSFET turns on. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. Because the on-times are forced to occur at intervals no greater than 40 μs, the frequency will not fall far below 25 kHz. Figure 27 shows ultrasonic power-save operation. Fig. 28 - Power-Save Mode minimum fSW ~ 25 kHz Smart Power-Save Protection FB ripple Active loads may leak current from a higher voltage into the voltage (VFB) switcher output. Under light load conditions with FB threshold (600 mV) power-save enabled, this can force VOUT to slowly rise and reach the over-voltage threshold, resulting in a hard Inductor (0 A) shut-down. Smart power-save prevents this condition. current When the FB voltage exceeds 10 % above nominal, the device immediately disables power-save, and DL drives high to turn on the low-side MOSFET. This draws current DH on-time is triggered when On-time from V through the inductor and causes V to fall. (tON) VFB reaches the FB threshold When VOUT drops back to the 600 mV trip point, a OnUoTrmal t FB ON DH switching cycle begins. This method prevents a hard OVP shut-down and also cycles energy from V back to V . It OUT IN 40 μs time-out also minimizes operating power by avoiding forced conduction mode operation. Figure 29 shows typical DL waveforms for the smart power-save feature. After the 40 µs time-out, DL drives high if VFB has not reached the FB threshold. VOUT drifts up to due to leakage current flowing into COUT VOUT discharges via inductor Fig. 27 - Ultrasonic Power-Save Operation Smart power save and low-side MOSFET threshold Power-Save Operation (SiC402B) FB Normal VOUT ripple threshold The SIC402B provides power-save operation at light loads DH and DL off with no minimum operating frequency. With power-save enabled, the internal zero crossing comparator monitors the High-side drive (DH) inductor current via the voltage across the low-side Single DH on-time pulse MOSFET during the off-time. If the inductor current falls to after DL turn-off zero for 8 consecutive switching cycles, the controller enters MOSFET on each subsequent cycle provided that the Low-side drive (DL) power-save operation. It will turn off the low-side MOSFET DL turns on when smart Normal DL pulse after DH on each subsequent cycle provided that the current crosses PSAVE threshold is reached on-time pulse zero. At this time both MOSFETs remain off until V drops DL turns off FB FB threshold is reached to the 600 mV threshold. Because the MOSFETs are off, the load is supplied by the output capacitor. Fig. 29 - Smart Power-Save If the inductor current does not reach zero on any switching cycle, the controller immediately exits power-save and returns to forced continuous mode. Figure 28 shows power-save operation at light loads. S14-2048-Rev. C, 13-Oct-14 12 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix SmartDriveTM Soft-Start of PWM Regulator For each DH pulse the DH driver initially turns on the high SiC402A/B has a programmable soft-start time that is side MOSFET at a lower speed, allowing a softer, smooth controlled by an external capacitor at the SS pin. After the turn-off of the low-side diode. Once the diode is off and the controller meets both UVLO and EN/PSV thresholds, the LX voltage has risen 0.5 V above P , the SmartDrive controller has an internal current source of 3 μA flowing GND circuit automatically drives the high-side MOSFET on at a through the SS pin to charge the capacitor. During the start rapid rate. This technique reduces switching losses while up process (figure 31), 50 % of the voltage at the SS pin is maintaining high efficiency and also avoids the need for used as the reference for the FB comparator. The PWM snubbers for the power MOSFETs. comparator issues an on-time pulse when the voltage at the FB pin is less than 40 % of the SS pin. As a result, the output Current Limit Protection voltage follows the SS voltage. The output voltage reaches The device features programmable current limiting, which is and maintains regulation when the soft start voltage is accomplished by using the R of the lower MOSFET for DS(on)  1.5 V. The time between the first LX pulse and VOUT current sensing. The current limit is set by RILIM resistor. The reaching regulation is the soft-start time (tSS). The RILIM resistor connects from the ILIM pin to the LXS pin which calculation for the soft-start time is shown by the following is also the drain of the low-side MOSFET. When the low-side equation. MOSFET is on, an internal ~10 μA current flows from the I LIM 1.5 V pin and through the R resistor, creating a voltage drop t = C x ILIM SS SS 3 μA across the resistor. While the low-side MOSFET is on, the inductor current flows through it and creates a voltage The voltage at the SS pin continues to ramp up and across the RDS(on). The voltage across the MOSFET is eventually equals 64 % of VDD. After the soft start negative with respect to ground. If this MOSFET voltage completes, the FB pin voltage is compared to an internal drop exceeds the voltage across RILIM, the voltage at the ILIM reference of 0.6 V. The delay time between the VOUT pin will be negative and current limit will activate. The regulation point and P going high is shown by the GOOD current limit then keeps the low-side MOSFET on and will following equation. not allow another high-side on-time, until the current in the C x (0.64 x V - 1.5 V) low-side MOSFET reduces enough to bring the I voltage t = SS DD LIM PGOOD-DELAY 3 μA back up to zero. This method regulates the inductor valley current at the level shown by I in figure 30. LIM IPEAK nt urre ILOAD C or ILIM ct u d n I Fig. 30 - Valley Current Limit Setting the valley current limit to 10 A results in a peak inductor current of 10 A plus peak ripple current. In this situation, the average (load) current through the inductor is 10 A plus one-half the peak-to-peak ripple current. The internal 10 μA current source is temperature compensated at 4100 ppm in order to provide tracking with Fig. 31 - Soft-Start Timing Diagram the RDS(on). Pre-Bias Startup The RILIM value is calculated by the following equation. The SiC402A/B can start up normally even when there is an R = 446 x I x [0.099 x (5 V - V ) + 1] existing output voltage present. The soft start time is still the ILIM LIM DD When selecting a value for R be sure not to exceed the same as normal start up (when the output voltage starts ILIM absolute maximum voltage value for the I pin. Note that from zero). The output voltage starts to ramp up when 40 % LIM because the low-side MOSFET with low R is used for of the voltage at SS pin meets the existing FB voltage level. DS(on) current sensing, the PCB layout, solder connections, and Pre-bias startup is achieved by turning off the lower gate PCB connection to the LX node must be done carefully to when the inductor current falls below zero. This method obtain good results. R should be connected directly to prevents the output voltage from discharging. ILIM LXS (pin 28). S14-2048-Rev. C, 13-Oct-14 13 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix Power Good Output The P (power good) output is an open-drain output Note that if the LDO voltage is set lower than 4.5 V, the GOOD which requires a pull-up resistor. When the voltage at the FB minimum output capacitance for the LDO is 10 μF. pin is 10 % below the nominal voltage, P is pulled low. GOOD LDO ENL Functions It is held low until the output voltage returns above -8 % of The ENL input is used to enable/disable the internal LDO. nominal. When ENL is a logic low, the LDO is off. When ENL is above P will transition low if the V pin exceeds +20 % of GOOD FB the V UVLO threshold, the LDO is enabled and the nominal, which is also the over-voltage shutdown threshold. IN switcher is also enabled if the EN/PSV and V are above P also pulls low if the EN/PSV pin is low when V is DD GOOD DD their threshold. The table below summarizes the function of present. ENL and EN/PSV pins. Output Over-Voltage Protection Over-voltage protection becomes active as soon as the EN/PSV ENL LDO SWITCHER device is enabled. The threshold is set at 600 mV +20 % Disabled Low, < 0.4 V Off Off (720 mV). When V exceeds the OVP threshold, DL latches FB Enabled Low, < 0.4 V Off On high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN/PSV input is Disabled 1 V < High < 2.6 V On Off toggled or V is cycled. There is a 5 μs delay built into the Enabled 1 V < High < 2.6 V On Off DD OVP detector to prevent false transitions. PGOOD is also low Disabled High, > 2.6 V On Off after an OVP event. Enabled High, > 2.6 V On On Output Under-Voltage Protection The ENL pin also acts as the switcher under-voltage lockout When VFB falls 25 % below its nominal voltage (falls to for the VIN supply. When SiC402A/B is self-biased from the 450 mV) for eight consecutive clock cycles, the switcher is LDO and runs from the VIN power source only, the VIN UVLO shut off and the DH and DL drives are pulled low to tri-state feature can be used to prevent false UV faults for the PWM the MOSFETs. The controller stays off until EN/PSV is output by programming with a resistor divider at the VIN, toggled or VDD is cycled. ENL and AGND pins. When SiC402A/B has an external bias voltage at V and the ENL pin is used to program the DD V UVLO, and POR DD V UVLO feature, the voltage at FBL needs to be higher IN UVLO (Under-Voltage Lock-Out) circuitry inhibits switching than 750 mV to force the LDO off. and tri-states the DH/DL drivers until V rises above 3 V. An DD Timing is important when driving ENL with logic and not internal POR (Power-On Reset) occurs when V exceeds DD implementing V UVLO. The ENL pin must transition from IN 3 V, which resets the fault latch and a soft-start counter high to low within 2 switching cycles to avoid the PWM cycle begins which prepares for soft-start. The SiC402A/B output turning off. If ENL goes below the V UVLO threshold IN then begins a soft-start cycle. The PWM will shut off if V DD and stays above 1 V, then the switcher will turn off but the falls below 2.4 V. LDO will remain on. LDO Regulator Timing is important when driving ENL with logic and not SiC402A/B has an option to bias the switcher by using an implementing VIN UVLO. The ENL pin must transition from internal LDO from V . The LDO output is connected to V high to low within 2 switching cycles to avoid the PWM IN DD internally. The output of the LDO is programmable by using output turning off. If ENL goes below the VIN UVLO threshold external resistors from the V pin to A (see figure 32). and stays above 1 V, then the switcher will turn off but the DD GND The feedback pin (FBL) for the LDO is regulated to 750 mV. LDO will remain on. LDO Start-Up VDD to FBL pin Before start-up, the LDO checks the status of the following signals to ensure proper operation can be maintained. R LDO1 1.ENL pin R LDO2 2.V input voltage IN When the ENL pin is high and V is above the UVLO point, IN the LDO will begin start-up. During the initial phase, when the V voltage (which is the LDO output voltage) is less DD Fig. 32 - LDO Output Voltage Selection than 0.75 V, the LDO initiates a current-limited start-up The LDO output voltage is set by the following equation. (typically 65 mA) to charge the output capacitors while protecting from a short circuit event. When V is greater R DD VLDO = 750 mV x 1 + RLDO1 than 0.75 V but still less than 90 % of its final value (as LDO2 sensed at the FBL pin), the LDO current limit is increased to A minimum capacitance of 1 μF referenced to A is GND ~115 mA. When V has reached 90 % of the final value (as DD normally required at the output of the LDO for stability. sensed at the FBL pin), the LDO current limit is increased to S14-2048-Rev. C, 13-Oct-14 14 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix ~200 mA and the LDO output is quickly driven to the nominal value by the internal LDO regulator. It is Switchover recommended that during LDO start-up to hold the PWM control Switchover MOSFET switching off until the LDO has reached 90 % of the final value. This prevents overloading the current-limited LDO LDO VOUT output during the LDO start-up. Due to the initial current limitations on the LDO during power up (figure 33), any external load attached to the V pin must DD be limited to less than the start up current before the LDO Parastic diode has reached 90 % of its final regulation value. V DD Fig. 34 - Switch-over MOSFET Parasitic Diodes Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (V ) is the highest specified IN max. input voltage. The minimum input voltage (V ) is INmin. determined by the lowest input voltage after evaluating the Fig. 33 - LDO Start-Up voltage drops due to connectors, fuses, switches, and PCB LDO Switch-Over Operation traces. The SiC402A/B includes a switch-over function for the LDO. The following parameters define the design. The switch-over function is designed to increase efficiency • Nominal output voltage (V ) OUT by using the more efficient DC/DC converter to power the • Static or DC output tolerance LDO output, avoiding the less efficient LDO regulator when possible. The switch-over function connects the V pin • Transient response DD directly to the VOUT pin using an internal switch. When the • Maximum load current (IOUT). switch-over is complete the LDO is turned off, which results There are two values of load current to evaluate - continuous in a power savings and maximizes efficiency. If the LDO load current and peak load current. Continuous load current output is used to bias the SiC402A/B, then after switch-over relates to thermal stresses which drive the selection the device is self-powered from the switching regulator with of the inductor and input capacitors. Peak load current the LDO turned off. determines instantaneous component stresses and The switch-over starts 32 switching cycles after PGOOD filtering requirements such as inductor saturation, output output goes high. The voltages at the VDD and VOUT pins are capacitors, and design of the current limit circuit. then compared; if the two voltages are within ± 300 mV of The following values are used in this design. each other, the V pin connects to the V pin using an DD OUT V = 12 V ± 10 % internal switch, and the LDO is turned off. To avoid IN unwanted switch-over, the minimum difference between the VOUT = 1.5 V ± 4 % voltages for VOUT and VDD should be ± 500 mV. fSW = 300 kHz It is not recommended to use the switch-over feature for an Load = 10 A maximum output voltage less than V UVLO threshold since the DD Frequency Selection SiC402A/B is not operational below that threshold. Selection of the switching frequency requires making a Switch-over MOSFET Parasitic Diodes trade-off between the size and cost of the external filter The switch-over MOSFET contains parasitic diodes that are components (inductor and output capacitor) and the power inherent to its construction, as shown in figure 34. If the conversion efficiency. voltage at the V pin is higher than V , then the OUT DD The desired switching frequency is 300 kHz which results respective diode will turn on and the current will flow from using components selected for optimum size and cost. through this diode. This has the potential of damaging the A resistor (R ) is used to program the on-time (indirectly device. Therefore, V must be less than V to prevent tON OUT DD setting the frequency) using the following equation. damaging the device. k R = ton 25 pF x f sw S14-2048-Rev. C, 13-Oct-14 15 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix To select R , use the maximum value for V , and for t Capacitor Selection tON IN ON use the value associated with maximum VIN. The output capacitors are chosen based upon required ESR and capacitance. The maximum ESR requirement is tON = VINMVAOXU. Tx fSW ctoolnertaronlcleed. Tbhye othuetp ouut tvpoultta griep phlaes are DqCui rveamlueen tth aatn ids ethqeu aDl tCo the valley of the output ripple plus 1/2 of the peak-to-peak Substituting for RtON results in the following solution. ripple. A change in the output ripple voltage will lead to a R = 133.3 k, use R = 130 k change in DC voltage at the output. tON tON Inductor Selection The design goal for output voltage ripple is 3 % of 1.5 V or 45 mV. The maximum ESR value allowed is shown by the In order to determine the inductance, the ripple current must following equations. first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. ESRMAX = VRIPPLE = 45 mV Higher inductor values will reduce the ripple current/voltage IRIPPLEMAX 4.43 A and for a given DC resistance are more efficient. However, ESRMAX = 10.2 mΩ larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are The output capacitance is usually chosen to meet transient all used in the selection process. requirements. A worst-case load release, from maximum The ripple current will also set the boundary for P load to no load at the exact moment when inductor current SAVE operation. The switching will typically enter P mode is at the peak, determines the required capacitance. If the SAVE when the load current decreases to 1/2 of the ripple current. load release is instantaneous (load changes from maximum For example, if ripple current is 4 A then P operation will to zero in < 1 μs), the output capacitor must absorb all the SAVE typically start for loads less than 2 A. If ripple current is set inductor's stored energy. This will cause a peak voltage on at 40 % of maximum load current, then P will start for the capacitor according to the following equation. SAVE loads less than 20 % of maximum current. 1 The inductor value is typically selected to provide a ripple COUT_MIN =L (IOUT + 2 x IRIPPLEMAX)2 current that is between 25 % to 50 % of the maximum load (VPEAK)2 - (VOUT)2 current. This provides an optimal trade-off between cost, Assuming a peak voltage V of 1.65 V (150 mV rise efficiency, and transient performance. PEAK upon load release), and a 10 A load release, the required During the on-time, voltage across the inductor is capacitance is shown by the next equation. (V - V ). The equation for determining inductance is IN OUT shown next. 1 L =(VIN - VOUT) x tON COUT_MIN = 1 µH (10 + 2 x 4.43)2 IRIPPLE (1.65)2 - (1.5)2 COUT_MIN = 316 µF Example During the load release time, the voltage cross the inductor In this example, the inductor ripple current is set equal is approximately - V . This causes a down-slope or falling to 45 % of the maximum load current. Therefore ripple OUT dI/dt in the inductor. If the load dI/dt is not much faster than current will be 45 % x 10 A or 4.5 A. To find the minimum the dI/dt of the inductor, then the inductor current will tend inductance needed, use the V and t values that IN ON to track the falling load current. This will reduce the excess correspond to V . IN max. inductive energy that must be absorbed by the output (13.2 - 1.5) x 379 ns L = = 0.99 µH capacitor; therefore a smaller capacitance can be used. 4.5 A The following can be used to calculate the needed A slightly larger value of 1 μH is selected. This will decrease capacitance for a given dI /dt. LOAD the maximum I to 4.43 A. RIPPLE Peak inductor current is shown by the next equation. Note that the inductor must be rated for the maximum DC I = I + 1/2 x I LPK max. RIPPLE max. load current plus 1/2 of the ripple current. I = 10 + 1/2 x 4.43 = 12.215 A LPK The ripple current under minimum V conditions is also IN dI checked using the following equations. Rate of change of Load Current = LOAD TON_VINMIN =25 pF x RTON x VOUT = 451 ns dt VINMIN I = maximum load release = 10 A max. IRIPPLE = (VIN - VOLUT) x tON L x I L P K - I M A X x dt IRIPPLE_VINMIN = (10.8 - 1.5) x 451 ns = 4.19 A COUT = ILPK x V2O (UVTPK -d VlLOOUATD) 1 µH S14-2048-Rev. C, 13-Oct-14 16 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix Example ESR loop instability is caused by insufficient ESR. The dlLOAD =2.5 A details of this stability issue are discussed in the ESR dt 1 µs Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe This would cause the output current to move from 10 A the output voltage ripple envelope for overshoot and ringing. to 0 A in 4 μs, giving the minimum output capacitance Ringing for more than one cycle after the initial step is an requirement shown in the following equation. indication that the ESR should be increased. ESR Requirements 12.215 10 1 µH x - x 1 µs 1.5 2.5 A minimum ESR is required for two reasons. One reason COUT = 12.215 x 2 (1.65 - 1.5) is to generate enough output ripple voltage to provide 10 mV at the FB pin (after the resistor divider) to avoid COUT = 169 µF p-p double-pulsing. Note that C is much smaller in this example, 169 μF OUT The second reason is to prevent instability due to insufficient compared to 316 μF based on a worst-case load release. To ESR. The on-time control regulates the valley of the output meet the two design criteria of minimum 316 μF and ripple voltage. This ripple voltage is the sum of the two maximum 10.2 m ESR, select one capacitor of 330 μF and voltages. One is the ripple generated by the ESR, the other 9 m ESR. is the ripple due to capacitive charging and discharging Stability Considerations during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the output Unstable operation is possible with adaptive on-time capacitors, typically SP or POSCAP devices. For stability controllers, and usually takes the form of double-pulsing or the ESR zero of the output capacitor should be lower than ESR loop instability. approximately one-third the switching frequency. The Double-pulsing occurs due to switching noise seen at the formula for minimum ESR is shown by the following FB input or because the FB ripple voltage is too low. This equation. causes the FB comparator to trigger prematurely after the 3 250 ns minimum off-time has expired. In extreme cases the ESRMIN = noise can cause three or more successive on-times. 2 x π x COUT x fSW Double-pulsing will result in higher ripple voltage at the Using Ceramic Output Capacitors output, but in most applications it will not affect operation. When the system is using high ESR value capacitors, the This form of instability can usually be avoided by providing feedback voltage ripple lags the phase node voltage by 90°. the FB pin with a smooth, clean ripple signal that is at least Therefore, the converter is easily stabilized. When the 10 mV , which may dictate the need to increase the ESR p-p system is using ceramic output capacitors, the ESR value is of the output capacitors. It is also imperative to provide a normally too small to meet the above ESR criteria. As a proper PCB layout as discussed in the Layout Guidelines result, the feedback voltage ripple is 180° from the phase section. node and behaves in an unstable manner. In this application Another way to eliminate doubling-pulsing is to add a small it is necessary to add a small virtual ESR network that is (~10 pF) capacitor across the upper feedback resistor, as composed of two capacitors and one resistor, as shown in shown in figure 35. This capacitor should be left figure 36. unpopulated until it can be confirmed that double-pulsing exists. Adding the C capacitor will couple more ripple TOP into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. CTOP VOUT R1 To FB pin Fig. 36 - Virtual ESR Ramp Circuit R2 The ripple voltage at FB is a superposition of two voltage sources: the voltage across C and output ripple voltage. L Fig. 35 - Capacitor Coupling to FB Pin S14-2048-Rev. C, 13-Oct-14 17 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix They are defined in the following equations. I x DCR (s x L/DCR + 1) V = L CL S x RC + 1 L L ΔI ΔV = L OUT 8C x f SW Figure 37 shows the magnitude of the ripple contribution due to C at the FB pin. L Fig. 39 - FB Voltage in Phasor Diagram The magnitude of the feedback ripple voltage, which is dominated by the contribution from C , is controlled L by the value of R , R and C . If the corner frequency of 1 2 C (R //R ) x C is too high, the ripple magnitude at the FB pin 1 2 C will be smaller, which can lead to double-pulsing. Conversely, if the corner frequency of (R //R ) x C is too 1 2 C low, the ripple magnitude at FB pin will be higher. Since the SiC402A/B regulates to the valley of the ripple voltage Fig. 37 - FB Voltage by C Voltage L at the FB pin, a high ripple magnitude is undesirable as it significantly impacts the output voltage regulation. It is shown by the following equation. As a result, it is desirable to select a corner frequency for (R //R ) x C to achieve enough, but not excessive, ripple 1 2 C magnitude and phase margin. The component values for (R //R ) x S x C VFB = V x 1 2 C R , R , and C should be calculated using the following CL CL (R //R ) x S x C + 1 1 2 C 1 2 C procedure. Figure 38 shows the magnitude of the ripple contribution Select C (typical 10 nF) and R to match with L and DCR L L due to the output voltage ripple at the FB pin. time constant using the following equation. L R = L DCR x C L Select C by using the following equation. C 1 3 C ≈ x C R //R 2 x π x f 1 2 sw The resistor values (R and R ) in the voltage divider circuit 1 2 set the V for the switcher. The typical value for C is from OUT C 10 pF to 1 nF. Dropout Performance The output voltage adjustment range for continuous Fig. 38 - FB Voltage by Output Voltage conduction operation is limited by the fixed 250 ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calculated using It is shown by the following equation. worst-case values for on- and off-times. The duty-factor limitation is shown by the next equation. R VFBΔV = ΔV x 2 OUT OUT R// 1 + R 1 S x CC 2 TON(MIN) DUTY = TON(MIN) x TOFF(MAX) It is recommended that R be set to 1k. 2 The inductor resistance and MOSFET on-state voltage The purpose of this network is to couple the inductor current drops must be included when performing worst-case ripple information into the feedback voltage such that the dropout duty-factor calculations. feedback voltage has 90° phase lag to the switching node similar to the case of using standard high ESR capacitors. This is illustrated in figure 39. S14-2048-Rev. C, 13-Oct-14 18 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix System DC Accuracy (V Controller) HIGH OUTPUT VOLTAGE OPERATION OUT Three factors affect VOUT accuracy: the trip point of the FB For the SiC40X family the recommended maximum output error comparator, the ripple voltage variation with line and voltage of no more than 75 % of V . IN load, and the external resistor tolerance. The error For applications where an output voltage greater than 5 V is comparator offset is trimmed so that under static conditions required a resistive network should be used to step down the it trips when the feedback pin is 600 mV, 1 %. output voltage in order to provide the V with 4.5 V. OUT_PIN The on-time pulse from the SiC402A/B in the design example is calculated to give a pseudo-fixed frequency of 300 kHz. Some frequency variation with line and load is R (V - V ) expected. This variation changes the output ripple voltage. R1 = 2 VOUT OUT_PIN OUT_PIN Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC For example, if an output voltage of V = 8.5 V is required, regulation error. For example, if the output ripple is 50 mV OUT setting R = 10 k and V = 4.5 V results in R = 8870  with V = 6 V, then the measured DC output will be 25 mV 2 OUT_PIN 1 IN above the comparator trip point. If the ripple increases to The switching frequency will also need recalculating using a 80 mV with VIN = 25 V, then the measured DC output will be VOUT_PIN magnitude of 4.5 V. 40 mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. V The use of 1 % feedback resistors may result in up to f = OUT_PIN sw t x V 1 % error. If tighter DC accuracy is required, 0.1 % resistors ON IN should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor LX effect on the DC output voltage. The output ESR also affects Vout the output ripple and thus has a minor effect on the DC output voltage. R1 SiC40X V Cout Switching Frequency Variation OUT_PIN The switching frequency varies with load current as a result of the power losses in the MOSFETs and DCR of the R2 inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. An adaptive on-time converter must also compensate for the same losses by increasing the Fig. 40 - Resistor Divider Network allows 4.5 V at the VOUT Pin effective duty cycle (more time is spent drawing energy from V as losses increase). The on-time is essentially constant IN for a given V /V combination, to offset the losses the OUT IN off-time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load. S14-2048-Rev. C, 13-Oct-14 19 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix LAYOUT CONSIDERATIONS The SiC40x family of footprint compatible 15 A, 10 A, and 3.It is advisable to use ceramic capacitors at the output to 6 A products offers the designer a scalable buck regulator reduce impedance. Place these as close to the IC P GND solution. If the below layout recommendations are followed, and output voltage node as design will allow. Place a the same layout can be used to cover a wide range of output small 10 nF/100 nF ceramic capacitor closest to the IC currents and voltages without any changes to the board and inductor loop. design and only minor changes to the component values in 4.The loop between LX, V and the IC GND should be as OUT the schematic. compact as possible. This will lower series resistance The reference design has a majority of the components and also make the current loop smaller enabling the high placed on the top layer. This allows for easy assembly and frequency response of the output capacitors to take straightforward layout. effect. Figure 41 outlines the pointers for the layout considerations 5.The output impedance should be small when high and the explanations follow. current is required; use high current traces, multiple layers can be used with many vias. 6.Use many vias when multiple layers are involved. This will have the effect of lowering the resistance between 9 layers and reducing the via inductance of the PCB nets. 2 VVIINN 7.If a voltage injection network is needed then place it near 1 to the inductor LX node. 7 SiC40X 8.P can be used on internal layers if the resistance of GND 00VV 6 the PCB is to be small; this will also help remove heat. LX 10 Use extra vias if needed but be mindful to allow a path between the vias. 11 VVOOUUTT 3 4 9.A quiet plane should be employed for the AGND, this is 5 placed under the small signal passives. This can be 8 placed on multiple layers if needed for heat removal. This should be connected to the P plane near to the input GND GND at one connection only of at least 1 mm width. Fig. 41 - Reference Design Pointers 10.The LX copper can also be used on multiple layers, use 1.Place input ceramic capacitors close to the voltage input a number of vias. pins with a small 10 nF/100 nF placed as close as the 11.The copper area beneath the inductor has been removed design rules will allow. This will help reduce the size of (on all layers) in this design to reduce the inductive the input high frequency current loop and consequently coupling that occurs between the inductor and the GND reduce the high frequency ripple noise seen at the input trace. No other voltage planes should be placed under and the LX node. this area. 2.Place the setup and control passive devices logically around the IC with the intention of placing a quiet ground plane beneath them on a secondary layer. S14-2048-Rev. C, 13-Oct-14 20 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix PCB LAYOUT Fig. 42 - Top Layer Fig. 44 - Inner Layer 2 Fig. 43 - Inner Layer 1 Fig. 45 - Bottom Layer S14-2048-Rev. C, 13-Oct-14 21 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix SCHEMATIC Note • If OUT voltage setting  5 VDC, please change R10 and R11 value based on “High Output Voltage Operation” formula calculation. S14-2048-Rev. C, 13-Oct-14 22 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix BILL OF MATERIALS (V = 12 V, V = 1.5 V, F = 500 kHz) IN OUT sw PCB ITEM QTY REFERENCE VALUE VOLTAGE PART NUMBER MANUFACTURER FOOTPRINT 1 2 C1, C2 1206 Omit 35 V C3216X5R1V226M160AC TDK 2 2 C3, C4 1206 22 μF 35 V C3216X5R1V226M160AC TDK 3 3 C5, C9, C12 0402 10 nF 50 V GRM155R71H103KA88D Murata 4 1 C6 0402 2.2 μF 10 V C0402C225M8PACTU Kemet 5 2 C7, C10 0402 2.2 nF 50 V GRM155R71H222KA01D Murata 6 1 C8 0402 100 nF 35 V CGA2B3X7R1V104K050BB Vishay 7 3 C13, C14, C15 1206 47 μF 10 V GRM31CR61A476ME15L Murata 8 5 C16, C17, C18, C19, C20 1206 Omit 10 V GRM31CR61A476ME15L Murata 9 2 C21, C22 7343 Omit - - - 10 4 P1, P3, P9, P10 Banana Jack - - 575-4K-ND Keystone 11 5 P2, P4, P5, P7, P8 Header-2 - - 826926-2 AMP (TE) 12 1 P6 Header-3 - - HTSW-103-08-T-S Samtec 13 1 L1 IHLP4040 1 μH - IHLP4040DZER1R0 Vishay 14 1 R1 0402 249K - CRCW0402249KFKED Vishay 15 1 R2 0402 100K - CRCW0402100KFKED Vishay 16 1 R3 0402 169K - CRCW0402169KFKED Vishay 17 1 R4 0402 30K - CRCW040230K0FKED Vishay 18 1 R5 0402 5K11 - CRCW04025K11FKED Vishay 19 1 R6 0402 76K8 - CRCW040276K8FKED Vishay 20 1 R7 0402 10R - CRCW040210R0FKEA Vishay 21 1 R8 0402 10K - CRCW040210K0FKED Vishay 22 1 R9 0805 Omit - - Vishay 23 1 R10 0402 0R - CRCW04020000Z0ED Vishay 24 1 R11 0402 Omit - - Vishay 25 1 R12 0402 1K54 - CRCW04021K54FKED Vishay 26 1 R13 0402 1K - CRCW0402249KFKED Vishay 27 1 R14 0402 10R - CRCW040210R0FKEA Vishay 28 1 R15 0402 10K - CRCW040210K0FKED Vishay 29 1 U1 MLP55-33 SIC402 - - - S14-2048-Rev. C, 13-Oct-14 23 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC402A, SiC402BCD www.vishay.com Vishay Siliconix PACKAGE DIMENSIONS AND MARKING INFO MILLIMETERS INCHES MILLIMETERS INCHES DIM. NOTE DIM. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.027 0.029 0.031 D2-1 3.43 3.48 3.53 0.135 0.137 0.139 A1 0.00 - 0.05 0.00 - 0.002 8 D2-2 1.00 1.05 1.10 0.039 0.041 0.043 A2 0.20 ref. 0.008 ref. D2-3 1.00 1.05 1.10 0.039 0.041 0.043 b 0.20 0.25 0.30 0.078 0.098 0.110 4 D2-4 1.92 1.97 2.02 0.075 0.077 0.079 D 5.00 BSC 0.196 BSC D2-5 0.36 0.014 e 0.50 BSC 0.019 BSC E2-1 3.43 3.48 3.53 0.135 0.137 0.139 E 5.00 BSC 0.196 BSC E2-2 1.61 1.66 1.71 0.063 0.065 0.067 L 0.35 0.40 0.45 0.013 0.015 0.017 E2-3 1.43 1.48 1.53 0.056 0.058 0.060 N 32 32 3 E2-4 0.45 0.018 Nd 8 8 3 Ne 8 8 3 Notes 1.Use millimeters as the primary measurement. 2.Dimensioning and tolerances conform to ASME Y1 4.5M - 1994. 3.N is the number of terminals Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4.Dimensions applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 5.The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6.Exact shape and size of this feature is optional. 7.Package warpage max. 0.08 mm. 8.Applied only for terminals.            Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63729. S14-2048-Rev. C, 13-Oct-14 24 Document Number: 63729 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information Vishay Siliconix PowerPAK® MLP55-32L CASE OUTLINE 0.08C 5 6 2x A bPyin m 1a drkoitng A 0.10CA A1 D2 - 1 2x D A2 0.360 D2 - 2 Pin #1 identification 0.10CB 25 32 R0.200 24 1 e 2 E (5 3m2mL Tx/ S5 LmPm) A10BC E2 - 1 0.45 E2 - Nd-1) XeRef. 40. 2 - 3 ( E 17 8 B 16 9 b D2 - 4 D2 - 3 C (Nd-1) Xe L Ref. 0.36 D4 Top View Side View Bottom View MILLIMETERS INCHES DIM MIN. NOM. MAX. MIN. NOM. MAX. A 0.80 0.85 0.90 0.031 0.033 0.035 A1(8) 0.00 - 0.05 0.000 - 0.002 A2 0.20 REF. 0.008 REF. b(4) 0.20 0.25 0.30 0.078 0.098 0.011 D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC E 5.00 BSC 0.196 BSC L 0.35 0.40 0.45 0.013 0.015 0.017 N(3) 32 32 Nd(3) 8 8 Ne(3) 8 8 D2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 D2 - 2 1.00 1.05 1.10 0.039 0.041 0.043 D2 - 3 1.00 1.05 1.10 0.039 0.041 0.043 D2 - 4 1.92 1.97 2.02 0.075 0.077 0.079 E2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 E2 - 2 1.61 1.66 1.71 0.063 0.065 0.067 E2 - 3 1.43 1.48 1.53 0.056 0.058 0.060 ECN: T-08957-Rev. A, 29-Dec-08 DWG: 5983 Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. Document Number: 64714 www.vishay.com Revision: 29-Dec-08 1

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