End of Life. Last Available Purchase Date is 31-Dec-2014 Si9910 Vishay Siliconix Adaptive Power MOSFET Driver1 FEATURES dv/dt and di/dt Control t Shoot-Through Current Limiting Compatible with Wide Range of MOSFET Devices rr Undervoltage Protection Low Quiescent Current Bootstrap and Charge Pump Compatible Short-Circuit Protection CMOS Compatible Inputs (High-Side Drive) DESCRIPTION The Si9910 Power MOSFET driver provides optimized gate Fault protection circuitry senses an undervoltage or output drive signals, protection circuitry and logic level interface. Very short-circuit condition and disables the power MOSFET. low quiescent current is provided by a CMOS buffer and a Addition of one external resistor limits maximum di/dt of the high-current emitter-follower output stage. This efficiency external Power MOSFET. A fast feedback circuit may be used allows operation in high-voltage bridge applications with to limit shoot-through current during t (diode reverse recovery rr “bootstrap” or “charge-pump” floating power supply time) in a bridge configuration. techniques. The non-inverting output configuration minimizes current The Si9910 is available in both standard and lead (Pb)-free drain for an n-channel “on” state. The logic input is internally 8-pin plastic DIP and SOIC packages which are specified to diode clamped to allow simple pull-down in high-side drives. operate over the industrial temperature range of −40 C to 85 C. FUNCTIONAL BLOCK DIAGRAM R3 VDS *100 k VDD C1 DRAIN Undervoltage/ *2 to 5 pF Overcurrent Protection PULL-UP R2 *250 2- s Delay PULL-DOWN INPUT ISENSE R1 *0.1 VSS * Typical Values 1. Patent Number 484116. Document Number: 70009 www.vishay.com S-42043—Rev. H, 15-Nov-04 1

Si9910 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to VSS Pin Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 85(cid:2)C VDD Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150(cid:2)C Power Dissipation (Package)a Pin 1, 4, 5, 7, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V 8-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.7 V to VDD + 0.3 V 8-Pin Plastic DIP (J Suffix)b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (cid:1)20 mA Notes Peak Current (Ipk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A a. Device mounted with all leads soldered or welded to PC board. Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150(cid:2)C b. Derate 5.6 mW/(cid:2)C above 25(cid:2)C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONSa Test Conditions Limits UUnnlleessss OOtthheerrwwiissee SSppeecciiffiieedd Parameter Symbol TA = OpVeDrDa t1in0g.8Te Vm tpoe 1ra6t.u5r eV Range Minc Typb Maxc Unit Input High Level Input Voltage VIH 0.70 x VDD 7.4 Low Level Input Voltage VIL 6.0 0.35 x VDD V Input Voltage Hysteresis Vh 0.90 2.0 3.0 High Level Input Current IIH VIN = VDD (cid:1)1 (cid:2)(cid:2)AA Low Level Input Current IIL VIN = 0 V (cid:1)1 Output High Level Output Voltage VOH IOH = −200 mA VDD −3 10.7 Low Level Output Voltage VOL IOL = 200 mA 1.3 3 Undervoltage Lockout VUVLO 8.3 9.2 10.6 VV ISENSE Pin Threshold VTH M10a0x mISV = C2h manAg, eIn opnu tD Hraiginh 0.5 0.66 0.8 Voltage Drain-Source Maximum VDS Input High 8.3 9.1 10.2 Input Current for VDS Input IVDS 12 20.0 (cid:2)A Peak Output Source Current IOS+ 1 A Peak Output Sink Current IOS− −1 Supply Supply Range VDD 10.8 16.5 V IDD1 Output High, No Load 0.1 1 SSuuppppllyy CCuurrrreenntt (cid:2)(cid:2)AA IDD2 Output Low, No Load 100 500 Dynamic Propagation Delay Time Low to High Level tPLH 120 Propagation Delay Time High to Low Level tPHL 135 Rise Time tr CCLL == 22000000 ppFF 50 nnss Fall Time tf 35 Overcurrent Sense Delay (VDS) tDS 1 (cid:2)S Input Capacitance Cin 5 pF Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. www.vishay.com Document Number: 70009 2 S-42043—Rev. H, 15-Nov-04

Si9910 Vishay Siliconix AC TESTING CONDITIONS VDD IN 50% (IN = L) VSS tPLH tPHL 90% VOH 10% OUT VOL tr tf PIN CONFIGURATIONS AND ORDERING INFORMATION PDIP-8 SOIC-8 VDS 1 8 PULL-UP VDS 1 8 PULL-UP INPUT 2 7 Pull-DOWN INPUT 2 7 PULL−DOWN VDD 3 6 VSS VDD 3 6 VSS DRAIN 4 5 ISENSE DRAIN 4 5 ISENSE Top View Top View ORDERING INFORMATION Part Number Temperature Range Package Si9910DY Si9910DY-T1 SOIC-8 Si9910DY-T1—E3 −40 to 85(cid:2)C Si9910DJ PPDDIIPP-88 Si9910DJ—E3 Document Number: 70009 www.vishay.com S-42043—Rev. H, 15-Nov-04 3

Si9910 Vishay Siliconix PIN DESCRIPTION “floating” applications (half-bridge, high-side) and ground-referenced applications (half-bridge, low-side). Pin 1: V DS Pin 7: PULL-DOWN Pin 1 or V is a sense input for the maximum source-drain Pin 8: PULL-UP DS voltage limit. Two microseconds after a high transition on input Pull-up and pull-down outputs collectively provide the power pin 2, an internal timer enables the VDS(max) sense circuitry. A MOSFET gate with charging and discharging currents. Turn catastrophic overcurrent condition, excessive on-resistance, “on” or “off” di/dt can be limited by adding resistance (R ) in or insufficient gate-drive voltage can be sensed by limiting 2 series with the appropriate output. the maximum voltage drop across the power MOSFET. An external resistor (R3) is required to protect pin 1 from overvoltage during the MOSFET “off” condition. Exceeding APPLICATIONS V latches the Si9910 “off.” Drive is re-enabled on the DS(max) next positive- going input on pin 2. If pin 1 is not used, it must “Floating” High-Side Drive Applications be connected to pin 6 (V ). SS As demonstrated in Figure 1, the Si9910 is intended for use Pin 2: INPUT as both a ground-referenced gate driver and as a “high-side” or source-referenced gate driver in half-bridge applications. A non-inverting, Schmidt trigger input controls the state of the Several features of the Si9910 permit its use in half-bridge MOSFET gate-drive outputs and enables the protection logic. high-side drive applications. When the input is low ((cid:2) V ), V is monitored for an IL DD undervoltage condition (insufficiently charged bootstrap A simple and inexpensive method of isolating a floating supply capacitor). If an undervoltage ((cid:2) V ) condition exists, to power the Si9910 in high-side driver applications had to be DD(min) the driver will ignore a turn-on input signal. An undervoltage provided. Therefore, the Si9910 was designed to be ((cid:2) V ) condition during an “on” state will not be sensed. compatible with two of the most commonly used floating DD(min) supply techniques: the bootstrap and the charge pump. Both of these techniques have limitations when used alone. A properly designed bootstrap circuit can provide Pin 3: V DD low-impedance drive which minimizes transition losses and V supplies power for the driver’s internal circuitry and the charge pump circuit provides static operation. DD charging current for the power MOSFET’s gate capacitance. The Si9910 minimizes the internal IDD in the “on” state The Si9910 is configured to take advantage of either floating (gate-drive outputs high) allowing a “floating” power supply to supply technique if the application is not sensitive to their be provided by charge pump or bootstrap techniques. particular limitations, or both techniques if switching losses must be minimized and static operation is necessary. The Pin 4: DRAIN schematic above illustrates both the charge pump and bootstrap circuits used in conjunction with an Si9910 in a Drain is an analog input to the internal dv/dt limiting circuitry. high-side driver application. An external capacitor (C1) must be used to protect the input from exposure to the high-voltage (“off” state) drain and to set Input signal level shifting is accomplished with a passive the power MOSFET’s maximum rate of dv/dt. If dv/dt feedback pull-up (R4) and n-channel MOSFET (Q2) for pull-down in is not used, pin 4 must be left open. applications below 500 V. Total node capacitance defines the value of R4 needed to guarantee an input transition rate which Pin 5: I safely exceeds the maximum dv/dt rate of the output SENSE half-bridge. Using level-shift devices with higher current I in combination with an external resistor (R SENSE 1) capabilities may necessitate the addition of current-limiting protects the power MOSFET from potentially catastrophic components such as R5. peak currents. I is an analog feedback that limits current SENSE during the power MOSFET’s transition to an “on” state. It is Bootstrap Undervoltage Lockout intended to protect power MOSFETs (in a half-bridge arrangement) from “shoot-through” current, resulting from When using a bootstrap capacitor as a high-side floating excess di/dt and t of flyback diodes or from logic timing supply, care must be taken to ensure time is available to rr overlap. An 0.8-V drop across (R1) should indicate a current recharge the bootstrap capacitor prior to turn-on of the level that is approximately four times the maximum allowable high-side MOSFET. As a catastrophic protection against load current. When the ISENSE input is not used, it should be abnormal conditions such as start-up, loss of power, etc., an tied to pin 6 (V ). internal voltage monitor has been included which monitors the SS bootstrap voltage when the Si9910 is in the low state. The Si9910 will not respond to a high input signal until the voltage Pin 6: V SS on the bootstrap capacitor is sufficient to fully enhance the V is the driver’s ground return pin. The applications diagram power MOSFET gate. For more details, please refer to SS illustrates the connection of V for source-referenced Application Note AN705. SS www.vishay.com Document Number: 70009 4 S-42043—Rev. H, 15-Nov-04

Si9910 Vishay Siliconix APPLICATION CIRCUIT VDD (12 to 15 V) VDD VDS R3 D1 DRAIN C1 R4 PULL-UP R2 C2 PULL-DOWN Q1 INPUT ISENSE C3 R1 VDD OSC VDS R3’ Motor Q2 CMOS Logic DRAIN C1’ C4 PULL-UP R2’ R5 PULL-DOWN Q1’ INPUT ISENSE VSS R1’ C2 = Bootstrap Cap C3 = Chargepump Cap FIGURE 1. High-Voltage Half-Bridge with Si9910 Drivers Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70009. Document Number: 70009 www.vishay.com S-42043—Rev. H, 15-Nov-04 5

Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 7 6 5 E H 1 2 3 4 S D h x 45 C 0.25 mm (Gage Plane) A All Leads q 0.101 mm e B A1 L 0.004" MILLIMETERS INCHES DIM Min Max Min Max A 1.35 1.75 0.053 0.069 A 0.10 0.20 0.004 0.008 1 B 0.35 0.51 0.014 0.020 C 0.19 0.25 0.0075 0.010 D 4.80 5.00 0.189 0.196 E 3.80 4.00 0.150 0.157 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.50 0.93 0.020 0.037 q 0° 8° 0° 8° S 0.44 0.64 0.018 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 www.vishay.com 11-Sep-06 1

Package Information Vishay Siliconix PDIP: 8-LEAD (POWER IC ONLY) MILLIMETERS INCHES Dim Min Max Min Max 8 7 6 5 A 3.81 5.08 0.150 0.200 E A1 0.38 1.27 0.015 0.050 E1 B 0.38 0.51 0.015 0.020 1 2 3 4 B1 0.89 1.65 0.035 0.065 C 0.20 0.30 0.008 0.012 D 9.02 10.92 0.355 0.430 E 7.62 8.26 0.300 0.325 E1 5.59 7.11 0.220 0.280 D e1 2.29 2.79 0.090 0.110 S Q1 eA 7.37 7.87 0.290 0.310 L 2.79 3.81 0.110 0.150 Q1 1.27 2.03 0.050 0.080 A S 0.76 1.65 0.030 0.065 ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5918 A1 L 15° NOTE: End leads may be half leads. e1 MAX C B1 B eA Document Number: 72813 www.vishay.com 28-Jan-04 1

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