New Product Si7454DDP Vishay Siliconix N-Channel 100 V (D-S) MOSFET FEATURES PRODUCT SUMMARY • TrenchFET® Power MOSFET VDS (V) RDS(on) () Max. ID (A)a Qg (Typ.) (cid:129) 100 % Rg and UIS Tested (cid:129) Material categorization: For definitions of compliance 0.033 at VGS = 10 V 21 please see www.vishay.com/doc?99912 100 0.036 at VGS = 7.5 V 20 6.1 nC APPLICATIONS 0.047 at VGS = 4.5 V 17.7 (cid:129) DC/DC Primary Side Switch PowerPAK® SO-8 (cid:129) Telecom/Server 48 V, Full/Half-Bridge DC/DC (cid:129) Industrial (cid:129) Synchronous Rectification 6.15 mm S 5.15 mm D 1 S 2 S 3 G 4 D 8 D 7 D G 6 D 5 Bottom View Ordering Information: Si7454DDP-T1-GE3 (Lead (Pb)-free and Halogen-free) S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) A Parameter Symbol Limit Unit Drain-Source Voltage VDS 100 V Gate-Source Voltage VGS ± 20 TC = 25 °C 21 TC = 70 °C 17 Continuous Drain Current (T = 150 °C) I J TA = 25 °C D 7.9b, c TA = 70 °C 6.3b, c A Pulsed Drain Current (t = 300 µs) IDM 40 TC = 25 °C 22 Continuous Source-Drain Diode Current TA = 25 °C IS 3.7b, c Single Pulse Avalanche Current IAS 12 L =0.1 mH Single Pulse Avalanche Energy EAS 7.2 mJ TC = 25 °C 29.7 TC = 70 °C 19 Maximum Power Dissipation TA = 25 °C PD 4.1b, c W TA = 70 °C 2.6b, c Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C Soldering Recommendations (Peak Temperature)d, e 260 THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambientb, f t  10 s RthJA 24 30 °C/W Maximum Junction-to-Case (Drain) Steady State RthJC 3.3 4.2 Notes: a.Based on T = 25 °C. C b.Surface mounted on 1" x 1" FR4 board. c. t = 10 s. d.See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e.Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 70 °C/W. Document Number: 67883 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com S12-1358-Rev. A, 11-Jun-12 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

New Product Si7454DDP Vishay Siliconix SPECIFICATIONS (T = 25 °C, unless otherwise noted) J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 100 V VDS Temperature Coefficient VDS/TJ 60 ID = 250 µA mV/°C VGS(th) Temperature Coefficient VGS(th)/TJ - 5 Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1.5 3.0 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA VDS = 100 V, VGS = 0 V 1 Zero Gate Voltage Drain Current IDSS µA VDS = 100 V, VGS = 0 V, TJ = 55 °C 10 On-State Drain Currenta ID(on) VDS 5 V, VGS = 10 V 20 A VGS = 10 V, ID = 10 A 0.027 0.033 Drain-Source On-State Resistancea RDS(on) VGS = 7.5 V, ID = 8 A 0.029 0.036  VGS = 4.5 V, ID = 6 A 0.036 0.047 Forward Transconductancea gfs VDS = 10 V, ID = 10 A 19 S Dynamicb Input Capacitance Ciss 550 Output Capacitance Coss VDS = 50 V, VGS = 0 V, f = 1 MHz 217 pF Reverse Transfer Capacitance Crss 26 VDS = 50 V, VGS = 10 V, ID = 10 A 12.8 19.5 Total Gate Charge Qg VDS = 50 V, VGS = 7.5 V, ID = 10 A 9.7 15 6.1 9.5 nC Gate-Source Charge Qgs VDS = 50 V, VGS = 4.5 V, ID = 10 A 1.8 Gate-Drain Charge Qgd 2.9 Output Charge Qoss VDS = 50 V, VGS = 0 V 17.2 26 Gate Resistance Rg f = 1 MHz 0.2 1 2  Turn-On Delay Time td(on) 10 20 Rise Time tr VDD = 50 V, RL = 5  13 26 Turn-Off Delay Time td(off) ID  10 A, VGEN = 10 V, Rg = 1  16 32 Fall Time tf 9 18 ns Turn-On Delay Time td(on) 10 20 Rise Time tr VDD = 50 V, RL = 5  12 24 Turn-Off Delay Time td(off) ID  10 A, VGEN = 7.5 V, Rg = 1  16 32 Fall Time tf 9 18 Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS TC = 25 °C 22 A Pulse Diode Forward Currenta ISM 40 Body Diode Voltage VSD IS = 4 A 0.8 1.2 V Body Diode Reverse Recovery Time trr 30 60 ns Body Diode Reverse Recovery Charge Qrr 28 56 nC I = 5 A, dI/dt = 100 A/µs, T = 25 °C F J Reverse Recovery Fall Time ta 19 ns Reverse Recovery Rise Time tb 11 Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com For technical questions, contact: pmostechsupport@vishay.com Document Number: 67883 2 S12-1358-Rev. A, 11-Jun-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

New Product Si7454DDP Vishay Siliconix TYPICAL CHARACTERISTICS (25°C, unless otherwise noted) 50 50 V = 10 V thru 5 V GS 40 40 ent (A) 30 nt (A) 30 I - Drain CurrD 20 VGS = 4 V - Drain CurreD 20 TC = 25 °C I 10 10 VGS = 3 V TC = 125 °C T = - 55 °C C 0 0 0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.6 3.2 4.8 6.4 8.0 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.0700 850 e (Ω) 0.0600 pF) 680 Ciss Resistanc 0.0500 acitance (510 Coss R - On-DS(on)0.0400 VGS = 4.5 V VGS = 7.5 V C - Cap340 0.0300 170 V = 10 V C GS rss 0.0200 0 0 8 16 24 32 40 0 16 32 48 64 80 I - Drain Current (A) D V - Drain-to-Source Voltage (V) DS On-Resistance vs. Drain Current and Gate Voltage Capacitance 1 0 2.0 ID = 10 A ID = 10 A VGS = 10 V V) 8 1.7 Gate-to-Source Voltage ( 46 VDS = 25 V VDS = 50 V VDS = 75 V - On-Resistance DS(on)(Normalized) 11..14 VGS = 4.5 V - S R VG 2 0.8 0 0.5 0.0 2.8 5.6 8.4 11.2 14.0 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 67883 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com S12-1358-Rev. A, 11-Jun-12 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

New Product Si7454DDP Vishay Siliconix TYPICAL CHARACTERISTICS (25°C, unless otherwise noted) 100 0.20 10 0.16 ID = 10 A Current (A) 1 TJ = 150 °C TJ = 25 °C sistance (Ω) 0.12 ource 0.1 On-Re 0.08 I - SS - DS(on) TJ = 125 °C 0.01 R 0.04 T = 25 °C J 0.001 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.4 100 0.2 80 0 V) ce ( W) 60 Varian - 0.2 ID = 5 mA ower ( GS(th) - 0.4 P 40 V - 0.6 ID = 250 μA 20 - 0.8 0 - 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10 T - Temperature (°C) Time (s) J Threshold Voltage Single Pulse Power, Junction-to-Ambient 100 I Limited DM 10 I Limited A) D 100 μs nt ( e urr 1 ms C 1 ain 10 ms Dr - Limited by RDS(on)* 100 ms D I 0.1 1 s 10 s T = 25 °C A Single Pulse BVDSS Limited DC 0.01 0.01 0.1 1 10 100 V -Drain-to-Source Voltage (V) DS * V > minimum V at which R is specified GS GS DS(on) Safe Operating Area, Junction-to-Ambient www.vishay.com For technical questions, contact: pmostechsupport@vishay.com Document Number: 67883 4 S12-1358-Rev. A, 11-Jun-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

New Product Si7454DDP Vishay Siliconix TYPICAL CHARACTERISTICS (25°C, unless otherwise noted) 25 20 A) nt ( 15 e urr C n Drai 10 - D I 5 0 0 25 50 75 100 125 150 T -Case Temperature (°C) C Current Derating* 40 2.20 32 1.76 W) 24 (W) 1.32 er ( wer w o Po 16 P 0.88 8 0.44 0 0.00 0 25 50 75 100 125 150 0 25 50 75 100 125 150 TC - Case Temperature (°C) TA-AmbientTemperature(°C) Power, Junction-to-Case Power, Junction-to-Ambient * The power dissipation P is based on T = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper D J(max.) dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 67883 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com S12-1358-Rev. A, 11-Jun-12 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

New Product Si7454DDP Vishay Siliconix TYPICAL CHARACTERISTICS (25°C, unless otherwise noted) 1 Duty Cycle = 0.5 nt e si Trannce 0.2 ective mpeda 0.1 0.1 NNootteess:: Normalized EffThermal I 00..0025 1212P..P..DPDDPDMeuMeurtrtyyUUCnCniytiytt1t1ccBBlleeata,t2,s2sDDee====RRtthhttttJ12J12AA==7700 °°CC//WW 33..TTJJMM--TTAA==PPDDMMZZtthhJJAA((tt)) Single Pulse 44..SSuurrffaacceeMMoouunntteedd 0.01 0.0001 0.001 0.01 0.1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Duty Cycle = 0.5 nt e 0.2 si Trannce 0.1 ective mpeda 0.1 0.00.205 d Effmal I Single Pulse alizeTher m or N 0.01 0.0001 0.001 0.01 0.1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67883. www.vishay.com For technical questions, contact: pmostechsupport@vishay.com Document Number: 67883 6 S12-1358-Rev. A, 11-Jun-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix PowerPAK® SO-8, (Single/Dual) H L E2 K W E4 θ D4 1 M 1 Z 2 2 e 2D1D D2 D D5 3 3 4 4b θ L1 E3 θ θ A1 Backside View of Single Pad H E2 K L A E4 c 2 4 E1 Detail Z D 1 E D3 (2x) D1 2 D2 K1 D5 3 D2 4b Notes 1.Inch will govern. 2 Dimensions exclusive of mold gate burrs. E3 3.Dimensions exclusive of mold flash and cutting burrs. Backside View of Dual Pad MILLIMETERS INCHES DIM. MIN. NOM. MAX. MIN. NOM. MAX. A 0.97 1.04 1.12 0.038 0.041 0.044 A1 - 0.05 0 - 0.002 b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.23 0.28 0.33 0.009 0.011 0.013 D 5.05 5.15 5.26 0.199 0.203 0.207 D1 4.80 4.90 5.00 0.189 0.193 0.197 D2 3.56 3.76 3.91 0.140 0.148 0.154 D3 1.32 1.50 1.68 0.052 0.059 0.066 D4 0.57 typ. 0.0225 typ. D5 3.98 typ. 0.157 typ. E 6.05 6.15 6.25 0.238 0.242 0.246 E1 5.79 5.89 5.99 0.228 0.232 0.236 E2 3.48 3.66 3.84 0.137 0.144 0.151 E3 3.68 3.78 3.91 0.145 0.149 0.154 E4 0.75 typ. 0.030 typ. e 1.27 BSC 0.050 BSC K 1.27 typ. 0.050 typ. K1 0.56 - - 0.022 - - H 0.51 0.61 0.71 0.020 0.024 0.028 L 0.51 0.61 0.71 0.020 0.024 0.028 L1 0.06 0.13 0.20 0.002 0.005 0.008  0° - 12° 0° - 12° W 0.15 0.25 0.36 0.006 0.010 0.014 M 0.125 typ. 0.005 typ. ECN: S17-0173-Rev. L, 13-Feb-17 DWG: 5881 Revison: 13-Feb-17 1 Document Number: 71655 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

VISHAY SILICONIX www.vishay.com Power MOSFETs Application Note AN821 PowerPAK® SO-8 Mounting and Thermal Considerations by Wharton McDaniel PowerPAK SO-8 SINGLE MOUNTING MOSFETs for switching applications are now available with The PowerPAK single is simple to use. The pin arrangement die on resistances around 1 m and with the capability to (drain, source, gate pins) and the pin dimensions are the handle 85 A. While these die capabilities represent a major same as standard SO-8 devices (see figure 2). Therefore, the advance over what was available just a few years ago, it is PowerPAK connection pads match directly to those of the important for power MOSFET packaging technology to keep SO-8. The only difference is the extended drain connection pace. It should be obvious that degradation of a high area. To take immediate advantage of the PowerPAK SO-8 performance die by the package is undesirable. PowerPAK single devices, they can be mounted to existing SO-8 land is a new package technology that addresses these issues. patterns. In this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed. THE PowerPAK PACKAGE The PowerPAK package was developed around the SO-8 package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This Standard SO-8 PowerPAK SO-8 allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 Fig. 2 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger The minimum land pattern recommended to take full die than a standard SO-8. In fact, this larger die is slightly advantage of the PowerPAK thermal performance see larger than a full sized DPAK die. The bottom of the die Application Note 826, Recommended Minimum Pad attach pad is exposed for the purpose of providing a direct, Patterns With Outline Drawing Access for Vishay Siliconix low resistance thermal path to the substrate the device is MOSFETs. Click on the PowerPAK SO-8 single in the index mounted on. Finally, the package height is lower than the of this document. standard SO-8, making it an excellent choice for applications with space constraints. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance A from the foot of the PowerPAK to the PC board and P therefore to the ambient. Note that increasing the drain land P area beyond a certain point will yield little decrease L in foot-to-board and foot-to-ambient thermal resistance. I Under specific conditions of board configuration, copperC weight and layer stack, experiments have found thatA more than about 0.25 in2 to 0.5 in2 of additional copperT (in addition to the drain land) will yield little improvement inI O thermal performance. N N Fig. 1 PowerPAK 1212 Devices O T Revision: 16-Mai-13 1 Document Number: 71622 E For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Application Note AN821 www.vishay.com Vishay Siliconix PowerPAK® SO-8 Mounting and Thermal Considerations PowerPAK SO-8 DUAL For the lead (Pb)-free solder profile, see www.vishay.com/doc?73257. The pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8. As in the single-channel package, the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns. To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document. The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the Fig. 3 Solder Reflow Temperature Profile PowerPAK SO-8 dual package. REFLOW SOLDERING Ramp-Up Rate + 3 °C /s max. Temperature at 150 - 200 °C 120 s max. Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder Temperature Above 217 °C 60 - 150 s reflow as a test preconditioning and are then Maximum Temperature 255 + 5/- 0 °C reliability-tested using temperature cycle, bias humidity, Time at Maximum 30 s HAST, or pressure pot. The solder reflow temperature profile Temperature used, and the temperatures and time duration, are shown in Ramp-Down Rate + 6 °C/s max. figures 3 and 4. 30 s 260 °C 3 °C(max) 6 °C /s (max.) 217 °C 150 - 200 °C 150 s (max.) 60 s (min.) Reflow Zone E Pre-Heating Zone T O N Maximum peak temperature at 240 °C is allowed. N O I T Fig. 4 Solder Reflow Temperatures and Time Durations A C I L P PRevision: 16-Mai-13 2 Do cument Number: 71622 A For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Application Note AN821 www.vishay.com Vishay Siliconix PowerPAK® SO-8 Mounting and Thermal Considerations THERMAL PERFORMANCE Introduction Because of the presence of the trough, this result suggests A basic measure of a device’s thermal performance a minimum performance improvement of 10 °C/W by using is the junction-to-case thermal resistance, R , or the a PowerPAK SO-8 in a standard SO-8 PC board mount. thJC junction-to-foot thermal resistance, R This parameter is The only concern when mounting a PowerPAK on a thJF measured for the device mounted to an infinite heat sink and standard SO-8 pad pattern is that there should be no traces is therefore a characterization of the device only, in other running between the body of the MOSFET. Where the words, independent of the properties of the object to which standard SO-8 body is spaced away from the pc board, the device is mounted. Table 1 shows a comparison of allowing traces to run underneath, the PowerPAK sits the DPAK, PowerPAK SO-8, and standard SO-8. The directly on the pc board. PowerPAK has thermal performance equivalent to the Thermal Performance - Spreading Copper DPAK, while having an order of magnitude better thermal Designers may add additional copper, spreading copper, to performance over the SO-8. the drain pad to aid in conducting heat from a device. It is TABLE 1 - DPAK AND POWERPAK SO-8 helpful to have some information about the thermal EQUIVALENT STEADY STATE performance for a given area of spreading copper. PERFORMANCE Figure 6 shows the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in., four-layer FR-4 PC board. PowerPAK Standard DPAK The two internal layers and the backside layer are solid SO-8 SO-8 copper. The internal layers were chosen as solid copper to Thermal 1.2 °C/W 1 °C/W 16 °C/W model the large power and ground planes common in many Resistance R thJC applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance Thermal Performance on Standard SO-8 Pad Pattern measurements were taken. The results indicate that an area Because of the common footprint, a PowerPAK SO-8 above 0.3 to 0.4 square inches of spreading copper gives no can be mounted on an existing standard SO-8 pad pattern. additional thermal performance improvement. A The question then arises as to the thermal performance subsequent experiment was run where the copper on the of the PowerPAK device under these conditions. A back-side was reduced, first to 50 % in stripes to mimic characterization was made comparing a standard SO-8 and circuit traces, and then totally removed. No significant effect a PowerPAK device on a board with a trough cut out was observed. underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in figure 5. (0 %R, t5h 0v s%. ,S 1p0re0a %di nBga Ccko pCpoeprper) 56 Si4874DY vs. Si7446DP PPAK on a 4-Layer Board SO-8 Pattern, Trough Under Drain 60 )s 51 tta 50 w/C )s ( e ttaw 40 cna 46 E /( eC Si4874DY depm T cn 30 I O adep Si7446DP 41 100 % m 0 % N I 20 50 % N 10 36 O 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 I Spreading Copper (sq in) T 0 A 0.0001 0.01 1 100 10000 Fig. 6 Spreading Copper Junction-to-Ambient Performance C Pulse Duration (sec) I Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal L Path P PRevision: 16-Mai-13 3 Do cument Number: 71622 A For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Application Note AN821 www.vishay.com Vishay Siliconix PowerPAK® SO-8 Mounting and Thermal Considerations SYSTEM AND ELECTRICAL IMPACT OF Suppose each device is dissipating 2.7 W. Using the PowerPAK SO-8 junction-to-foot thermal resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the die In any design, one must take into account the change in temperature is determined to be 107 °C for the PowerPAK MOSFET R with temperature (figure 7). DS(on) (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the PowerPAK On-Resistance vs. Junction Temperature and a 43 °C rise for the standard SO-8. Referring to figure 7, 1.8 a 2 °C difference has minimal effect on R whereas a DS(on) )dezilam 1.6 VID G =S 2=3 1 0 A V M43in °iCm idziifnfegr tehnec teh hearms aal sriisgen iafibcoavnet ethffee cbto oanrd R tDeSm(opn)e. rature by roN using PowerPAK has not only eased the thermal design but ( ) 1.4 it has allowed the device to run cooler, keep rDS(on) low, and ( e permits the device to handle more current than the same c na 1.2 MOSFET die in the standard SO-8 package. ts is e R CONCLUSIONS -n 1.0 O - PowerPAK SO-8 has been shown to have the same thermal )n 0.8 performance as the DPAK package while having the same o (S footprint as the standard SO-8 package. The PowerPAK D R SO-8 can hold larger die approximately equal in size to the 0.6 -50 -25 0 25 50 75 100 125 150 maximum that the DPAK can accommodate implying no sacrifice in performance because of package limitations. TJ - Junction Temperature (°C) Recommended PowerPAK SO-8 land patterns are provided Fig. 7 MOSFET R vs. Temperature to aid in PC board layout for designs using this new DS(on) A MOSFET generates internal heat due to the current package. passing through the channel. This self-heating raises the Thermal considerations have indicated that significant junction temperature of the device above that of the PC advantages can be gained by using PowerPAK SO-8 board to which it is mounted, causing increased power devices in designs where the PC board was laid out for dissipation in the device. A major source of this problem lies the standard SO-8. Applications experimental data gave in the large values of the junction-to-foot thermal resistance thermal performance data showing minimum and of the SO-8 package. typical thermal performance in a SO-8 environment, plus PowerPAK SO-8 minimizes the junction-to-board thermal information on the optimum thermal performance resistance to where the MOSFET die temperature is very obtainable including spreading copper. This further close to the temperature of the PC board. Consider two emphasized the DPAK equivalency. devices mounted on a PC board heated to 105 °C by other PowerPAK SO-8 therefore has the desired small size components on the board (figure 8). characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package. PowerPAK SO-8 Standard SO-8 107 °C 148 °C E T O N 0.8 °C/W 16 C/W N PC Board at 105 °C O I T A C I L Fig. 8 Temperature of Devices on a PC Board P PRevision: 16-Mai-13 4 Do cument Number: 71622 A For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single 0.260 (6.61) 0.150 (3.81) 0.024 (0.61) (00..06266) 0.154 (3.91) 0.174 (4.42) 0.050 (1.27) 0.050 0.032 0.040 (1.27) (0.82) (1.02) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index A P P L I C A T I O N N O T E Document Number: 72599 www.vishay.com Revision: 21-Jan-08 15

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