Si6954ADQ Vishay Siliconix N-Channel 2.5-V (G-S) Battery Switch FEATURES PRODUCT SUMMARY • Halogen-free V (V) R (Ω) I (A) DS DS(on) D (cid:129) TrenchFET® Power MOSFETs: 2.5 V Rated 0.053 at VGS = 10 V 3.4 30 RoHS 0.075 at VGS = 4.5 V 2.9 COMPLIANT D1 D2 TSSOP-8 D1 1 8 D2 G1 G2 S1 2 7 S2 S1 3 6 S2 G1 4 5 G2 Top View S1 S2 Ordering Information: Si6954ADQ-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol 10 s Steady State Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a TTAA == 2750 °°CC ID 32..47 32..15 A Pulsed Drain Current (10 µs Pulse Width) IDM 20 Continuous Source Current (Diode Conduction)a IS 0.83 0.69 TA = 25 °C 1.0 0.83 Maximum Power Dissipationa PD W TA = 70 °C 0.96 0.53 Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit t ≤ 10 s 90 125 Maximum Junction-to-Ambienta RthJA Steady State 126 150 °C/W Maximum Junction-to-Foot (Drain) Steady State RthJF 65 80 Notes: a. Surface Mounted on 1" x 1" FR4 board. Document Number: 71130 www.vishay.com S-81221-Rev. C, 02-Jun-08 1

Si6954ADQ Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V 100 nA VDS = 30 V, VGS = 0 V 1 Zero Gate Voltage Drain Current IDSS µA VDS = 30 V, VGS = 0 V, TJ = 55 °C 10 On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 20 A VGS = 10 V, ID = 3.4 A 0.044 0.053 Drain-Source On-State Resistancea RDS(on) Ω VGS = 4.5 V, ID = 2.9 A 0.062 0.075 Forward Transconductancea gfs VDS = 15 V, ID = 3.4 A 10 S Diode Forward Voltagea VSD IS = 0.83 A, VGS = 0 V 0.8 1.2 V Dynamicb Total Gate Charge Qg 8 16 Gate-Source Charge Qgs VDS = 10 V, VGS = 10 V, ID = 3.4 A 1.4 nC Gate-Drain Charge Qgd 1.2 Turn-On Delay Time td(on) 12 20 Rise Time tr VDD = 10 V, RL = 10 Ω 10 20 Turn-Off Delay Time td(off) ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω 23 45 ns Fall Time tf 8 15 Source-Drain Reverse Recovery Time trr IF = 0.83 A, dI/dt = 100 A/µs 25 40 Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 20 20 VGS = 10 thru 5 V 16 16 4 V A) A) nt ( 12 nt ( 12 e e urr urr C C n n ai 8 ai 8 Dr Dr - - D D I I 4 3 V 4 TC = 125 °C 25 °C - 55 °C 0 0 0 1 2 3 4 0 1 2 3 4 5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics www.vishay.com Document Number: 71130 2 S-81221-Rev. C, 02-Jun-08

Si6954ADQ Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.15 600 500 0.12 )Ω Ciss esistance ( 0.09 VGS = 4.5 V ance (pF) 400 n-R acit 300 O p - S(on) 0.06 VGS = 10 V C - Ca 200 RD 0.03 Coss 100 Crss 0.00 0 0 4 8 12 16 20 0 6 12 18 24 30 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance 10 1.8 VDS = 10 V VGS = 10 V V) 8 ID = 3.4 A 1.6 ID = 3.4 A e ( e g c a n Gate-to-Source Volt 46 - On-ResistaDS(on)(Normalized) 111...024 - R S G 2 V 0.8 0 0.6 0 2 4 6 8 -50 -25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 0.15 20 TJ = 150 °C 10 )Ω 0.12 nt (A) nce ( e Curre Resista 0.09 ID = 3.4 A - SourcIS TJ = 25 °C - On-S(on) 0.06 D R 0.03 1 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Document Number: 71130 www.vishay.com S-81221-Rev. C, 02-Jun-08 3

Si6954ADQ Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.4 30 0.2 25 ID = 250 µA e (V) 0.0 20 anc W) Vari -0.2 er ( 15 w h) o S(t P G -0.4 10 V -0.6 5 -0.8 0 -50 -25 0 25 50 75 100 125 150 10-3 10-2 10-1 1 10 100 600 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 2 1 nt Duty Cycle = 0.5 e e Transiedance 0.2 ctivmp Notes: ed Effeermal I 0.1 0.1 PDM malizTh 0.05 t1 Nor 0.02 1. Duty Cyclet,2 D = t1 t2 2. Per Unit Base = RthJA = 126°C/W Single Pulse 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 nt Duty Cycle = 0.5 e e Transiedance 0.2 ctivmp ed Effeermal I 0.1 0.1 zh aliT 0.05 m Nor 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?71130. www.vishay.com Document Number: 71130 4 S-81221-Rev. C, 02-Jun-08

Package Information Vishay Siliconix (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:6)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12) JEDEC Part Number: MO-153 (cid:13)(cid:14)(cid:9)(cid:9)(cid:14)(cid:13)(cid:10)(cid:1)(cid:10)(cid:15)(cid:2) Dim Min Nom Max A – – 1.20 A1 0.05 0.10 0.15 E1 A2 0.80 1.00 1.05 B 0.19 0.28 0.30 C – 0.127 – D 2.90 3.00 3.10 e) E 6.20 6.40 6.60 n a Pl E1 4.30 4.40 4.50 e R 0.10 D ag e – 0.65 – Corners) e E 5 (G L 0.45 0.60 0.75 AA2 C 0.2 L1 0.90 1.00 1.10 Y – – 0.10 A1 B R 0.10 L (cid:1)K1 (cid:1)K1 0(cid:2) 3(cid:2) 6(cid:2) (4 Corners) L1 ECN: S-03946—Rev. G, 09-Jul-01 DWG: 5844 Document Number: 71201 www.vishay.com 06-Jul-01 1

AN1001 Vishay Siliconix (cid:1) LITTLE FOOT TSSOP-8 The Next Step in Surface-Mount Power MOSFETs Wharton McDaniel and David Oldham When Vishay Siliconix introduced its LITTLE FOOT This is the low profile demanded by applications such as MOSFETs, it was the first time that power MOSFETs had been PCMCIA cards. offered in a true surface-mount package, the SOIC. LITTLE FOOT immediately found a home in new small form factor disk It reduces the power package to the same height as many drives, computers, and cellular phones. resistors and capacitors in 0805 and 0605 sizes. It also allows placement on the “passive” side of the PC board. The new LITTLE FOOT TSSOP-8 power MOSFETs are the natural evolutionary response to the continuing demands of The standard pinouts of the LITTLE FOOT TSSOP-8 many markets for smaller and smaller packages. LITTLE packages have been changed from the standard established FOOT TSSOP-8 MOSFETs have a smaller footprint and a by LITTLE FOOT. This change minimizes the contribution of lower profile than LITTLE FOOT SOICs, while maintaining low interconnection resistance to rDS(on) and maximizes the r and high thermal performance. Vishay Siliconix has transfer of heat out of the package. DS(on) accomplished this by putting one or two high-density MOSFET die in a standard 8-pin TSSOP package mounted on a custom Figure 2 shows the pinouts for a single-die TSSOP. Notice that leadframe. both sides of the package have Source and Drain connections, whereas LITTLE FOOT has the Source and Gate connections on one side of the package, and the Drain connections are on the opposite side. THE TSSOP-8 PACKAGE LITTLE FOOT TSSOP-8 power MOSFETs require approximately half the PC board area of an equivalent LITTLE Drain Drain FOOT device (Figure 1). In addition to the reduction in board Source Source area, the package height has been reduced to 1.1 mm. Source Source Gate Drain Figure 2. Pinouts for Single Die TSSOP Figure 3 shows the standard pinouts for a dual-die TSSOP-8. In this case, the connections for each individual MOSFET Top View occupy one side. Drain 1 Drain 2 Source 1 Source 2 Side View Source 1 Source 2 Gate 1 Gate 2 Figure 1. An TSSOP-8 Package Next to a SOIC-8 Package with Views from Both Top and Side Figure 3. Pinouts for Dual-Die TSSOP Document Number: 70571 www.vishay.com 12-Dec-03 1

AN1001 Vishay Siliconix Because the TSSOP has a fine pitch foot print, the pad layout is somewhat more demanding than the layout of the SOIC. Careful attention must be paid to silkscreen-to-pad and soldermask-to-pad clearances. Also, fiduciary marks may be required. The design and spacing of the pads must be dealt with carefully. The pads must be sized to hold enough solder paste to form a good joint, but should not be so large or so placed as to extend under the body, increasing the potential for Figure 5. solder bridging. The pad pattern should allow for typical pick and place errors of 0.25 mm. See Application Note 826, The actual test is based on dissipating a known amount of Recommended Minimum Pad Patterns With Outline power in the device for a known period of time so the junction Drawing Access for Vishay Siliconix MOSFETs, temperature is raised to 150(cid:2)C. The starting and ending (http://www.vishay.com/doc?72286), for the recommended junction temperatures are determined by measuring the pad pattern for PC board layout. forward drop of the body diode. The thermal resistance for that pulse width is defined by the temperature rise of the junction THERMAL ISSUES above ambient and the power of the pulse, (cid:1)Tja/P. Figure 6 shows the single pulse power curve of the Si6436DQ LITTLE FOOT TSSOP MOSFETs have been given thermal laid over the curve of the Si9936DY to give a comparison of the ratings using the same methods used for LITTLE FOOT. The thermal performance. The die in the two devices have maximum thermal resistance junction-to-ambient is 83(cid:2)C/W equivalent die areas, making this a comparison of the for the single die and 125(cid:2)C/W for dual-die parts. TSSOP relies packaging. This comparison shows that the TSSOP package on a leadframe similar to LITTLE FOOT to remove heat from performs as well as the SOIC out to 150 ms, with long-term the package. The single- and dual-die leadframes are shown performance being 0.5 W less. Although the thermal in Figure 4. performance is less, LITTLE FOOT TSSOP will operate in a large percentage of applications that are currently being served by LITTLE FOOT. 14.0 12.0 10.0 a) 8-Pin Single-Pad TSSOP W) 8.0 er ( w Po 6.0 4.0 Si9936 2.0 Si6436 0.0 0.1 1 10 100 b) 8-Pin Dual-Pad TSSOP Time (Sec.) Figure 6. Comparison of Thermal Performance Figure 4. Leadframe CONCLUSION The MOSFETs are characterized using a single pulse power test. For this test the device mounted on a one-square-inch piece of copper clad FR-4 PC board, such as those shown in TSSOP power MOSFETs provide a significant reduction in PC Figure 5. The single pulse power test determines the board footprint and package height, allowing reduction in maximum amount of power the part can handle for a given board size and application where SOICs will not fit. This is pulse width and defines the thermal resistance accomplished using a standard IC package and a custom junction-to-ambient. The test is run for pulse widths ranging leadframe, combining small size with good power handling from approximately 10 ms to 100 seconds. The thermal capability. resistance at 30 seconds is the rated thermal resistance for the part. This rating was chosen to allow comparison of packages For the TSSOP-8 package outline visit: and leadframes. At longer pulse widths, the PC board thermal http://www.vishay.com/doc?71201 charateristics become dominant, making all parts look the For the SOIC-8 package outline visit: same. http://www.vishay.com/doc?71192 www.vishay.com Document Number: 70571 2 12-Dec-03

AN806 Vishay Siliconix (cid:1) Mounting LITTLE FOOT TSSOP-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated The pad patterns with copper spreading for the single-MOSFET circuit and small-signal packages which have been been modified TSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2) to provide the heat transfer capabilities required by power devices. show the starting point for utilizing the board area available for the Leadframe materials and design, molding compounds, and die heat-spreading copper. To create this pattern, a plane of copper attach materials have been changed, while the footprint of the overlies the drain pins. The copper plane connects the drain pins packages remains the same. electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFET, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT TSSOP-8 power MOSFET 0.284 7.6 package footprint. In converting the footprint to the pad set for a power device, designers must make two connections: an electrical 0.032 0.8 connection and a thermal connection, to draw heat away from the 0.026 0.122 package. 0.66 3.1 0.018 0.45 0.073 0.091 In the case of the TSSOP-8 package, the thermal connections 1.78 1.65 are very simple. Pins 1, 5, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern with the dual package, pins 1 and 8 are the two drains. For a Copper Spreading small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins also provide the thermal connection to the Since surface-mounted packages are small, and reflow soldering package, this level of connection is inadequate. The total is the most common way in which these are affixed to the PC cross section of the copper may be adequate to carry the board, “thermal” connections from the planar copper to the pads current required for the application, but it presents a large have not been used. Even if additional planar copper area is used, thermal impedance. Also, heat spreads in a circular fashion there should be no problems in the soldering process. The actual from the heat source. In this case the drain pins are the heat solder connections are defined by the solder mask openings. By sources when looking at heat spread on the PC board. combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. 0.284 A final item to keep in mind is the width of the power traces. The 7.6 absolute minimum power trace width must be determined by the 0.032 amount of current it has to carry. For thermal reasons, this 0.8 minimum width should be at least 0.020 inches. The use of wide 0.026 0.122 0.66 3.1 traces connected to the drain plane provides a low impedance 0.018 path for heat to move away from the device. 0.45 0.073 0.118 1.78 3.54 FIGURE 1. Single MOSFET TSSOP-8 Pad Pattern with Copper Spreading Document Number: 70738 www.vishay.com 17-Dec-03 1

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR TSSOP-8 0.092 (2.337) 0.026 (0.660) 2 5) 2 3) 6 5 8 2 2 6 1 6 0. 6. 0. 4. ( ( 0 6) 4 1 0 0 0. 1. ( 0.014 0.012 (0.356) (0.305) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index A P P L I C A T I O N N O T E Document Number: 72611 www.vishay.com Revision: 21-Jan-08 27

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