Si6924AEDQ Vishay Siliconix N-Channel 2.5-V (G-S) Battery Switch, ESD Protection FEATURES PRODUCT SUMMARY • Halogen-free V (V) R (Ω) I (A) DS DS(on) D (cid:129) Low R 0.033 at VGS = 4.5 V 4.6 DS(on) (cid:129) VGS Max Rating: 14 V RoHS 28 0.038 at VGS = 3.0 V 4.3 (cid:129) Exceeds 2 kV ESD Protection COMPLIANT 0.042 at VGS = 2.5 V 4.1 (cid:129) 28 V V Rated DS (cid:129) Symmetrical Voltage Blocking (Off Voltage) DESCRIPTION The Si6924AEDQ is a dual N-Channel MOSFET with ESD stage diode is designed to protect the gate from any protection and gate over-voltage protection circuitry remaining ESD energy and over-voltages above the gates incorporated into the MOSFET. The device is designed for inherent safe operating range. The series resistor used to use in Lithium Ion battery pack circuits. The common-drain limit the current through the second stage diode during over construction takes advantage of the typical battery pack voltage conditions has a maximum value which limits the topology, allowing a further reduction of the device’s on- input current to ≤ 10 mA at 14 V and the maximum t to 12 off resistance. The 2-stage input protection circuit is a unique µs. The Si6924AEDQ has been optimized as a battery or design, consisting of two stages of back-to-back zener load switch in Lithium Ion applications with the advantage of diodes separated by a resistor. The first stage diode is both a 2.5 V R rating and a safe 14 V gate-to-source DS(on) designed to absorb most of the ESD energy. The second maximum rating. APPLICATION CIRCUITS D ESD and ESD and Overvoltage Overvoltage Protection Protection R** G S Battery Protection Circuit **R typical value is 3.3 kΩ by design. See Typical Characteristics, *Thermal connection to drain pins is required to achieve specific performance Gate-Current vs. Gate-Source Voltage, Page 3. Figure 1. Typical Use In a Lithium Ion Battery Pack Figure 2. Input ESD and Overvoltage Protection Circuit Document Number: 72215 www.vishay.com S-81056-Rev. B, 12-May-08 1

Si6924AEDQ Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION *D *D 3.3 kΩ 3.3 kΩ TSSOP-8 G1 G2 D 1 8 D S1 2 Si6924AEDQ 7 S2 S1 3 6 S2 G1 4 5 G2 S1 S2 Top View N-Channel N-Channel Ordering Information:Si6924AEDQ-T1-GE3 (Lead (Pb)-free and Halogen-free) *Thermal connection to drain pins is required to achieve specific performance. Figure 3. Figure 4. ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol 10 s Steady State Unit Drain-Source Voltage, Source-Drain Voltage VDS 28 V Gate-Source Voltage VGS ± 14 Continuous Drain-to-Source Current (TJ = 150 °C)a TTAA == 2750 °°CC ID 43..67 43..12 A Pulsed Drain-to-Source Current IDM 20 Pulsed Source Current (Diode Conduction)a IS 1.2 0.9 TA = 25 °C 1.3 1.0 Maximum Power Dissipationa PD W TA = 70 °C 0.84 0.64 Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit t ≤ 10 s 71 95 Maximum Junction-to-Ambienta RthJA Steady State 96 125 °C/W Maximum Junction-to-Foot (Drain) Steady State RthJF 56 70 Notes: a. Surface Mounted on FR4 board. www.vishay.com Document Number: 72215 2 S-81056-Rev. B, 12-May-08

Si6924AEDQ Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 0.6 1.5 V VDS = 0 V, VGS = ± 4.5 V ± 1 µA Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 14 V ± 20 mA VDS = 22.4 V, VGS = 0 V 1 Zero Gate Voltage Drain Current IDSS µA VDS = 22.4 V, VGS = 0 V, TJ = 55 °C 5 On-State Drain Currentb ID(on) VDS ≥ 5 V, VGS = 5 V 10 A VGS = 4.5 V, ID = 4.6 A 0.022 0.033 Drain-Source On-State Resistanceb RDS(on) VGS = 3.0 V, ID = 4.3 A 0.025 0.038 Ω VGS = 2.5 V, ID = 4.1 A 0.029 0.042 Forward Transconductanceb gfs VDS = 10 V, ID = 4.6 A 25 S Diode Forward Voltageb VSD IS = 1.2 A, VGS = 0 V 0.7 1.1 V Dynamica Total Gate Charge Qg 6.5 10 Gate-Source Charge Qgs VDS = 10 V, VGS = 4.5 V, ID = 4.6 A 1.2 nC Gate-Drain Charge Qgd 1.5 Turn-On Delay Time td(on) 0.95 1.5 Rise Time tr VDD = 10 V, RL = 10 Ω 1.4 2.1 µs Turn-Off Delay Time td(off) ID ≅ 1 A, VGEN = 4.5 V, RG = 6 Ω 7 11 Fall Time tf 3.1 5 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.020 10,000 1,000 mA) 0.015 A) 100 Current ( Current ( 10 TJ = 150 °C Gate 0.010 Gate 1 - - S S GS GS 0.1 I 0.005 I TJ = 25 °C 0.01 0.000 0.001 0 3 6 9 12 15 0 2 4 6 8 10 12 14 VGS - Gate-to-Source Voltage (V) VGS -Gate-to-Source Voltage (V) Gate-Current vs. Gate-Source Voltage Gate Current vs. Gate-Source Voltage Document Number: 72215 www.vishay.com S-81056-Rev. B, 12-May-08 3

Si6924AEDQ Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 25 25 VGS = 5 thru 2,5 V 20 20 - Drain Current (A)D 1105 2 V - Drain Current (A)D 1105 I I TC = 125 °C 5 5 25 °C - 55 °C 0 0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.05 5 )Ω 0.04 ge (V) 4 IVDD =S 4=. 61 0A V nce ( Volta sta 0.03 VGS = 2.5 V ce 3 Resi Sour n- o- - OS(on) 0.02 VGS = 3 V VGS = 4.5 V - Gate-t 2 RD 0.01 GS 1 V 0.00 0 0 4 8 12 16 20 0 1 2 3 4 5 6 7 ID - Drain Current (A) Qg - Total Gate Charge (nC) On-Resistance vs. Drain Current Gate Charge 1.8 20 VGS = 4.5 V 1.6 ID = 4.6 A 10 e - On-ResistancRDS(on)(Normalized) 111...024 - Source Current (A)S TJ = 150 °C TJ = 25 °C I 0.8 0.6 1 - 50 - 25 0 25 50 75 100 125 150 0 0.4 0.6 0.8 1.0 1.2 TJ - Junction Temperature (°C) VSD - Source-to-Drain Voltage (V) On-Resistance vs. Junction Temperature Source-Drain Diode Forward Voltage www.vishay.com Document Number: 72215 4 S-81056-Rev. B, 12-May-08

Si6924AEDQ Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.10 0.4 ID = 250 µA 0.08 0.2 )Ω e ( V) Resistanc 0.06 IIDD == 44..66 AA Variance ( 0.0 - On-on) 0.04 VGS(th) -0.2 S( D R 0.02 -0.4 0.00 -0.6 0 1 2 3 4 5 - 50 - 25 0 25 50 75 100 125 150 VVGS -- GGaattee--ttoo--SSoouurrccee VVoollttaaggee ((VV)) TJ - Temperature (°C) On-Resistance vs. Gate-to-Source Voltage Threshold Voltage 100 60 Limited by R D S (o n )* 50 10 40 A) 1 ms W) ent ( er ( 30 Curr 1 Pow ain 10 ms Dr 20 - 100 ms D I 0.1 TC = 25 °C 1 s 10 Single Pulse 10 s DC 0 0.01 0.001 0.01 0.1 1 10 0.1 1 10 100 Time (s) VD S -Drain-to-SourceVoltage(V) Single Pulse Power *VGS>minimumVGSatwhichRDS(on)isspecified Safe Operating Area 2 1 nt Duty Cycle = 0.5 e ed Effective Transiermal Impedance 0.1 000...2105 NPoDteMs: NormalizTh 0.02 1. Duty Cytc1le, tD2 = tt12 2. Per Unit Base = RthJA = 96 °C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Document Number: 72215 www.vishay.com S-81056-Rev. B, 12-May-08 5

Si6924AEDQ Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 2 1 nt Duty Cycle = 0.5 e ctive Transimpedance 0.2 zed Effehermal I 0.1 00..105 aliT m or 0.02 N Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72215. www.vishay.com Document Number: 72215 6 S-81056-Rev. B, 12-May-08

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