Si4136/Si4126 ISM RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS Features  Dual-band RF synthesizers  Minimal external components RF1: 2300MHz to 2500MHz required RF2: 2025MHz to 2300MHz  Low phase noise  IF synthesizer  5µA standby current 62.5MHz to 1000MHz  25.7mA typical supply current Ordering Information:  Integrated VCOs, loop filters,  2.7V to 3.6V operation varactors, and resonators  Packages: 24-pin TSSOP, See page29. 28-lead QFN Lead-free/RoHS-compliant options available Pin Assignments Applications Si4136-GT  ISM and MMDS band  Dual-band communications communications SCLK 1 24 SEN  Wireless LAN and WAN SDATA 2 23 VDDI GND 3 22 IFOUT Description GND 4 21 GND The Si4136 is a monolithic integrated circuit that performs both IF and RF NC 5 20 IFLB synthesis for wireless communications applications. The Si4136 includes GND 6 19 IFLA three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and powerdown settings are programmable through a three-wire NC 7 18 GND serial interface. GND 8 17 VDDD GND 9 16 GND Functional Block Diagram GND 10 15 XIN RFOUT 11 14 PWDN XIN RAemfeprleifniecre ÷1/÷2 RRF1 Phase VDDR 12 13 AUXOUT Detect Power RF1 PWDN Down Si4136-GM Control NRF1 2 RFOUT SDSACTLKA InSteerrfiaacle RRF2 DPheatescet GND SDATA SCLK SEN VDDI IFOUT GND 22-bit RF2 28 27 26 25 24 23 22 SEN Data Register NRF2 2 GND 1 21 GND GND 2 20 IFLB AUXOUT Test RIF Phase IFDIV IFOUT NC 3 19 IFLA Mux Detect IF GND 4 GND 18 GND N IFLA NC 5 17 VDDD IF IFLB GND 6 16 GND GND 7 15 XIN 8 9 10 11 12 13 14 GND GND OUT DDR OUT WDN GND RF V UX P A Patents pending Rev. 1.42 Copyright © 2014 by Silicon Laboratories Si4136/Si4126 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).

Si4136/Si4126 2 Rev. 1.42

Si4136/Si4126 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.2. Setting the IF VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3. Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.4. Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.5. PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.6. RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.7. Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.8. Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.9. Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4. Pin Descriptions: Si4136-GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5. Pin Descriptions: Si4136-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 7. Si4136 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8. Package Outline: Si4136-GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9. Package Outline: Si4136-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 1.42 3

Si4136/Si4126 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Ambient Temperature T –40 25 85 °C A Supply Voltage V 2.7 3.0 3.6 V DD Supply Voltages Difference V (V – V ), –0.3 — 0.3 V  DDR DDD (V – V ) DDI DDD Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit DC Supply Voltage V –0.5 to 4.0 V DD Input Current3 IIN ±10 mA Input Voltage3 VIN –0.3 to VDD+0.3 V Storage Temperature Range TSTG –55 to 150 oC Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of <2kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SEN, PWDN, and XIN. 4 Rev. 1.42

Si4136/Si4126 Table 3. DC Characteristics (V = 2.7 to 3.6V, T = –40 to 85°C) DD A Parameter Symbol Test Condition Min Typ Max Unit Total Supply Current1 RF1 and IF operating — 25.7 31 mA RF1 Mode Supply Current1 — 15.7 19 mA RF2 Mode Supply Current1 — 15 18 mA IF Mode Supply Current1 — 10 12 mA Standby Current PWDN=0 — 1 — µA High Level Input Voltage2 V 0.7V — — V IH DD Low Level Input Voltage2 V — — 0.3V V IL DD High Level Input Current2 I V =3.6 V, –10 — 10 µA IH IH V =3.6 V DD Low Level Input Current2 I V =0 V, –10 — 10 µA IL IL V =3.6 V DD High Level Output Voltage3 V I =–500 µA V –0.4 — — V OH OH DD Low Level Output Voltage3 V I =500 µA — — 0.4 V OL OH Notes: 1. RF1=2.4GHz, RF2=2.1GHz, IFOUT=800MHz, LPWR=0. 2. For signals SCLK, SDATA, SEN, and PWDN. 3. For signal AUXOUT. Rev. 1.42 5

Si4136/Si4126 Table 4. Serial Interface Timing (V = 2.7 to 3.6V, T = –40 to 85°C) DD A Parameter1 Symbol Test Condition Min Typ Max Unit SCLK Cycle Time t Figure1 40 — — ns clk SCLK Rise Time t Figure1 — — 50 ns r SCLK Fall Time t Figure1 — — 50 ns f SCLK High Time t Figure1 10 — — ns h SCLK Low Time t Figure1 10 — — ns l SDATA Setup Time to SCLK2 t Figure2 5 — — ns su SDATA Hold Time from SCLK2 t Figure2 0 — — ns hold SEN to SCLKDelay Time2 t Figure2 10 — — ns en1 SCLK to SENDelay Time2 t Figure2 12 — — ns en2 SEN to SCLKDelay Time2 t Figure2 12 — — ns en3 SEN Pulse Width t Figure2 10 — — ns w Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure2. t t r f 80% SCLK 50% 20% t t h l t clk Figure1.SCLK Timing Diagram 6 Rev. 1.42

Si4136/Si4126 A A Figure2.Serial Interface Timing Diagram First bit Last bit clocked in clocked in D D D D D D D D D D D D D D D D D D A A A A 1716151413121110 9 8 7 6 5 4 3 2 1 0 3 2 1 0 data address field field Figure3.Serial Word Format Rev. 1.42 7

Si4136/Si4126 Table 5. RF and IF Synthesizer Characteristics (V = 2.7 to 3.6V, T = –40 to 85°C) DD A Parameter1 Symbol Test Condition Min Typ Max Unit XIN Input Frequency f XINDIV2 = 0 2 — 25 MHz REF XIN Input Frequency f XINDIV2 = 1 25 — 50 MHz REF Reference Amplifier Sensitivity V 0.5 — V V REF DD PP +0.3 V Phase Detector Update Frequency f f = f /R for XIN- 0.010 — 1.0 MHz   REF DIV2 = 0 f = f /2R for XIN-  REF DIV2 = 1 RF1 VCO Tuning Range2 2300 — 2500 MHz RF2 VCO Tuning Range2 2025 — 2300 MHz IF VCO Center Frequency Range f 526 — 952 MHz CEN IFOUT Tuning Range from f with IFDIV 62.5 — 1000 MHz CEN IFOUT VCO Tuning Range from f Note: L ±10% –5 — 5 % CEN RF1 VCO Pushing Open loop — 0.75 — MHz/V RF2 VCO Pushing — 0.65 — MHz/V IF VCO Pushing — 0.10 — MHz/V RF1 VCO Pulling VSWR = 2:1, all — 0.250 — MHz p-p phases, open loop RF2 VCO Pulling — 0.100 — MHz p-p IF VCO Pulling — 0.025 — MHz p-p RF1 Phase Noise 1MHz offset — –130 — dBc/Hz RF1 Integrated Phase Error 100Hz to 100kHz — 1.2 — degrees rms RF2 Phase Noise 1MHz offset — –131 — dBc/Hz RF2 Integrated Phase Error 100Hz to 100kHz — 1.0 — degrees rms IF Phase Noise at 800MHz 100kHz offset — –104 — dBc/Hz IF Integrated Phase Error 100Hz to 100kHz — 0.4 — degrees rms Notes: 1. f (RF)=1MHz, f (IF)=1MHz, RF1=2.4GHz, RF2=2.1GHz, IFOUT=800MHz, LPWR=0, for all parameters   unless otherwise noted. 2. RF VCO tuning range limits are fixed by inductance of internally bonded wires. 3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register2) to supply current equal to I . PWDN 8 Rev. 1.42

Si4136/Si4126 Table 5. RF and IF Synthesizer Characteristics (Continued) (V = 2.7 to 3.6V, T = –40 to 85°C) DD A Parameter1 Symbol Test Condition Min Typ Max Unit RF1 Harmonic Suppression Second Harmonic — –28 –20 dBc RF2 Harmonic Suppression — –23 –20 dBc IF Harmonic Suppression — –26 –20 dBc RFOUT Power Level Z =50RF1 active –7 –3.5 –0.5 dBm L RFOUT Power Level Z =50RF2 active –7 –3.5 –0.5 dBm L IFOUT Power Level Z =50 –7 –4 0 dBm L RF1 Output Reference Spurs Offset=1MHz — –63 — dBc Offset=2MHz — –68 — dBc Offset=3MHz — –70 — dBc RF2 Output Reference Spurs Offset=1MHz — –63 — dBc Offset=2MHz — –68 — dBc Offset=3MHz — –70 — dBc Powerup Request to Synthesizer Ready3 t Figures 4, 5 — 80 100 s pup Time f > 500kHz  Powerup Request to Synthesizer Ready3 t Figures 4, 5 — 40/f 50/f pup   Time f  500kHz  Powerdown Request to Synthesizer t Figures 4, 5 — — 100 ns pdn OffTime4 Notes: 1. f (RF)=1MHz, f (IF)=1MHz, RF1=2.4GHz, RF2=2.1GHz, IFOUT=800MHz, LPWR=0, for all parameters   unless otherwise noted. 2. RF VCO tuning range limits are fixed by inductance of internally bonded wires. 3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register2) to supply current equal to I . PWDN Rev. 1.42 9

Si4136/Si4126 RF synthesizers settled to within 0.1 ppm frequency error. RF synthesizers settled to within 0.1 ppm frequency error. t t pup pdn I T t t I I pup pdn PWDN T I PWDN SEN PWDN SDATA PDIB = 1 PDIB = 0 PDRB = 1 PDRB = 0 Figure4.Software Power Management Figure5.Hardware Power Management Timing Diagram Timing Diagram 10 Rev. 1.42

Si4136/Si4126 Figure6.Typical Transient Response RF1 at 2.4GHz with 1MHz Phase Detector Update Frequency Rev. 1.42 11

Si4136/Si4126 -60 -70 -80 z) -90 H c/ B d se ( -100 oi N e s a Ph -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Offset Frequency (Hz) Typical RF1 Phase Noise at 2.4 GHz Figure7.Typical RF1 Phase Noise at 2.4GHz with 1MHz Phase Detector Update Frequency Figure8.Typical RF1 Spurious Response at 2.4GHz with 1MHz Phase Detector Update Frequency 12 Rev. 1.42

Si4136/Si4126 s -60 -70 -80 z) -90 H c/ B d se ( -100 oi N e s a Ph -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Offset Frequency (Hz) Typical RF2 Phase Noise at 2.1 GHz Figure9.Typical RF2 Phase Noise at 2.1GHz with 1MHz Phase Detector Update Frequency Figure10.Typical RF2 Spurious Response at 2.1GHz with 1MHz Phase Detector Update Frequency Rev. 1.42 13

Si4136/Si4126 -60 -70 -80 Hz) -90 Bc/ d oise (-100 N e as Ph-110 -120 -130 -140 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Offset Frequency (Hz) Typical IF Phase Noise at 800 MHz Figure11.Typical IF Phase Noise at 800MHz with 1MHz Phase Detector Update Frequency Figure12.IF Spurious Response at 800MHz with 1MHz Phase Detector Update Frequency 14 Rev. 1.42

Si4136/Si4126 V Si4136 DD From 1 24 30  System SCLK SEN 0.022F Controller 2 23 SDATA VDDI L 560 pF MATCH 3 22 GND IFOUT IFOUT 4 21 GND GND Printed Trace 5 20 NC IFLB Inductor or Chip Inductor 6 19 GND IFLA 7 18 NC GND VDD 0.022F 8 17 GND VDDD 9 16 GND GND 560 pF 10 15 GND XIN External Clock 560 pF 11 14 RFOUT RFOUT PWDN PDWNB 0.022F VDD 12 13 VDDR AUXOUT AUXOUT *Add 30  series resistor if using IF output divide values 2, 4, or 8 and f < 600 MHz. CEN Figure13.Typical Application Circuit: Si4136-GT Rev. 1.42 15

Si4136/Si4126 2. Functional Description frequencies greater than 25MHz, the Si4136 includes a programmable divide-by-2 option (XINDIV2 in The Si4136 is a monolithic integrated circuit that Register0, D6) on the XIN input. By enabling this performs IF and dual-band RF synthesis for many option, the Si4136 can accept a range of TCXO wireless communications applications. This integrated frequencies from 25MHz to 50MHz. This feature circuit (IC), along with a minimum number of external makes the Si4136 ideal for W-LAN radio designs components, is all that is necessary to implement the operating at an XIN of 44MHz. frequency synthesis function in applications like W-LAN The unique PLL architecture used in the Si4136 using the IEEE 802.11 standard. produces settling (lock) times that are comparable in The Si4136 has three complete phase-locked loops speed to fractional-N architectures without suffering the (PLLs), with integrated voltage-controlled oscillators high phase noise or spurious modulation effects often (VCOs). The low phase noise of the VCOs makes the associated with those designs. Si4136 suitable for use in demanding wireless 2.1. Serial Interface communications applications. Also integrated are phase detectors, loop filters, and reference and output A timing diagram for the serial interface is shown in frequency dividers. The IC is programmed through a Figure2 on page 7. Figure3 on page 7 shows the three-wire serial interface. format of the serial word. Two PLLs are provided for RF synthesis. These RF The Si4136 is programmed serially with 22-bit words PLLs are multiplexed so that only one PLL is active at a comprised of 18-bit data fields and 4-bit address fields. given time (as determined by the setting of an internal When the serial interface is enabled (i.e., when SEN is register). The active PLL is the last one written. The low) data and address bits on the SDATA pin are center frequency of the VCO in each PLL is set by the clocked into an internal shift register on the rising edge internal bond wire inductance within the package. of SCLK. Data in the shift register is then transferred on Inaccuracies in these inductances are compensated for the rising edge of SEN into the internal data register by the self-tuning algorithm. The algorithm is run addressed in the address field. The serial interface is following power-up or following a change in the disabled when SEN is high. programmed output frequency. Table11 on page21 summarizes the data register The RF PLLs contain a divide-by-2 circuit before the N- functions and addresses. It is not necessary (although it divider. As a result, the phase detector frequency (f) is is permissible) to clock into the internal shift register any equal to half the desired channel spacing. For example, leading bits that are “don’t cares.” for a 200kHz channel spacing, f would equal 100kHz. 2.2. Setting the IF VCO Center Frequencies The IF PLL does not contain the divide-by-2 circuit before the N-divider. In this case, f is equal to the The IF PLL can adjust its output frequency ±5% from desired channel spacing. Each RF VCO is optimized for the center frequency as established by the value of an a particular frequency range. The RF1 VCO is optimized external inductance connected to the VCO. The RF1 to operate from 2.3GHz to 2.5GHz, while the RF2 VCO and RF2 PLLs have fixed operating ranges due to the is optimized to operate between 2.025GHz and inductance set by the internal bond wires. Each center 2.3GHz. frequency is established by the value of the total inductance (internal and/or external) connected to the One PLL is provided for IF synthesis. The center respective VCO. Manufacturing tolerance of ±10% for frequency of this circuit’s VCO is set by an external the external inductor is acceptable for the IF VCO. The inductance. The PLL can adjust the IF output frequency Si4136 will compensate for inaccuracies by executing a by ±5% of the VCO center frequency. Inaccuracies in self-tuning algorithm following PLL power-up or the value of the external inductance are compensated following a change in the programmed output for by the Si4136’s proprietary self-tuning algorithm. frequency. This algorithm is initiated each time the PLL is powered- up (by either the PWDN pin or by software) and/or each Because the total tank inductance is in the low nH time a new output frequency is programmed. The IF range, the inductance of the package needs to be VCO can have its center frequency set as low as considered in determining the correct external 526MHz and as high as 952MHz. An IF output divider inductance. The total inductance (L ) presented to TOT is provided to divide down the IF output frequencies, if the IF VCO is the sum of the external inductance (L ) EXT needed. The divider is programmable, capable of and the package inductance (L ). The IF VCO has a PKG dividing by 1, 2, 4, or 8. nominal capacitance (C ) in parallel with the total NOM inductance, and the center frequency is as follows: In order to accommodate designs running at XIN 16 Rev. 1.42

Si4136/Si4126 2.3. Self-Tuning Algorithm 1 1 fCEN = --------------------------------------------- = ---------------------------------------------------------------------- The self-tuning algorithm is initiated immediately 2 L C 2 L +L C TOT NOM PKG EXT NOM following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output Table6 summarizes the characteristics of the IF VCO. frequency. This algorithm attempts to tune the VCO so Table 6. Si4136-GT VCO Characteristics that its free-running frequency is near the desired output frequency. In so doing, the algorithm will compensate VCO Fcen Range Cnom Lpkg Lext Range for manufacturing tolerance errors in the value of the (MHz) (pF) (nH) (nH) external inductance connected to the IF VCO. It will also reduce the frequency error for which the PLL must Min Max Min Max correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a IF 526 952 6.5 2.1 2.2 12.0 frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation Si4136 frequency. The PLL will complete frequency locking, L IFLA eliminating any remaining frequency error. Thereafter, it PKG will maintain frequency-lock, compensating for effects 2 caused by temperature and supply voltage variations. L EXT The Si4136’s self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the IFLB PLL to compensate for drift in component values that L PKG occur after self-tuning is limited. For external 2 inductances with temperature coefficients around ±150 Figure14.Example of IF External Inductor ppm/°C, the PLL will be able to maintain lock for changes in temperature of approximately ±30°C. As a design example, suppose synthesizing Applications where the PLL is regularly powered-down frequencies in a 30MHz band between 735MHz and or the frequency is periodically reprogrammed minimize 765MHz is desired. The center frequency should be or eliminate the potential effects of temperature drift defined as midway between the two extremes, or because the VCO is re-tuned in either case. In 750MHz. The PLL will be able to adjust the VCO output applications where the ambient temperature can drift frequency ±5% of the center frequency, or ±37.5MHz of substantially after self-tuning, it may be necessary to 750MHz (i.e., from approximately 713MHz to monitor the lock-detect bar (LDETB) signal on the 788MHz). The IF VCO has a C of 6.5pF, and a NOM AUXOUT pin to determine whether a PLL is about to 6.9nH inductance (correct to two digits) in parallel with run out of locking capability. (See “2.9. Auxiliary Output this capacitance will yield the desired center frequency. (AUXOUT)” for how to select LDETB.) The LDETB An external inductance of 4.8nH should be connected signal will be low after self-tuning has completed but will between IFLA and IFLB, as shown in Figure14. This, in rise when either the IF or RF PLL nears the limit of its addition to 2.1nH of package inductance, will present compensation range. (LDETB will also be high when the correct total inductance to the VCO. In either PLL is executing the self-tuning algorithm.) The manufacturing, the external inductance can vary ±10% output frequency will still be locked when LDETB goes of its nominal value and the Si4136 will correct for the high, but the PLL will eventually lose lock if the variation with the self-tuning algorithm. temperature continues to drift in the same direction. For more information on designing the external trace Therefore, if LDETB goes high both the IF and RF PLLs inductor, please refer to Application Note 31. should promptly be re-tuned by initiating the self-tuning algorithm. 2.4. Output Frequencies The IF and RF output frequencies are set by programming the R- and N-Divider registers. Each PLL has its own R and N registers so that each can be Rev. 1.42 17

Si4136/Si4126 programmed independently. Programming either the R- transient until the point at which stability begins to be or N-Divider register for RF1 or RF2 automatically compromised. The optimal gain depends on N. Table8 selects the associated output. lists recommended settings for different values of N. When XINDIV2 = 0, the reference frequency on the XIN Table 8. Optimal K Settings pin is divided by R and this signal is the input to the P PLL’s phase detector. The other input to the phase RF1 RF2 IF detector is the PLL’s VCO output frequency divided by N K <1:0> K <1:0> K <1:0> 2N for the RF PLLs or N for the IF PLL. After an initial P1 P2 PI transient 2047 00 00 00 Equation1.f = (2N/R) f (for the RF PLLs) OUT  REF 2048 to 4095 00 01 01 Equation2.f = (N/R) f (for the IF PLL). OUT  REF The integers R are set by programming the RF1 R- 4096 to 8191 01 10 10 Divider register (Register6), the RF2R-Divider register (Register7) and the IF R-Divider register (Register8). 8192 to 16383 10 11 11 The integers N are set by programming the RF1 N- 16384 11 11 11 Divider register (register 3), the RF2 N-Divider register (Register4), and the IF N-Divider register (Register5). The VCO gain and loop filter characteristics are not If the optional divide-by-2 circuit on the XIN pin is programmable. enabled (XINDIV2 = 1) then after an initial transient The settling time for each PLL is directly proportional to fOUT = (N/R) fREF (for the RF PLLs) its phase detector update period T (T equals 1/f). f = (N/2R) f (for the IF PLL). During the first 13 update periods the Si4136 executes OUT REF the self-tuning algorithm. Thereafter the PLL controls Each N-Divider is implemented as a conventional high the output frequency. Because of the unique speed divider. That is, it consists of a dual-modulus architecture of the Si4136 PLLs, the time required to prescaler, a swallow counter, and a lower speed settle the output frequency to 0.1ppm error is only synchronous counter. However, the control of these about 25 update periods. Thus, the total time after sub-circuits is handled automatically. Only the power-up or a change in programmed frequency until appropriate N value should be programmed. the synthesized frequency is well settled—including 2.5. PLL Loop Dynamics time for self-tuning—is around 40 update periods. The transient response for each PLL is determined by Note: This settling time analysis holds for f 500kHz. For  its phase detector update rate f (equal to fREF/R) and f 500kHz, the settling time can be a maximum of the phase detector gain programmed for each RF1, 100s as specified in Table5. RF2, or IF synthesizer. (See Register1.) Four different 2.6. RF and IF Outputs (RFOUT and IFOUT) settings for the phase detector gain are available for each PLL. The highest gain is programmed by setting The RFOUT and IFOUT pins are driven by amplifiers the two phase detector gain bits to 00, and the lowest by that buffer the RF VCOs and IF VCO, respectively. The setting the bits to 11. The values of the available gains, RF output amplifier receives its input from either the relative to the highest gain, are listed in Table7. RF1 or RF2 VCO, depending upon which R- or N- Divider register was last written. For example, Table 7. Gain Values (Register 1) programming the N-Divider register for RF1 automatically selects the RF1 VCO output. Relative P.D. K Bits P Gain Figure13 on page 15 shows an application diagram for the Si4136. The RF output signal must be AC coupled 00 1 to its load through a capacitor. 01 1/2 The IFOUT pin must also be AC coupled to its load through a capacitor. The IF output level is dependent 10 1/4 upon the load. Figure17 displays the output level 11 1/8 versus load resistance. For resistive loads greater than 500 the output level saturates and the bias currents in In general, a higher phase detector gain will decrease the IF output amplifier are higher than they need to be. in-band phase noise and increase the speed of the PLL The LPWR bit in the Main Configuration register 18 Rev. 1.42

Si4136/Si4126 (Register0) can be set to 1 to reduce the bias currents and therefore reduce the power dissipated by the IF 450 amplifier. For loads less than 500 LPWR should be 400 set to 0 to maximize the output level. 350 LPWR=1 For IF frequencies greater than 500MHz, a matching LPWR=0 300 nFdeeigttwuerroemrk1in 5eis d rbbeeyql uoTiwareb. dle Ti9nh. eo rdvear lutoe droivf e LaM 5A0TCH locaadn. Sebee Output Voltage (mVrms)220500 Typical values range between 8nH and 40nH. 150 100 50 >500 pF IFOUT 0 0 200 400 600 800 1000 1200 Load Resistance () L MATCH Figure17.Typical IF Output Voltage vs. 50  Load Resistance at 550MHz 2.7. Reference Frequency Amplifier The Si4136 provides a reference frequency amplifier. If Figure15.IF Frequencies > 500MHz the driving signal has CMOS levels, it can be connected directly to the XIN pin. Otherwise, the reference Table 9. L Values frequency signal should be AC coupled to the XIN pin MATCH through a 560pF capacitor. Frequency L MATCH 2.8. Powerdown Modes 500–600MHz 40nH Table10 summarizes the powerdown functionality. The 600–800MHz 27nH Si4136 can be powered down by taking the PWDN pin low or by setting bits in the Powerdown register 800–1GHz 18nH (Register2). When the PWDN pin is low, the Si4136 will be powered down regardless of the Powerdown register For frequencies less than 500MHz, the IF output buffer settings. When the PWDN pin is high, power can directly drive a 200 resistive load or higher. For management is under control of the Powerdown register resistive loads greater than 500 (f < 500MHz) the bits. LPWR bit can be set to reduce the power consumed by the IF output buffer. See Figure16 below. The IF and RF sections of the Si4136 circuitry can be individually powered down by setting the Powerdown register bits PDIB and PDRB low. The reference >500 pF frequency amplifier will also be powered up if either the IFOUT PDRB and PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register0) is equivalent to setting both bits in the >200  Powerdown register to 1. The serial interface remains available and can be written in all power-down modes. Figure16.IF Frequencies < 500MHz 2.9. Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register0). The LDETB signal can be selected by setting the AUXSEL bits to 011. This signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be re- tuned. Rev. 1.42 19

Si4136/Si4126 Table 10. Powerdown Configuration RF PWDN Pin AUTOPDB PDIB PDRB IF Circuitry Circuitry PWDN=0 x x x OFF OFF 0 0 0 OFF OFF 0 0 1 OFF ON PWDN=1 0 1 0 ON OFF 0 1 1 ON ON 1 x x ON ON Note: x=don’t care. 20 Rev. 1.42

Si4136/Si4126 3. Control Registers Table 11. Register Summary Register Name Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Main 0 0 0 0 AUXSEL IFDIV 0 0 0 XIN LPWR 0 AUTO 0 0 0 Configuration DIV2 PDB 1 Phase 0 0 0 0 0 0 0 0 0 0 0 0 K K K PI P2 P1 Detector Gain 2 Powerdown 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB 3 RF1 N N RF1 Divider 4 RF2 N 0 N RF2 Divider 5 IF N Divider 0 0 N IF 6 RF1 R 0 0 0 0 0 R RF1 Divider 7 RF2 R 0 0 0 0 0 R RF2 Divider 8 IF R Divider 0 0 0 0 0 R IF 9 Reserved . . . 15 Reserved Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Rev. 1.42 21

Si4136/Si4126 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 AUXSEL IFDIV 0 0 0 XIN LPWR 0 AUTO 0 0 0 PDB DIV2 Bit Name Function 17:14 Reserved Program to zero. 13:12 AUXSEL Auxiliary Output Pin Definition. 00 =Reserved. 01 =Force output low. 11 =Lock Detect (LDETB). 11:10 IFDIV IF Output Divider 00=IFOUT=IFVCO Frequency 01=IFOUT=IFVCO Frequency/2 10=IFOUT=IFVCO Frequency/4 11=IFOUT=IFVCO Frequency/8 9:7 Reserved Program to zero. 6 XINDIV2 XIN Divide-By-2 Mode. 0=XIN not divided by 2. 1=XIN divided by 2. 5 LPWR Output Power-Level Settings for IF Synthesizer Circuit. 0=R 500—normal power mode. LOAD 1=R 500—low power mode. LOAD 4 Reserved Program to zero. 3 AUTOPDB Auto Powerdown 0=Software powerdown is controlled by Register 2. 1=Equivalent to setting all bits in Register 2=1. 2:0 Reserved Program to zero. 22 Rev. 1.42

Si4136/Si4126 Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 K K K PI P2 P1 Bit Name Function 17:6 Reserved Program to zero. 5:4 K IF Phase Detector Gain Constant. PI N Value K PI <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 3:2 K RF2 Phase Detector Gain Constant. P2 N Value K P2 <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 1:0 K RF1 Phase Detector Gain Constant. P1 N Value K P1 <4096 = 00 4096–8191 = 01 8192–16383 = 10 >16383 = 11 Rev. 1.42 23

Si4136/Si4126 Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB Bit Name Function 17:2 Reserved Program to zero. 1 PDIB Powerdown IF Synthesizer. 0=IF synthesizer powered down. 1=IF synthesizer on. 0 PDRB Powerdown RF Synthesizer. 0=RF synthesizer powered down. 1=RF synthesizer on. Register 3. RF1 N Divider Address Field (A[3:0]) = 0011 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name N RF1 Bit Name Function 17:0 N N Divider for RF1 Synthesizer. RF1 N  992. RF1 Register 4. RF2 N Divider Address Field = A[3:0] = 0100 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 N RF2 Bit Name Function 17 Reserved Program to zero. 16:0 N N Divider for RF2 Synthesizer. RF2 N  240. RF2 24 Rev. 1.42

Si4136/Si4126 Register 5. IF N Divider Address Field (A[3:0]) = 0101 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 N IF Bit Name Function 17:16 Reserved Program to zero. 15:0 N N Divider for IF Synthesizer. IF N  56. IF Register 6. RF1 R Divider Address Field (A[3:0]) = 0110 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 R RF1 Name Function 17:13 Reserved Program to zero. 12:0 R R Divider for RF1 Synthesizer. RF1 R can be any value from 7 to 8189 if K = 00 RF1 P1 8 to 8189 if K = 01 P1 10 to 8189 if K = 10 P1 14 to 8189 if K = 11 P1 Register 7. RF2 R Divider Address Field (A[3:0]) = 0111 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 R RF2 Bit Name Function 17:13 Reserved Program to zero. 12:0 R R Divider for RF2 Synthesizer. RF2 R can be any value from 7 to 8189 if K = 00 RF2 P2 8 to 8189 if K = 01 P2 10 to 8189 if K = 10 P2 14 to 8189 if K = 11 P2 Rev. 1.42 25

Si4136/Si4126 Register 8. IF R Divider Address Field (A[3:0]) = 1000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 R IF Bit Name Function 17:13 Reserved Program to zero. 12:0 R R Divider for IF Synthesizer. IF R can be any value from 7 to 8189 if K = 00 IF P1 8 to 8189 if K = 01 P1 10 to 8189 if K = 10 P1 14 to 8189 if K = 11 P1 26 Rev. 1.42

Si4136/Si4126 4. Pin Descriptions: Si4136-GT SCLK 1 24 SEN SDATA 2 23 VDDI GND 3 22 IFOUT GND 4 21 GND NC 5 20 IFLB GND 6 19 IFLA NC 7 18 GND GND 8 17 VDDD GND 9 16 GND GND 10 15 XIN RFOUT 11 14 PWDN VDDR 12 13 AUXOUT Pin Number(s) Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 3, 4, 6, 8–10, GND Common ground 16, 18, 21 5, 7 NC No connect 11 RFOUT Radio frequency (RF) output of the selected RF VCO 12 VDDR Supply voltage for the RF analog circuitry 13 AUXOUT Auxiliary output 14 PWDN Powerdown input pin 15 XIN Reference frequency amplifier input 17 VDDD Supply voltage for digital circuitry 19, 20 IFLA, IFLB Pins for inductor connection to IF VCO 22 IFOUT Intermediate frequency (IF) output of the IF VCO 23 VDDI Supply voltage for IF analog circuitry 24 SEN Enable serial port input Rev. 1.42 27

Si4136/Si4126 5. Pin Descriptions: Si4136-GM GND SDATA SCLK SEN VDDI IFOUT GND 28 27 26 25 24 23 22 GND 1 21 GND GND 2 20 IFLB NC 3 19 IFLA GND 4 GND 18 GND NC 5 17 VDDD GND 6 16 GND GND 7 15 XIN 8 9 10 11 12 13 14 GND GND OUT DDR OUT WDN GND RF V UX P A Pin Number(s) Name Description 1, 2, 4, 6, 7–9, 14, GND Common ground 16, 18, 21, 22, 28 3, 5 NC No connect 10 RFOUT Radio frequency (RF) output of the selected RF VCO 11 VDDR Supply voltage for the RF analog circuitry 12 AUXOUT Auxiliary output 13 PWDN Powerdown input pin 15 XIN Reference frequency amplifier input 17 VDDD Supply voltage for digital circuitry 19, 20 IFLA, IFLB Pins for inductor connection to IF VCO 23 IFOUT Intermediate frequency (IF) output of the IF VCO 24 VDDI Supply voltage for IF analog circuitry 25 SEN Enable serial port input 26 SCLK Serial clock input 27 SDATA Serial data input 28 Rev. 1.42

Si4136/Si4126 6. Ordering Guide Ordering Part Description Lead-Free/ Temperature Number RoHS Compliant Si4136-F-GT 2.5GHz/2.3GHz/IFOUT/LeadFree  –40 to 85 oC Si4136-F-GM 2.5GHz/2.3GHz/IFOUT/LeadFree  –40 to 85 oC Si4126-F-GM 2.3GHz/IFOUT/LeadFree  –40 to 85 oC 7. Si4136 Derivative Devices The Si4136 performs both IF and dual-band RF frequency synthesis. The Si4126 is a derivative of this device. The Si4126 features two synthesizers, RF2 and IF; it does not include RF1. The pinouts for the Si4126 and the Si4136 are the same. Unused registers related to RF1 should be programmed to zero. Rev. 1.42 29

Si4136/Si4126 8. Package Outline: Si4136-GT Figure18 illustrates the package details for the Si4136-GT. Table12 lists the values for the dimensions shown in the illustration. E/2 E1 E  L ddd C B A 2x e ccc A D aaa C A Seating Plane b A1 C 24x C bbb M C B A Figure18.24-Pin Thin Shrink Small Outline Package (TSSOP) Table 12. Package Diagram Dimensions Millimeters Symbol Min Nom Max A — — 1.20 A1 0.05 — 0.15 b 0.19 — 0.30 c 0.09 — 0.20 D 7.70 7.80 7.90 e 0.65 BSC E 6.40 BSC E1 4.30 4.40 4.50 L 0.45 0.60 0.75  0° — 8° aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 30 Rev. 1.42

Si4136/Si4126 9. Package Outline: Si4136-GM Figure19 illustrates the package details for the Si4136-GM. Table13 lists the values for the dimensions shown in the illustration. 2x A D 0.10 C A D/2 0.05C A b 0.10 M C A B A1 Pin 1 ID 2x D2 0.20 R N 0.10C B N 1 1 E/2 2 2 3 3 E E2 L B  TOP VIEW C Seating e Plane SIDE VIEW BOTTOM VIEW Figure19.28-Pin Quad Flat No-Lead (QFN) Table 13. Package Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom Max A — 0.85 0.90 A1 0.00 0.01 0.05 b 0.18 0.23 0.30 D, E 5.00 BSC D2, E2 2.55 2.70 2.85 N 28 e 0.50 BSC L 0.50 0.60 0.75  12° Rev. 1.42 31

Si4136/Si4126 DOCUMENT CHANGE LIST Revision 1.3 to Revision 1.4  Si4136-BT change to Si4136-BT/GT  Si4136-BM change to Si4136-BM/GM Revision 1.4 to Revision 1.41  Updated contact information. Revision 1.41 to Revision 1.42  Si4136-F-BT removed from document.  Si4136-F-BM removed from document.  Si4126-F-BM removed from document. 32 Rev. 1.42

Si4136/Si4126 NOTES: Rev. 1.42 33

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