Si3437DV Vishay Siliconix P-Channel 150-V (D-S) MOSFET FEATURES PRODUCT SUMMARY (cid:129) Halogen-free According to IEC 61249-2-21 VDS (V) RDS(on) (Ω) ID (A)a Qg (Typ.) Definition 0.75 at V = - 10 V - 1.4 (cid:129) TrenchFET® Power MOSFET GS - 150 8 nC (cid:129) 100 % R and UIS Tested 0.79 at V = - 6 V - 1.3 g GS (cid:129) Compliant to RoHS Directive 2002/95/EC APPLICATIONS (cid:129) Active Clamp Circuits in DC/DC Power Supplies TSOP-6 Top View D 1 6 D S 3 mm D 2 5 D Marking Code G AH XXX G 3 4 S Lot Traceab ility and Date Code Part # Code 2.8 5 mm D Ordering Information: Si3437DV-T1-E3 (Lead (Pb)-free) Si3437DV-T1-GE3 (Lead (Pb)-free and Halogen-free) P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage VDS - 150 V Gate-Source Voltage VGS ± 20 T = 25 °C - 1.4 C T = 70 °C - 1.1 Continuous Drain Current (T = 150 °C) C I J TA = 25 °C D - 1.1b,c TA = 70 °C - 0.88b,c A Pulsed Drain Current IDM - 5 T = 25 °C - 2.6 Continuous Source-Drain Diode Current TC = 25 °C IS 1.6b,c A Avalanche Current IAS 5 L = 0.1 mH Single-Pulse Avalanche Energy EAS 1.25 mJ T = 25 °C 3.2 C T = 70 °C 2.1 Maximum Power Dissipation TCA = 25 °C PD 2b,c W TA = 70 °C 1.25b,c Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambientb, d t ≤ 5 s RthJA 51 62.5 °C/W Maximum Junction-to-Foot Steady State RthJF 32 39 Notes: a. T = 25 °C. C b. Surface Mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under Steady State conditions is 110 °C/W. Document Number: 73899 www.vishay.com S09-0766-Rev. B, 04-May-09 1

Si3437DV Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 150 V VVGDSS (tThe) mTepmerpaeturaretu Creo Cefofiecfifeicnitent ΔVΔVGSD(Sth/T)/JTJ ID = - 250 µA - 51.650 mV/°C Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 2 - 4 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS =V -D 1S5 =0 -V 1, 5V0G SV ,= V 0G VS, =T 0J =V 5 5 °C -- 1 10 µA On-State Drain Currenta ID(on) VDS ≥ - 10 V, VGS = - 10 V - 3 A Drain-Source On-State Resistancea RDS(on) VGVSG S= =- 1- 06 VV,, IIDD == -- 11. 4A A 00..6614 00..7759 Ω Forward Transconductancea gfs VDS = - 10 V, ID = - 1.4 A 4.5 S Dynamicb Input Capacitance Ciss 510 Output Capacitance Coss VDS = - 50 V, VGS = 0 V, f = 1 MHz 30 pF Reverse Transfer Capacitance Crss 21 Total Gate Charge Qg VDS = - 75 V, VGS = - 10 V, ID = - 1 A 12.2 19 8 12 nC Gate-Source Charge Qgs VDS = - 75 V, VGS = - 6 V, ID = - 1 A 2.1 Gate-Drain Charge Qgd 3.9 Gate Resistance Rg f = 1 MHz 8.5 13 Ω Turn-On Delay Time td(on) 9 15 Rise Time tr VDD = - 75 V, RL = 75 Ω 11 18 Turn-Off DelayTime td(off) ID ≅ - 1 A, VGEN = - 10 V, Rg = 1 Ω 28 42 Fall Time tf 12 18 ns Turn-On Delay Time td(on) 14 21 Rise Time tr VDD = - 75 V, RL = 75 Ω 29 44 Turn-Off DelayTime td(off) ID ≅ - 1 A, VGEN = - 6 V, Rg = 1 Ω 23 35 Fall Time tf 14 21 Drain-Source Body Diode Characteristics Continous Source-Drain Diode Current IS TC = 25 °C - 1.4 A Pulse Diode Forward Current ISM - 5 Body Diode Voltage VSD IS = - 1 A, VGS = 0 V - 0.8 - 1.2 V Body Diode Reverse Recovery Time trr 60 90 ns Body Diode Reverse Recovery Charge Qrr I = - 1.2 A, dI/dt = 100 A/µs, T = 25 °C 120 180 nC Reverse Recovery Fall Time ta F J 35 ns Reverse Recovery Rise Time tb 25 Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 73899 2 S09-0766-Rev. B, 04-May-09

Si3437DV Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 8 1.5 VGS = 10 V thru 6 V 1.2 6 )A( tne )A( tn 0.9 rruC niarD -D 4 5 V erruC niarD - 0.6 I 2 ID 25 °C 0.3 TC = 125 °C - 55 °C 0 0.0 0 2 4 6 8 10 0 2 4 6 8 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 1.4 750 Ω) 1.2 600 Ciss ( e )F c p natseisR 1.0 c( ecnati 450 -n ap -O n) 0.8 VGS = 6 V aC - 300 DS(o VGS = 10 V C R 0.6 150 Coss Crss 0.4 0 0.0 1.6 3.2 4.8 6.4 8.0 0 4 8 12 16 20 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 10 2.4 ID = 1 A ID = 1.2 A )V 8 2.0 e( egatloV ecruoS-ot- 46 VDS = V50D SV = 75 V VDS = 100 V ecnasisen -tR-O)n)iodezlamrN( 11..26 VGS = 10 VVGS = 6 V a tG - RoSD( SG 2 0.8 V 0 0.4 0 2.6 5.2 7.8 10.4 13 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ- Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 73899 www.vishay.com S09-0766-Rev. B, 04-May-09 3

Si3437DV Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 5 ID = 1.2 A Ω) 4 ( )A( tnerru 1 TJ = 150 °C TJ = 25 °C o-Source 3 -C ecruoS IS 0.1 Drain-t-DS(on) 2 125 °C R 1 25 °C 0 0.01 0 2 4 6 8 10 0.0 0.3 0.6 0.9 1.2 1.5 VSD- Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Temperature 0.8 60 0.6 48 ) V ( e c n a i r a - V h) 00..24 ID = 250 µA ID = 5 mA w)W( reoP 2346 GS(t 0.0 V 12 - 0.2 - 0.4 0 - 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10 T J - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 10 Limited by RDS(on)* 1 A) (tn 1 ms e rur 10 ms C 0.1 n ia rD 100 ms - D 1 s I 10 s 0.01 DC TA = 25 °C Single Pulse 0.001 0.1 1 10 100 1000 VDS - Drain-to-Source Voltage (V) * VGS minimum VG S at which RDS(on)isspecified Safe Operating Area, Junction-to-Ambient www.vishay.com Document Number: 73899 4 S09-0766-Rev. B, 04-May-09

Si3437DV Vishay Siliconix MOSFET TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 1.6 1.3 )W 1.0 ( re w o P 0.6 0.3 0.0 0 25 50 75 100 125 150 TC - Case Temperature (°C) Current Derating* 4.0 1.5 3.2 1.2 ) ( r w P W e o 2.4 er (W)wo 0.9 1.6 P 0.6 0.8 0.3 0.0 0.0 0 25 50 75 100 125 150 0 25 50 75 100 125 150 TC - Case Temperature (°C) TA - Ambient Temperature (°C) Power, Junction-to-Foot Power Derating, Junction-to-Ambient * The power dissipation P is based on T = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper D J(max) dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 73899 www.vishay.com S09-0766-Rev. B, 04-May-09 5

Si3437DV Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1 Duty Cycle = 0.5 t n e i s n a r T e v i t c e f f E d e z i l a m e c n a d e p m I l a m r e h T 0.1 00.00.2.51 NPoD tMes : t1 r o N 0.02 1. Duty Cycle,t 2 D = t1 t2 2. Per Unit Base = Rt hJA = 75 °C 3. TJ M – T = PD MZ thJA (t) Single Pulse 4. Surface Mounted 0.01 10- 4 10- 3 10- 2 10- 1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Duty Cycle = 0.5 t n e i s n a r T e v i t c e f f E d e z i l a m e c n a d e p m I l a m r e h T 0.1 000.0..020.215 r o N Single Pulse 0.01 10 -4 10- 3 10- 2 10- 1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73899. www.vishay.com Document Number: 73899 6 S09-0766-Rev. B, 04-May-09

Package Information Vishay Siliconix TSOP: 5/6−LEAD JEDEC Part N umber: MO-193C e1 e1 5 4 6 5 4 E1 E E1 E 1 1 2 3 2 3 -B- -B- e b 0.15 M C B A e b 0.15 M C B A 5-LEAD TSOP 6-LEAD TSOP -A- 4x 1 D 0.17 Ref R c A2 A R L 2 Gauge Plane Seating Plane Seating Plane L 0.08 C -C- A1 4x 1 (L1 ) MILLIMETERS INCHES Dim Min Nom Max Min Nom Max A 0.91 - 1.10 0.036 - 0.043 A1 0.01 - 0.10 0.0004 - 0.004 A2 0.90 - 1.00 0.035 0.038 0.039 b 0.30 0.32 0.45 0.012 0.013 0.018 c 0.10 0.15 0.20 0.004 0.006 0.008 D 2.95 3.05 3.10 0.116 0.120 0.122 E 2.70 2.85 2.98 0.106 0.112 0.117 E1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.95 BSC 0.0374 BSC e 1 1.80 1.90 2.00 0.071 0.075 0.079 L 0.32 - 0.50 0.012 - 0.020 L 1 0.60 Ref 0.024 Ref L 2 0.25 BSC 0.010 BSC R 0.10 - - 0.004 - - 0 4 8 0 4 8 1 7 Nom 7 Nom ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540 Document Number: 71200 www.vishay.com 18-Dec-06 1

AN823 Vishay Siliconix (cid:1) Mounting LITTLE FOOT TSOP-6 Power MOSFETs Surface mounted power MOSFET packaging has been based on Since surface mounted packages are small, and reflow soldering integrated circuit and small signal packages. Those packages is the most common form of soldering for surface mount have been modified to provide the improvements in heat transfer components, “thermal” connections from the planar copper to the required by power MOSFETs. Leadframe materials and design, pads have not been used. Even if additional planar copper area is molding compounds, and die attach materials have been used, there should be no problems in the soldering process. The changed. What has remained the same is the footprint of the actual solder connections are defined by the solder mask packages. openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. The basis of the pad design for surface mounted power MOSFET A final item to keep in mind is the width of the power traces. The is the basic footprint for the package. For the TSOP-6 package absolute minimum power trace width must be determined by the outline drawing see http://www.vishay.com/doc?71200 and see amount of current it has to carry. For thermal reasons, this http://www.vishay.com/doc?72610 for the minimum pad footprint. minimum width should be at least 0.020 inches. The use of wide In converting the footprint to the pad set for a power MOSFET, you traces connected to the drain plane provides a low impedance must remember that not only do you want to make electrical path for heat to move away from the device. connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. REFLOW SOLDERING In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated Vishay Siliconix surface-mount packages meet solder reflow circuit, typical connections would be made with traces that are reliability requirements. Devices are subjected to solder reflow as a 0.020 inches wide. Since the drain pins serve the additional test preconditioning and are then reliability-tested using function of providing the thermal connection to the package, this temperature cycle, bias humidity, HAST, or pressure pot. The level of connection is inadequate. The total cross section of the solder reflow temperature profile used, and the temperatures and copper may be adequate to carry the current required for the time duration, are shown in Figures 2 and 3. application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose. 0.167 4.25 Ramp-Up Rate +6(cid:2)C/Second Maximum 0.074 Temperature @ 155 (cid:1) 15(cid:2)C 120 Seconds Maximum 1.875 0.014 0.122 0.35 3.1 Temperature Above 180(cid:2)C 70 − 180 Seconds 0.026 Maximum Temperature 240 +5/−0(cid:2)C 0.65 Time at Maximum Temperature 20 − 40 Seconds Ramp-Down Rate +6(cid:2)C/Second Maximum 0.049 0.049 0.010 1.25 1.25 0.25 FIGURE 1. Recommended Copper Spreading Footprint FIGURE 2. Solder Reflow Temperature Profile Document Number: 71743 www.vishay.com 27-Feb-04 1

AN823 Vishay Siliconix 10 s (max) 255 − 260(cid:2)C 1(cid:2)4(cid:2)C/s (max) 3-6(cid:2)C/s (max) 217(cid:2)C 140 − 170(cid:2)C 60 s (max) 3(cid:2)C/s (max) 60-120 s (min) Reflow Zone Pre-Heating Zone Maximum peak temperature at 240(cid:2)C is allowed. FIGURE 3. Solder Reflow Temperature and Time Durations THERMAL PERFORMANCE A basic measure of a device’s thermal performance is the On-Resistance vs. Junction Temperature junction-to-case thermal resistance, R(cid:1) , or the 1.6 jc junction-to-foot thermal resistance, R(cid:1)jf. This parameter is VGS = 4.5 V measured for the device mounted to an infinite heat sink and ID = 6.1 A is therefore a characterization of the device only, in other 1.4 e words, independent of the properties of the object to which the c n a doef vthicee T isS OmPo-u6n.ted. Table 1 shows the thermal performance esiistzed) 1.2 n-Rmali TABLE 1. − On)(Nor 1.0 o S( D Equivalent Steady State Performance—TSOP-6 r 0.8 Thermal Resistance R(cid:1)jf 30(cid:2)C/W 0.6 −50 −25 0 25 50 75 100 125 150 SYSTEM AND ELECTRICAL IMPACT OF TJ − Junction Temperature ((cid:2)C) TSOP-6 FIGURE 4. Si3434DV In any design, one must take into account the change in MOSFET r with temperature (Figure 4). DS(on) www.vishay.com Document Number: 71743 2 27-Feb-04

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR TSOP-6 0.099 (2.510) 9 3) 4 6) 1 2 6 2 1 0 0 6 0. 3. 0. 1. ( ( 8 9) 2 9 0 6 0. 0. ( 0.039 0.020 0.019 (1.001) (0.508) (0.493) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index E T O N N O I T A C I L P P A www.vishay.com Document Number: 72610 26 Revision: 21-Jan-08

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