Si3056 Si3018/19/10 GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT Features Complete DAA includes the following:  Programmable line interface  Pulse dialing support  AC termination  Overload detection  DC termination  3.3V power supply  Ring detect threshold  Direct interface to DSPs  Ringer impedance  Serial interface control for up to eight  80dB dynamic range TX/RX paths devices  Integrated codec and 2- to 4-wire  >5000V isolation hybrid  Proprietary isolation technology  Integrated ring detector  Parallel handset detection Ordering Information  Type I and II caller ID support  +3.2dBm TX/RX level mode See page87.  Line voltage monitor  Programmable digital hybrid for near-  Loop current monitor end echo reduction  Polarity reversal detection  Low-profile SOIC packages  Programmable digital gain  Lead-free/RoHS-compliant packages Pin Assignments  Clock generation available Si3056 Applications MCLK 1 16 OFHK FSYNC 2 15 RGDT/FSD/M1  V.92 modems  Set-top boxes  Internet appliances SCLK 3 14 M0  Voice mail systems  Fax machines  Personal digital V 4 13 V  Multi-function printers assistants D A SDO 5 12 GND SDI 6 11 AOUT/INT Description FC/RGDT 7 10 C1A RESET 8 9 C2A The Si3056 is an integrated direct access arrangement (DAA) with a programmable line interface to meet global telephone line requirements. Available in two 16-pin small outline packages, it eliminates the need for an analog front end Si3018/19/10 (AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3056 dramatically reduces the number of discrete components and cost QE 1 16 DCT2 required to achieve compliance with global regulatory requirements. The Si3056 DCT 2 15 IGND interfaces directly to standard modem DSPs. RX 3 14 DCT3 Functional Block Diagram IB 4 13 QB C1B 5 12 QE2 C2B 6 11 SC Si3056 Si3018/19/10 VREG 7 10 VREG2 RNG1 8 9 RNG2 MCLK RX SCLK FSYNC Digital IB SDI Interface Hybrid and SC US Patent # 5,870,046 SDO dc DCT US Patent # 6,061,009 FC/RGDT Termination VREG Isolation Isolation VREG2 Other Patents Pending Interface Interface DCT2 DCT3 RGDT/FSD/M1 OFHK Control RNG1 RNG2 M0 Interface Ring Detect RESET Off-Hook QQEB QE2 AOUT/INT Rev. 1.06 8/16 Copyright © 2016 by Silicon Laboratories Si3056

Si3056 Si3018/19/10 2 Rev. 1.06

Si3056 Si3018/19/10 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.1. Upgrading from the Si3034/35/44 to Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.2. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.3. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.4. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.5. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.6. Transmit/Receive Full Scale Level (Si3019 Line-Side Only) . . . . . . . . . . . . . . . . . . .25 5.7. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.8. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.9. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5.10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.11. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.12. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.13. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.14. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.15. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.16. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.17. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.18. Billing Tone Protection and Receive Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.19. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.20. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.21. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.22. Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5.23. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5.24. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.25. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.26. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.27. Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.28. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.29. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.30. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.31. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.32. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 7. Pin Descriptions: Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 8. Pin Descriptions: Si3018/19/10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Rev. 1.06 3

Si3056 Si3018/19/10 10. Evaluation Board Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Silicon Laboratories Si3056 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4 Rev. 1.06

Si3056 Si3018/19/10 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter1 Symbol Test Condition Min2 Typ Max2 Unit Ambient Temperature T F and K-Grade 0 25 70 °C A Si3056 Supply Voltage, Digital3 V 3.0 3.3 3.6 V D Notes: 1. The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the Si3056 and any Si3018 or Si3019 are used. See Figure17 on page 18 for typical application schematic. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 3. 3.3V applies to both the digital and serial interface and the digital signals RGDT/FSD, OFHK, RESET, M0, and M. Rev. 1.06 5

Si3056 Si3018/19/10 Table 2. Loop Characteristics (V =3.0 to 3.6 V, T =0 to 70°C, see Figure1) D A Parameter Symbol Test Condition Min Typ Max Unit DC Termination Voltage V I =20mA, MINI=11, — — 6.0 V TR L ILIM=0, DCV=00, DCR=0 DC Termination Voltage V I =120mA, MINI=11, 9 — — V TR L ILIM=0, DCV=00, DCR=0 DC Termination Voltage V I =20mA, MINI=00, — — 7.5 V TR L ILIM=0, DCV=11, DCR=0 DC Termination Voltage V I =120mA, MINI=00, 9 — — V TR L ILIM=0, DCV=11, DCR=0 DC Termination Voltage V I =20mA, MINI=00, — — 7.5 V TR L ILIM=1, DCV=11, DCR=0 DC Termination Voltage V I =60mA, MINI=00, 40 — — V TR L ILIM=1, DCV=11, DCR=0 DC Termination Voltage V I =50mA, MINI=00, — — 40 V TR L ILIM=1, DCV=11, DCR=0 On Hook Leakage Current I V =–48V — — 5 µA LK TR Operating Loop Current I MINI=00, ILIM=0 10 — 120 mA LP Operating Loop Current I MINI=00, ILIM=1 10 — 60 mA LP DC Ring Current DC current flowing through ring — 1.5 3 µA detection circuitry Ring Detect Voltage* V RT=0 13.5 15 16.5 V RD rms Ring Detect Voltage* V RT=1 19.35 21.5 23.65 V RD rms Ring Frequency F 13 — 68 Hz R Ringer Equivalence Number REN — — 0.2 *Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above the maximum. TIP + 600  I Si3018 V L TR 10 F – RING Figure 1. Test Circuit for Loop Characteristics 6 Rev. 1.06

Si3056 Si3018/19/10 Table 3. DC Characteristics, V = 3.3 V D (V =3.0 to 3.6V, T =0 to 70°C) D A Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage V 2.4 — — V IH Low Level Input Voltage V — — 0.8 V IL High Level Output Voltage V I =–2 mA 2.4 — — V OH O Low Level Output Voltage V I =2 mA — — 0.35 V OL O Input Leakage Current I –10 — 10 µA L Power Supply Current, Digital1 I V pin — 15 — mA D D Total Supply Current, Sleep Mode1 I PDN=1, PDL=0 — 9 — mA D Total Supply Current, Deep Sleep1,2 I PDN=1, PDL=1 — 1 — mA D Notes: 1. All inputs at 0.4 or V – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded D (Static I =0mA). OUT 2. RGDT is not functional in this state. Rev. 1.06 7

Si3056 Si3018/19/10 Table 4. AC Characteristics (V =3.0 to 3.6V, T =0 to 70°C; see Figure17 on page 18) D A Parameter Symbol Test Condition Min Typ Max Unit Sample Rate1 Fs Fs=F /5120 7.2 — 16 kHz PLL2 PLL Output Clock Frequency1 F F =(F xM)/N — 98.304 — MHz PLL1 PLL1 MCLK Transmit Frequency Response Low –3dBFS Corner — 0 — Hz Receive Frequency Response Low –3dBFS Corner, — 5 — Hz FILT=0 Receive Frequency Response Low –3dBFS Corner, — 200 — Hz FILT=111 Transmit Full Scale Level2,3 V FULL=0 (0dBm) — 1.1 — V FS PEAK FULL=111(3.2dBm) — 1.58 — V PEAK FULL2=1 (6.0dBm) — 2.16 — V PEAK Receive Full Scale Level2,4 V FULL=0 (0dBm) 1.1 V FS PEAK FULL=111(3.2dBm) — 1.58 — V PEAK FULL2=1 (6.0dBm) — 2.16 — V PEAK Dynamic Range5,6,7 DR ILIM=0, DCV=11, DCR=0, — 80 — dB I =100mA, MINI=00 L Dynamic Range5,6,7 DR ILIM=0, DCV=00, DCR=0, — 80 — dB I =20mA, MINI=11 L Dynamic Range5,6,7 DR ILIM=1, DCV=11, DCR=0, — 80 — dB I =50mA, MINI=00 L Transmit Total Harmonic Distor- THD ILIM=0, DCV=11, DCR=0, — –72 — dB tion8,9 I =100mA, MINI=00 L Transmit Total Harmonic Distor- THD ILIM=0, DCV=00, DCR=0, — –78 — dB tion8,9 I =20mA, MINI=11 L Notes: 1. See Figure26 on page 37. 2. Measured at TIP and RING with 600 termination at 1kHz, as shown in Figure1. 3. With FULL=1, the transmit and receive full scale level of +3.2dBm can be achieved with a 600 ac termination, while the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1dBV into all reference impedances in “FULL” mode. With FULL2=1, the transmit and receive full scale level of +6.0dBm can be achieved with a 600 ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5dBV into all reference impedances. 4. Receive full scale level produces –0.9dBFS at SDO. 5. DR=20xlog (RMS V /RMS V ).+ 20xlog (RMS V /RMS noise). The RMS noise measurement excludes FS IN IN harmonics. V is the 0dBm full-scale level. FS 6. Measurement is 300 to 3400Hz. Applies to both transmit and receive paths. V =1kHz, –3dBFS, Fs=10300Hz. IN 7. When using the Si3010 line-side, the typical DR values will be approximately 10dB lower. 8. THD=20xlog (RMS distortion/RMS signal). V =1kHz, –3dBFS, Fs=10300Hz. IN 9. When using the Si3010 line-side, the typical THD values will be approximately 10dB higher. 10. DR =20xlog (RMS V /RMS V ) + 20xlog(RMS V /RMS noise). V is the 6V full-scale level for the typical CID CID IN IN CID application circuit in Figure17. With the enhanced CID circuit, the V full-scale level is 1.5V peak, and DR CID CID increases to 62dB. 11. Available on the Si3019 line-side device only. 8 Rev. 1.06

Si3056 Si3018/19/10 Table 4. AC Characteristics (Continued) (V =3.0 to 3.6V, T =0 to 70°C; see Figure17 on page 18) D A Parameter Symbol Test Condition Min Typ Max Unit Receive Total Harmonic Distor- THD ILIM=0, DCV=00, DCR=0, — –78 — dB tion8,9 I =20mA, MINI=11 L Receive Total Harmonic Distor- THD ILIM=1, DCV=11, DCR=0, — –78 — dB tion8,9 I =50mA, MINI=00 L Dynamic Range (caller ID DR VIN=1 kHz, –13dBFS — 50 — dB CID mode)10,7 Caller ID Full Scale Level10 V — 6 — V CID PEAK AOUT Low Level Current — — 10 mA AOUT High Level Current — — 10 mA Notes: 1. See Figure26 on page 37. 2. Measured at TIP and RING with 600 termination at 1kHz, as shown in Figure1. 3. With FULL=1, the transmit and receive full scale level of +3.2dBm can be achieved with a 600 ac termination, while the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1dBV into all reference impedances in “FULL” mode. With FULL2=1, the transmit and receive full scale level of +6.0dBm can be achieved with a 600 ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5dBV into all reference impedances. 4. Receive full scale level produces –0.9dBFS at SDO. 5. DR=20xlog (RMS V /RMS V ).+ 20xlog (RMS V /RMS noise). The RMS noise measurement excludes FS IN IN harmonics. V is the 0dBm full-scale level. FS 6. Measurement is 300 to 3400Hz. Applies to both transmit and receive paths. V =1kHz, –3dBFS, Fs=10300Hz. IN 7. When using the Si3010 line-side, the typical DR values will be approximately 10dB lower. 8. THD=20xlog (RMS distortion/RMS signal). V =1kHz, –3dBFS, Fs=10300Hz. IN 9. When using the Si3010 line-side, the typical THD values will be approximately 10dB higher. 10. DR =20xlog (RMS V /RMS V ) + 20xlog(RMS V /RMS noise). V is the 6V full-scale level for the typical CID CID IN IN CID application circuit in Figure17. With the enhanced CID circuit, the V full-scale level is 1.5V peak, and DR CID CID increases to 62dB. 11. Available on the Si3019 line-side device only. Rev. 1.06 9

Si3056 Si3018/19/10 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage V –0.5 to 3.6 V D Input Current, Si3056 Digital Input Pins I ±10 mA IN Digital Input Voltage V –0.3 to (V + 0.3) V IND D Operating Temperature Range T –40 to 100 °C A Storage Temperature Range T –65 to 150 °C STG Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict functional operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability. Table 6. Switching Characteristics—General Inputs (V =3.0 to 3.6V, T =0 to 70°C, C =20pF) D A L Parameter1 Symbol Min Typ Max Unit Cycle Time, MCLK t 16.67 — 1000 ns mc MCLK Duty Cycle t 40 50 60 % dty MCLK Jitter Tolerance t — — ±2 ns jitter Rise Time, MCLK t — — 5 ns r Fall Time, MCLK t — — 5 ns f MCLK Before RESET  t 10 — — cycles mr RESET Pulse Width2 t 250 — — ns rl M0, M Before RESET3 t 20 — — ns mxr Notes: 1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are V =V – 0.4V, V =0.4V. Rise and fall times are referenced to the 20% and 80% levels of the waveform. IH D IL 2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times. 3. M0 and M are typically connected to V or GND and should not be changed during normal operation. D t mc t t r f V IH MCLK V IL t RESET mr t rl M0, M1 t mxr Figure 2. General Inputs Timing Diagram 10 Rev. 1.06

Si3056 Si3018/19/10 Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0) (V =3.0 to 3.6V, T =0 to 70°C, C =20pF) D A L Parameter Symbol Min Typ Max Unit Cycle time, SCLK t 244 1/256 Fs — ns c SCLK Duty Cycle t — 50 — % dty Delay Time, SCLKto FSYNC t — — 20 ns d1 Delay Time, SCLK to SDO Valid t — — 20 ns d2 Delay Time, SCLKto FSYNC t — — 20 ns d3 Setup Time, SDI Before SCLK  t 25 — — ns su Hold Time, SDI After SCLK  t 20 — — ns h Setup Time, FC Before SCLK t 40 — — ns sfc Hold time, FC After SCLK t 40 — — ns hfc Note: All timing is referenced to the 50% level of the waveform. Input test levels are V =V – 0.4V, V =0.4V. IH D IL t c V SCLK OH V OL t t d1 d3 FSYNC (mode 0) t d3 FSYNC (mode 1) t 16-Bit d2 D15 D14 D1 DD00 SDO t t su h 16-Bit D15 D14 D1 D0 SDI t t sfc hfc FC Figure 3. Serial Interface Timing Diagram (DCE = 0) Rev. 1.06 11

Si3056 Si3018/19/10 Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0) (V =Charge Pump, V =3.0 to 3.6V, T =0 to 70°C, C =20 pF) A D A L Parameter1,2 Symbol Min Typ Max Unit Cycle Time, SCLK t 244 1/256 Fs — ns c SCLK Duty Cycle t — 50 — % dty Delay Time, SCLKto FSYNC t — — 20 ns d1 Delay Time, SCLKto FSYNC t — — 20 ns d2 Delay Time, SCLK to SDO valid t — — 20 ns d3 Delay Time, SCLK to SDO Hi-Z t — — 20 ns d4 Delay Time, SCLK to FSD t — — 20 ns d5 Delay Time, SCLK to FSD t — — 20 ns d6 Setup Time, SDO Before SCLK t 25 — — ns su Hold Time, SDO After SCLK t 20 — — ns h Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are V =V – 0.4V, V =0.4V. IH D IL 2. See "5.27.Multiple Device Support" on page 38 for functional details. 32 SCLKs 16 SCLKs 16 SCLKs t c SCLK t t t d1 d2 d2 FSYNC (mode 1) td2 td6 td2 FSYNC (mode 0) t t t t d3 su h d4 SDO D15 D14 D13 D0 (master) t d3 SDO D15 (slave 1) t d5 FSYNC (Mode 0) t d5 FSYNC (Mode 1) t t su h SDI D15 D14 D13 D0 Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0) 12 Rev. 1.06

Si3056 Si3018/19/10 Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1) (V =3.0 to 3.6V, T =0 to 70°C, C =20pF) D A L Parameter1, 2 Symbol Min Typ Max Unit Cycle Time, SCLK t 244 1/256 Fs — ns c SCLK Duty Cycle t — 50 — % dty Delay Time, SCLKto FSYNC t — — 20 ns d1 Delay Time, SCLKto FSYNC t — — 20 ns d2 Delay Time, SCLK to SDO Valid t — — 20 ns d3 Delay Time, SCLK to SDO Hi-Z t — — 20 ns d4 Delay Time, SCLK to FSD t — — 20 ns d5 Setup Time, SDO Before SCLK t 25 — — ns su Hold Time, SDO After SCLK t 20 — — ns h Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are V =V – 0.4V, V =0.4V. IH D IL 2. See "5.27.Multiple Device Support" on page 38 for functional details. t c SCLK t t d1 d2 FSYNC (mode 1) t t t t d3 su h d4 SDO D15 D14 D13 D0 (master) t d3 SDO D15 (slave 1) t d5 FSD t t su h SDI D15 D14 D1 D0 Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1) Rev. 1.06 13

Si3056 Si3018/19/10 Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = 1) (V =Charge Pump, V =3.0 to 3.6V, T =0 to 70 °C, C =20pF) A D A L Parameter Symbol Min Typ Max Unit Cycle Time, MCLK t 244 1/256 Fs — ns c Setup Time, FSYNC before MCLK* t — — 20 ns su1 Delay Time, FSYNC after MCLK* t — — 20 ns d1 Setup Time, SDI before MCLK t — — 20 ns su3 Hold Time, SDI After MCLK t — — 20 ns h2 Delay Time, MCLK to SDO t — — 20 ns d3 Delay Time, MCLK to FSYNC t — — 20 ns d1 Delay Time, MCLK to FSYNC t — — 20 ns d2 *Note: T and T are listed for applications where the controller drives the MCLK and FSYNC instead of a master DAA. su1 h1 t C MCLK t SU1 t t d1 d1 t h1 FSYNC (mode 1) t d2 FSYNC (mode 0) t t su3 h2 SDI D15 D14 D0 t d3 SDO D15 D14 D0 Figure 6. Serial Interface Timing Diagram (Slave Mode, DCE = 1, FSD = 1) 14 Rev. 1.06

Si3056 Si3018/19/10 Table 11. Digital FIR Filter Characteristics—Transmit and Receive (V =3.0 to 3.6V, Sample Rate=8kHz, T =0 to 70°C) D A Parameter Symbol Min Typ Max Unit Passband (0.1 dB) F 0 — 3.3 kHz (0.1dB) Passband (3 dB) F 0 — 3.6 kHz (3dB) Passband Ripple Peak-to-Peak –0.1 — 0.1 dB Stopband — 4.4 — kHz Stopband Attenuation –74 — — dB Group Delay t — 12/Fs — s gd Note: Typical FIR filter characteristics for Fs=8000Hz are shown in Figures 7, 8, 9, and 10. Table 12. Digital IIR Filter Characteristics—Transmit and Receive (V =3.0 to 3.6V, Sample Rate=8 kHz, T =0 to 70°C) D A Parameter Symbol Min Typ Max Unit Passband (3 dB) F 0 — 3.6 kHz (3 dB) Passband Ripple Peak-to-Peak –0.2 — 0.2 dB Stopband — 4.4 — kHz Stopband Attenuation –40 — — dB Group Delay t — 1.6/Fs — s gd Note: Typical IIR filter characteristics for Fs=8000Hz are shown in Figures 11, 12, 13, and 14. Figures 15 and 16 show group delay versus input frequency. Rev. 1.06 15

Si3056 Si3018/19/10 Figure 7. FIR Receive Filter Response Figure 9. FIR Transmit Filter Response Figure 8. FIR Receive Filter Passband Ripple Figure 10. FIR Transmit Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate of Fs=8kHz. 16 Rev. 1.06

Si3056 Si3018/19/10 Figure 11. IIR Receive Filter Response Figure 14.IIR Transmit Filter Passband Ripple Figure 12. IIR Receive Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 13. IIR Transmit Filter Response Figure 16. IIR Transmit Group Delay Rev. 1.06 17

Si3056 Si3018/19/10 2. Typical Application Schematic RING TIP RV1RV1 R16R16 R15R15 C9C9 C8C8 C10C10 R6R6 Q3Q3 Q2Q2 FB2FB2 FB1FB1 0 1 Q1Q1 / Z1Z1 9 1 Section R5R5 C7C7 C3C3 D2D2 D1D1 018/) A 3s A ie Plane In D Q4Q4 R4R4 and Sdelin und 6 ui No Gro R11R11 Q5Q5 R32R32 C31C31 C30C30 R30R30 Si305yout g ea R10R10 R3R3 R2R2 161514131211109 C6C6 R8R8 R33R33 Optional CID Enhancement R31R31 R7R7 rcuit for thmmended l i U2U2 QEDCT2DCTIGNDRXDCT3IBQBC1BQE2C2BSCVREGVREG2RNG1RNG2 Si3018/19/10Si3018/19 tion Cr reco 12345678 ao cf R1R1 li7 p6 ++ C4C4 C5C5 R9R9 al Apo AN C1C1 C2C2 icr t pe yf R12R12 R13R13 TRe . 7( 1 e 16OFHK15RGDT/FSD/M114M013VA12GND11AOUT/INT10C1A9C2A Si3056Si3056 C51C51 Decoupling cap forU1 VA Figur R52R52 MCLKFSYNCSCLKVDSDOSDIFC/RGDTRESET U1U1 R51R51 12345678 VD R53R53 VD Decoupling cap forU1 VD C50C50 M0RGDTbOFHKb MCLKFSYNCbSCLK SDOSDIFCRESETb AOUT 18 Rev. 1.06

Si3056 Si3018/19/10 3. Bill of Materials Component(s) Value Supplier(s) C1, C2 33pF, Y2, X7R, 20% Panasonic, Murata, Vishay C31 10nF, 250V, X7R, ±10% Venkel, SMEC C4 1.0µF, 50V, Elec/Tant, ±20% Panasonic C5, C6, C50, C51 0.1µF, 16V, X7R, ±20% Venkel, SMEC C7 2.7nF, 50V, X7R, 20% Venkel, SMEC C8, C9 680pF, Y2, X7R, ±10% Panasonic, Murata, Vishay C10 0.01µF, 16V, X7R, ±20% Venkel, SMEC C30, C312 Not installed, 120pF, 250V, X7R, ±10% Venkel, SMEC D1, D23 MMBD3004S-7-T Diodes, Inc. (V =350V and I =0.225mA) RRM F FB1, FB2 Ferrite Bead, BLM18AG601SN1B Murata Q1, Q3 NPN, 300V, MMBTA42 OnSemi, Fairchild Q2 PNP, 300V, MMBTA92 OnSemi, Fairchild Q4, Q5 NPN, 60V, 330mW, MMBTA06 OnSemi, Fairchild RV1 Sidactor, 275V, 100A Teccor, Protek, ST Micro R1 1.07k, 1/2W, 1% Venkel, SMEC, Panasonic R2 150, 1/16W, 5% Venkel, SMEC, Panasonic R3 3.65k, 1/2W, 1% Venkel, SMEC, Panasonic R4 2.49k, 1/2W, 1% Venkel, SMEC, Panasonic R5, R6 100k, 1/16W, 5% Venkel, SMEC, Panasonic R7, R83 20M, 1/16W, 5% Venkel, SMEC, Panasonic R9 1M, 1/16W, 1% Venkel, SMEC, Panasonic R10 536, 1/4W, 1% Venkel, SMEC, Panasonic R11 73.2, 1/2W, 1% Venkel, SMEC, Panasonic R12, R13 56.2, 1/16W, 1% Venkel, SMEC, Panasonic R15, R164 0, 1/16W Venkel, SMEC, Panasonic R30, R322 Not installed, 15M, 1/8W, 5% Venkel, SMEC, Panasonic R31, R332 Not installed, 5.1M, 1/8W, 5% Venkel, SMEC, Panasonic R51, R52 4.7k, 1/10W, 5% Venkel, SMEC, Panasonic U1 Si3056 Silicon Labs U2 Si3018/19/10 Silicon Labs Z1 Zener Diode, 43V, 1/2W, ZMM43 General Semiconductor Notes: 1. Value for C3 above is recommended for use with the Si3018. In voice appliations, a C3 value of 3.9nF (250V, X7R, 20%) is recommended to improve return loss performance. 2. C30-31 and R30-33 can be substitued for R7-8 to implent the enhanced caller ID circuit. 3. Several diode configurations are acceptable, with the main requirement being V > 350 and I > 225mA, e.g., part RRM F number HD04-T in a MiniDIP package by Diodes, Inc., two MMBD3004S-7-F diode pairs by Diodes, Inc. in an SOT-23 package, or four 1N4004 diodes. 4. Murata BLM18AG601SN1B may be substituted for R15-R16 (0) to decrease emissions. Rev. 1.06 19

Si3056 Si3018/19/10 4. AOUT PWM Output Figure18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056 for call progress monitoring purposes. Set the PWME bit (Register1, bit 3) to enable this mode. +5 VA LS1 Q6 NPN R41 AOUT C41 Figure 18. AOUT PWM Circuit for Call Progress Table 13. Component Values—AOUT PWM Component Value Supplier LS1 Speaker BRT1209PF-06 Intervox Q6 NPN KSP13 Fairchild C41 0.1µF, 16V, X7R, ±20% Venkel, SMEC R41 1501/16W, ±5% Venkel, SMEC, Panasonic Registers 20 and 21 allow the receive and transmit paths to be attenuated linearly. When these registers are set to all 0s, the receive and transmit paths are muted. These registers affect the call progress output only and do not affect transmit and receive operations on the telephone line. The PWMM[1:0] bits (Register 1, bits 5:4) select one of the three different PWM output modes for the AOUT signal, including a delta-sigma data stream, a conventional 32kHz return to zero PWM output, and balanced 32kHz PWM output. 20 Rev. 1.06

Si3056 Si3018/19/10 5. Functional Description  New features have been added to the Si3056 including more ac terminations, a programmable The Si3056 is an integrated direct access arrangement hybrid, finer gain/attenuation step resolution, finer (DAA) that provides a programmable line interface to resolution loop current monitoring capability, ring meet global telephone line interface requirements. The validation, more HW interrupts, a 200Hz low Si3056 implements Silicon Laboratories® patented frequency filter pole. (See the appropriate functional isolation technology and offers the highest level of descriptions.) integration by replacing an analog front end (AFE), an  The secondary communication data format (see isolation transformer, relays, opto-isolators, and a 2- to "5.26.Digital Interface" on page 37). 4-wire hybrid with two 16-pin packages.  The low-power sleep mode, and system The Si3056 DAA is software programmable to meet requirements to support wake-on-ring. (See global requirements and is compliant with FCC, TBR21, "5.28.Power Management" on page 39.) JATE, and other country-specific PTT specifications as 5.2. Line-Side Device Support shown in Table16 on page26. In addition, the Si3056 meets the most stringent worldwide requirements for Three different line-side devices can be used with the out-of-band energy, emissions, immunity, high-voltage Si3056 system-side device: surges, and safety, including FCC Part 15 and 68,  Globally-compliant line-side device—Targets global EN55022, EN55024, and many other standards. DAA requirements. Use the Si3018 global line-side device for this configuration. This line-side device 5.1. Upgrading from the Si3034/35/44 to supports both FCC-compliant countries and non- Si3056 FCC-compliant countries. The Si3056 offers Silicon Laboratories® customers  Globally-compliant, enhanced features line-side currently using Si3034/35/44 standard serial interface device—Targets embedded and voice applications DAA chipsets with an upgrade path for use in new with global DAA requirements. Use the Si3019 line- designs. The Si3056 digital interface is similar to the side device for this configuration. The Si3019 Si3034/35/44 DAAs, thus the Si3056 retains the ability contains all the features available on the Si3018, to connect to many widely available DSPs. This also plus the following additional features/enhancements: allows customers to leverage software developed for Sixteen selectable ac terminations to increase return existing Si3034/35/44 designs. More importantly, the loss and trans-hybrid loss performance. Si3056 also offers a number of new features not Higher transmit and receive level mode. provided in the Si3034/35/44 DAAs. An overview of the Selectable 200Hz low frequency pole. feature differences between the Si3044 and the Si3056 –16 to 13.5dB digital gain/attenuation adjustment in is presented in Table14. Finally, the globally-compliant 0.1dB increments for the transmit and receive paths. Si3056 can be implemented with roughly half the Programmable line current/voltage threshold interrupt. external components required in the already highly  Globally-compliant, low-speed only line-side integrated Si3034/35/44 DAA application circuits. The device—Targets embedded 2400bps soft modem following items have changed in the Si3056 as applications. Use the Si3010 line-side device for this compared to the Si3034/35/44 DAAs: configuration. The Si3010 contains all the features  The pinout, the application circuit, and the bill of available on the Si3018, except the transmit and materials. The Si3056 is not pin compatible with receive paths are optimized and tested only for Si3034/35/44 DAA chipsets. modem connect rates up to 2400bps. Rev. 1.06 21

Si3056 Si3018/19/10 Table 14. New Si3056 Features Chipset Si3044 Si3056 System-Side Part # Si3021 Line-Side Part # Si3015 Si3010 Si3018 Si3019 Global DAA Yes Yes Yes Yes Digital Interface SSI SSI SSI SSI Power Supply 3.3V or 5V 3.3V 3.3V 3.3V Max Modem Connect Rate 56kbps 2400bps 56kbps 56kbps Data Bus Width 16-bit 16-bit 16-bit 16-bit Control Register Addressing 6-bit 8-bit 8-bit 8-bit Max Sampling Frequency 11.025kHz 16kHz 16kHz 16kHz AC Terminations 2 4 4 16 Programmable Gain 3dB steps 3dB steps 3dB steps 0.1dB steps Loop Current Monitoring 3mA/bit 1.1mA/bit 1.1mA/bit 1.1mA/bit Line Voltage Monitoring 2.75V per bit 1V per bit 1V per bit 1V per bit Polarity Reversal Detection Yes (SW polling) Yes (HW interrupt) Yes (HW interrupt) Yes (HW interrupt) Line I/V Threshold Detection No No No Yes Ring Qualification No Yes Yes Yes Wake-on-Ring Support Yes Yes (MCLK active) Yes (MCLK active) Yes (MCLK active) HW Interrupts Ring detect only 7 HW interrupts 7 HW interrupts 8 HW interrupts Integrated Fixed Analog Yes Yes Yes Yes Hybrid Programmable Digital Hybrid No Yes Yes Yes Full Scale Transmit/Receive +3.2dBm 0dBm 0dBm +3.2dBm Level 22 Rev. 1.06

Si3056 Si3018/19/10 Table 15. Country Specific Register Settings Register 16 31 16 16 26 26 26 302 163 Country OHS OHS2 RZ RT ILIM DCV[1:0] MINI[1:0] ACIM[3:0] ACT ACT2 Argentina 0 0 0 0 0 11 00 0000 0 0 Australia4 1 0 0 0 0 01 01 0011 0 1 Austria 0 1 0 0 1 11 00 0010 0 1 Bahrain 0 1 0 0 1 11 00 0010 0 1 Belgium 0 1 0 0 1 11 00 0010 0 1 Brazil 0 0 0 0 0 11 00 0000 0 0 Bulgaria 0 1 0 0 1 11 00 0011 0 1 Canada 0 0 0 0 0 11 00 0000 0 0 Chile 0 0 0 0 0 11 00 0000 0 0 China5 0 0 0 0 0 11 00 0000/1010 0 0 Colombia 0 0 0 0 0 11 00 0000 0 0 Croatia 0 1 0 0 1 11 00 0010 0 1 Cyprus 0 1 0 0 1 11 00 0010 0 1 Czech Republic 0 1 0 0 1 11 00 0010 0 1 Denmark 0 1 0 0 1 11 00 0010 0 1 Ecuador 0 0 0 0 0 11 00 0000 0 0 Egypt 0 1 0 0 1 11 00 0010 0 1 El Salvador 0 0 0 0 0 11 00 0000 0 0 Finland 0 1 0 0 1 11 00 0010 0 1 France 0 1 0 0 1 11 00 0010 0 1 Germany 0 1 0 0 1 11 00 0010 0 1 Greece 0 1 0 0 1 11 00 0010 0 1 Guam 0 0 0 0 0 11 00 0000 0 0 Hong Kong 0 0 0 0 0 11 00 0000 0 0 Hungary 0 1 0 0 1 11 00 0010 0 1 Iceland 0 1 0 0 1 11 00 0010 0 1 India 0 0 0 0 0 11 00 0000 0 0 Indonesia 0 0 0 0 0 11 00 0000 0 0 Ireland 0 1 0 0 1 11 00 0010 0 1 Israel 0 1 0 0 1 11 00 0010 0 1 Italy 0 1 0 0 1 11 00 0010 0 1 Japan 0 0 0 0 0 01 01 0000 0 0 Jordan 0 0 0 0 0 01 01 0000 0 0 Kazakhstan 0 0 0 0 0 11 00 0000 0 0 Kuwait 0 0 0 0 0 11 00 0000 0 0 Latvia 0 1 0 0 1 11 00 0010 0 1 Note: 1. Supported for loop current  20mA. 2. Available with Si3019 line-side only. 3. Available with Si3018 and Si3010 line-sides only. 4. See "5.11.DC Termination" on page 27 for DCV and MINI settings. 5. ACIM is 0000 for data applications and 1010 for voice applications. 6. For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.) Rev. 1.06 23

Si3056 Si3018/19/10 Table 15. Country Specific Register Settings (Continued) Register 16 31 16 16 26 26 26 302 163 Country OHS OHS2 RZ RT ILIM DCV[1:0] MINI[1:0] ACIM[3:0] ACT ACT2 Lebanon 0 1 0 0 1 11 00 0010 0 1 Luxembourg 0 1 0 0 1 11 00 0010 0 1 Macao 0 0 0 0 0 11 00 0000 0 0 Malaysia1 0 0 0 0 0 01 01 0000 0 0 Malta 0 1 0 0 1 11 00 0010 0 1 Mexico 0 0 0 0 0 11 00 0000 0 0 Morocco 0 1 0 0 1 11 00 0010 0 1 Netherlands 0 1 0 0 1 11 00 0010 0 1 New Zealand 0 0 0 0 0 11 00 0100 1 1 Nigeria 0 1 0 0 1 11 00 0010 0 1 Norway 0 1 0 0 1 11 00 0010 0 1 Oman 0 0 0 0 0 01 01 0000 0 0 Pakistan 0 0 0 0 0 01 01 0000 0 0 Peru 0 0 0 0 0 11 00 0000 0 0 Philippines 0 0 0 0 0 01 01 0000 0 0 Poland 0 1 0 0 1 11 00 0010 0 1 Portugal 0 1 0 0 1 11 00 0010 0 1 Romania 0 1 0 0 1 11 00 0010 0 1 Russia 0 0 0 0 0 11 00 0000 0 0 Saudi Arabia 0 0 0 0 0 11 00 0000 0 0 Singapore 0 0 0 0 0 11 00 0000 0 0 Slovakia 0 1 0 0 1 11 00 0010 0 1 Slovenia 0 1 0 0 1 11 00 0010 0 1 South Africa 0 0 1 0 0 11 00 0011 1 0 South Korea6 0 0 1 0 0 11 00 0000 0 0 Spain 0 1 0 0 1 11 00 0010 0 1 Sweden 0 1 0 0 1 11 00 0010 0 1 Switzerland 0 1 0 0 1 11 00 0010 0 1 Taiwan 0 0 0 0 0 11 00 0000 0 0 TBR21 0 0 0 0 1 11 00 0010 0 1 Thailand 0 0 0 0 0 01 01 0000 0 0 UAE 0 0 0 0 0 11 00 0000 0 0 United Kingdom 0 1 0 0 1 11 00 0101 0 1 USA 0 0 0 0 0 11 00 0000 0 0 Yemen 0 0 0 0 0 11 00 0000 0 0 Note: 1. Supported for loop current  20mA. 2. Available with Si3019 line-side only. 3. Available with Si3018 and Si3010 line-sides only. 4. See "5.11.DC Termination" on page 27 for DCV and MINI settings. 5. ACIM is 0000 for data applications and 1010 for voice applications. 6. For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.) 24 Rev. 1.06

Si3056 Si3018/19/10 5.3. Power Supplies The capacitive communications link is disabled by default. To enable it, the PDL bit (Register6,bit4) must The Si3056 system-side device operates from a 3.0– be cleared. No communication between the system- 3.6V power supply. The Si3056 input pins are 5V side and line-side can occur until this bit is cleared. The tolerant. The Si3056 output pins only drive 3.3V. The clock generator must be programmed to an acceptable line-side device derives its power from two sources: The sample rate before clearing the PDL bit. Si3056 and the telephone line. The Si3056 supplies power over the patented isolation link between the two 5.6. Transmit/Receive Full Scale Level devices, allowing the line-side device to communicate (Si3019 Line-Side Only) with the Si3056 while on-hook and perform other on- The Si3056 supports programmable maximum transmit hook functions such as line voltage monitoring. When and receive levels. The default signal level supported by off-hook, the line-side device also derives power from the Si3056 is 0dBm into a 600 load. Two additional the line current supplied from the telephone line. This feature is exclusive to DAAs from Silicon Laboratories® modes of operation offer increased transmit and receive level capability to enable use of the DAA in applications and allows the most cost-effective implementation for a that require higher signal levels. The full scale mode is DAA while still maintaining robust performance over all enabled by setting the FULL bit in Register 31. With line conditions. FULL=1, the full scale signal level increases to 5.4. Initialization +3.2dBm into a 600 load, or 1dBV into all reference impedances. The enhanced full scale mode (or 2X full When the Si3056 is powered up, assert the RESET pin. scale) is enabled by setting the FULL2 bit in Register When the RESET pin is deasserted, the registers have 30. Will FULL2=1, the full scale signal level increases default values. This reset condition guarantees the line- to +6.0dBm into a 600 load, or 1.5dBV into all side device is powered down without the possibility of reference impedances. The full scale and enhanced full loading the line (i.e., off-hook). An example initialization scale modes provide the ability to trade off TX power procedure is outlined in the following list: and TX distortion for a peak signal. By using the 1. Program the PLL with registers 8 and 9 (N[7:0], programmable digital gain registers in conjunction with M[7:0]) to the appropriate divider ratios for the the enhanced full scale signal level mode, a specific supplied MCLK frequency and the sample rate in power level (+3.2dBm for example) could be achieved register 7 (SRC), as defined in "5.25.Clock across all ACT settings. Generation" on page 36. 5.7. Parallel Handset Detection 2. Wait 1ms until the PLL is locked. 3. Write a 00H into Register 6 to power up the line-side The Si3056 can detect a parallel handset going off- device. hook. When the Si3056 is off-hook, the loop current can be monitored with the LCS bits. A significant drop in 4. Set the required line interface parameters (i.e., loop current signals that a parallel handset is going off- DCV[1:0], MINI[1:0], ILIM, DCR, ACT and ACT2 or hook. If a parallel handset causes the LCS bits to read ACIM[3:0], OHS, RT, RZ, ATX[2:0] or TGA2 and all 0s, the Drop-Out Detect (DOD) bit can be checked to TXG2) as defined by “Country Specific Register verify a valid line exists. Settings” shown in Table15. The LVS bits can be read to determine the line voltage When this procedure is complete, the Si3056 is ready when on-hook and off-hook. Significant drops in line for ring detection and off-hook. voltage can signal a parallel handset. For the Si3056 to 5.5. Isolation Barrier operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to The Si3056 achieves an isolation barrier through low- support two off-hook DAAs on the same line. Improved cost, high-voltage capacitors in conjunction with Silicon parallel handset operation can be achieved by changing Laboratories® proprietary signal processing techniques. the dc impedance from 50 to 800 and reducing the These techniques eliminate signal degradation from DCT pin voltage with the DVC[1:0] bits. capacitor mismatches, common mode interference, or noise coupling. As shown in Figure17 on page 18, the 5.8. Line Voltage/Loop Current Sensing C1, C2, C8, and C9 capacitors isolate the Si3056 The Si3056 can measure loop current and line voltage (system-side) from the line-side device. Transmit, with the Si3010, Si3018, and the Si3019 line-side receive, control, ring detect, and caller ID data are devices. The 8-bit LCS2[7:0] and LCS[4:0] registers passed across this barrier. Y2 class capacitors can be report loop current. The 8-bit LVS[7:0] register reports used to achieve surge performance of 5kV or greater. line voltage. Rev. 1.06 25

Si3056 Si3018/19/10 These registers can help determine the following: detection of another phone going off-hook by monitoring the dc loop current. The LCS bits are decoded from  When on-hook, detect if a line is connected. LCS2; so, both are available at the same time. The line  When on-hook, detect if a parallel phone is off-hook. current sense transfer function is shown in Figure19  When off-hook, detect if a parallel phone goes on or and detailed in Table16. The LCS and LCS2 bits report off-hook. loop current down to the minimum operating loop  Detect if enough loop current is available to operate. current for the DAA. Below this threshold, the reported  When used in conjunction with the OPD bit, detect if value of loop current is unpredictable. an overcurrent condition exists. (See "5.22.Overload Detection" on page 35.) Table 16. Loop Current Transfer Function 5.8.1. Line Voltage Measurement LCS[4:0] Condition The Si3056 device reports line voltage with the LVS[7:0] bits (Register29) in both on- and off-hook states with a 00000 Insufficient line current for normal resolution of 1V per bit. The accuracy of these bits is operation. Use the DOD bit (Register19, approximately ±10%. Bits 0 through 6 of this register bit1) to determine if a line is connected. indicate the value of the line voltage in 2s compliment 00100 Minimum line current for normal operation. format. Bit 7 of this register indicates the polarity of the tip/ring voltage. 11111 Loop current is greater than 127mA. An overcurrent situation may exist. If the INTE bit (Register2) and the POLM bit (Register 3) are set, a hardware interrupt is generated on the 5.9. Off-Hook AOUT/INT pin when bit 7 of the LVS register changes state. The edge-triggered interrupt is cleared by writing The communication system generates an off-hook 0 to the POLI bit (Register 4). The POLI bit is set each command by applying a logic0 to the OFHK pin or by time bit 7 of the LVS register changes state and must be setting the OH bit (Register5,bit0).The OFHK pin must written to 0 to clear it. be enabled by setting the OHE bit (Register5,bit 1). The default state of the LVS register forces the LVS bits The polarity of the OFHK pin is selected by the OPOL to 0 when the line voltage is 3V or less. The LVFD bit bit (Register5,bit4). With OFHK asserted, the system (Register 31, bit 0) disables the force-to-zero function is in an off-hook state. and allows the LVS register to display non-zero values The off-hook state seizes the line for incoming/outgoing of 3V and below. This register might display calls and also can be used for pulse dialing. With OFHK unpredictable values at line voltages between 0to 2V. deasserted, negligible dc current flows through the At 0V, the LVS register displays all 0s. hookswitch. When the OFHK pin is asserted, the hookswitch transistor pair, Q1 and Q2, turn on. This 5.8.2. Loop Current Measurement applies a termination impedance across TIP and RING When the Si3056 is off-hook, the LCS2[7:0] and and causes dc loop current to flow. The termination LCS[4:0] bits measure loop current in 1.1mA/bit and impedance has an ac and dc component. 3.3mA/bit resolution respectively. These bits enable Possible Overload 30 25 20 LCS BITS 15 10 5 0 0 3.3 6.6 9.913.216.519.823.126.429.733 36.339.642.946.249.L5o5o2.p8 5C6.u1r5r9e.1nt6 2(.7m6A6)69.372.675.979.282.585.889.192.495.799102.3 127 Figure 19. Typical Loop Current LCS Transfer Function 26 Rev. 1.06

Si3056 Si3018/19/10 Several events occur in the DAA when the OFHK pin is Registers 43 and 44 contain the line current/voltage asserted or the OH bit is set. There is a 250s latency threshold interrupt. This interrupt will trigger when either to allow the off-hook command to be communicated to the measured line voltage or current in the LVS or LCS2 the line-side device. Once the line-side device goes off- registers, as selected by the CVS bit (Register 44, bit 2), hook, an off-hook counter forces a delay for line crosses the threshold programmed into the CVT[7:0] transients to settle before transmission or reception bits. An interrupt can be programmed to occur when the occurs. This off-hook counter time is controlled by the measured value rises above or falls below the FOH[1:0] bits (Register31,bits6:5). The default setting threshold. Only the magnitude of the measured value is for the off-hook counter time is 128ms, but can be used to compare to the threshold programmed into the adjusted up to 512ms or down to either 64 or 8ms. CVT[7:0] bits, and thus only positive numbers should be used as a threshold. This line current/voltage threshold After the off-hook counter has expired, a resistor interrupt is only available with the Si3019 line-side calibration is performed for 17ms. This allows circuitry device. internal to the DAA to adjust to the exact conditions present at the time of going off-hook. This resistor 5.11. DC Termination calibration can be disabled by setting the RCALD bit (Register 25, bit 5). The DAA has programmable settings for dc impedance, minimum operational loop current, and TIP/RING After the resistor calibration is performed, an ADC voltage. The dc impedance of the DAA is normally calibration is performed for 256ms. This calibration represented with a 50 slope as shown in Figure20, helps to remove offset in the A/D sampling the but can be changed to an 800 slope by setting the telephone line. This ADC calibration can be disabled by DCR bit. This higher dc termination presents a higher setting the CALD bit (Register17, bit5). See resistance to the line as loop current increases. “5.29.Calibration” on page39. for more information on automatic and manual calibration. . Silicon Laboratories® recommends that the resistor and FCC DCT Mode 12 the ADC calibrations not be disabled except when a fast ) response is needed after going off-hook, such as when (V 11 responding to a Type II caller-ID signal. See “5.21.Caller A A ID” on page32. D 10 s To calculate the total time required to go off-hook and s o 9 start transmission or reception, the digital filter delay r c A (typically 1.5ms with the FIR filter) should be included e 8 in the calculation. g a 5.10. Interrupts Volt 7 6 The AOUT/INT pin can be used as a hardware interrupt .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 pin by setting the INTE bit (Register2,bit7). When this bit is set, the call progress output function (AOUT) is not Loop Current (A) available. The default state of this interrupt output pin is Figure 20. FCC Mode I/V Characteristics, active low, but active high operation can be enabled by DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0 setting the INTP bit (Register2, bit6). This pin is an open-drain output when the INTE bit is set, and requires For applications that require current limiting per the a 4.7k pullup or pulldown for correct operation. If TBR21 standard, the ILIM bit can be set to select this multiple INT pins are connected to a single input, the mode. In the current limiting mode, the dc I/V curve is combined pullup or pulldown resistance should equal changed to a 2000  slope above 40mA, as shown in 4.7k. Bits 7–2, and 0 in Register 3 and bit 1 in Figure21. The DAA operates with a 50V, 230 feed, Register 44 can be set to enable hardware interrupt which is the maximum line feed specified in the TBR21 sources. When one or more of these bits are set, the standard. AOUT/INT pin becomes active and stays active until the interrupts are serviced. If more than one hardware interrupt is enabled in Register 3, software polling determines the cause of the interrupts. Register4 and bit 3 of Register 44 contain sticky interrupt flag bits. Clear these bits after being set to service the interrupt. Rev. 1.06 27

Si3056 Si3018/19/10 TBR21 DCT Mode Table 17. AC Termination Settings for the Si3010 45 and Si3018 Line-Side Devices V) 40 A ( 35 ACT ACT2 AC Termination A D 30 0 0 Real, nominal 600  termination that sat- s s isfies the impedance requirements of o 25 cr FCC part 68, JATE, and other countries. A 20 e g 15 1 0 Complex impedance that satisfies global a olt 10 impedance requirements. V 0 1 Complex impedance that satisfies global 5 .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 impedance requirements EXCEPT New Zealand. Achieves higher return loss for Loop Current (A) countries requiring complex ac termina- Figure 21. TBR21 Mode I/V Characteristics, tion. [220 + (820 || 120nF) and DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 1 220 + (820 || 115nF)] The MINI[1:0] bits select the minimum operational loop 1 1 Complex impedance for use in New Zea- current for the DAA, and the DCV[1:0] bits adjust the land. [370 + (620 || 310nF)] DCT pin voltage, which affects the TIP/RING voltage of the DAA. These bits permit important trade-offs for the Table 18. AC Termination Settings for the system designer. Increasing the TIP/RING voltage provides more signal headroom, while decreasing the Si3019 Line-Side Device TIP/RING voltage allows compliance to PTT standards in low-voltage countries such as Japan. Increasing the ACIM[3:0] AC Termination minimum operational loop current above 10mA also 0000 600 increases signal headroom and prevents degradation of the signal level in low-voltage countries. 0001 900 Finally, Australia has separate dc termination 0010 270 + (750 || 150nF) and 275 requirements for line seizure versus line hold. Japan + (780 || 150nF) mode may be used to satisfy both requirements. However, if a higher transmit level for modem operation 0011 220 + (820 || 120nF) and is desired, switch to FCC mode 500ms after the initial 220 + (820 || 115nF) off-hook. This satisfies the Australian dc termination 0100 370 + (620 || 310nF) requirements. 0101 320 + (1050 || 230nF) 5.12. AC Termination The Si3056 has four ac termination impedances with 0110 370 + (820 || 110nF) the Si3018 line-side device and sixteen ac termination 0111 275 + (780 || 115nF) impedances with the Si3019 line-side device. The ACT and ACT2 bits select the ac impedance on the Si3018 1000 120 + (820 || 110nF) line-side device. The ACIM[3:0] bits select the ac 1001 350 + (1000 || 210nF) impedance on the Si3019. The available ac termination settings are listed for the line-side devices in Tables 17 1010 200 + (680 || 100nF) and 18. 1011 600 + 2.16µF The most widely used ac terminations are available as register options to satisfy various global PTT 1100 900 + 1µF requirements. The real 600 impedance satisfies the 1101 900 + 2.16µF requirements of FCC part 68, JATE, and many other countries. The 270+ (750 || 150nF) satisfies the 1110 600 + 1µF requirements of TBR21 (ACT=0, ACT=1, or ACIM [3:0]=0010). 1111 Global complex impedance 28 Rev. 1.06

Si3056 Si3018/19/10 There are two selections that are useful for satisfying setting the RPOL bit (Register14, bit 1). This pin is a non-standard ac termination requirements. The 350+ standard CMOS output. If multiple RGDT pins are (1000||210 nF) impedance selection is the ANSI/ connected to a single input, the combined pullup or EIA/TIA 464 compromise impedance network for trunks. pulldown resistance should equal 4.7k The last ac termination selection, ACIM[3:0]=1111, is When the RFWE bit is 0, the RGDT pin is asserted designed to satisfy minimum return loss requirements when the ring signal is positive, which results in an for every country in the world that requires a complex output signal frequency equal to the actual ring termination. For any of the ac termination settings, the frequency. When the RFWE bit is 1, the RGDT pin is programmable hybrid can be used to further reduce asserted when the ring signal is positive or negative. near-end echo. See “5.13.Transhybrid Balance” for The output then appears to be twice the frequency of more details. the ring waveform. 5.13. Transhybrid Balance The second method to monitor ring detection uses the ring detect bits (RDTP, RDTN, and RDT). The RDTP The Si3056 contains an on-chip analog hybrid that and RDTN behavior is based on the RNG1-RNG2 performs the 2- to 4-wire conversion and near-end echo voltage. When the signal on RNG1-RNG2 is above the cancellation. This hybrid circuit is adjusted for each ac positive ring threshold, the RDTP bit is set. When the termination setting selected. signal on RNG1-RNG2 is below the negative ring The Si3056 also offers a digital filter stage for additional threshold, the RDTN bit is set. When the signal on near-end echo cancellation. For each ac termination RNG1-RNG2 is between these thresholds, neither bit is setting selected, the eight programmable hybrid set. registers (Registers 45-52) can be programmed with The RDT behavior is also based on the RNG1-RNG2 coefficients to provide increased cancellation of real- voltage. When the RFWE bit is 0, a positive ring signal world line anomalies. This digital filter can produce sets the RDT bit for a period of time. When the RFWE 10dB or greater of near-end echo cancellation in bit is 1, a positive or negative ring signal sets the RDT addition to the echo cancellation provided by the analog bit. hybrid circuitry. The RDT bit acts like a one shot. When a new ring 5.14. Ring Detection signal is detected, the one shot is reset. If no new ring The ring signal is resistively coupled from TIP and RING signals are detected prior to the one shot counter to the RNG1 and RNG2 pins. The Si3056 supports reaching 0, then the RDT bit clears. The length of this either full- or half-wave ring detection. With full-wave count is approximately 5 seconds. The RDT bit is reset ring detection, the designer can detect a polarity to 0 by an off-hook event. If the RDTM bit reversal of the ring signal. See “5.21.Caller ID” on (Register3,bit7) is set, a hardware interrupt occurs on page32. The ring detection threshold is programmable the AOUT/INT pin when RDT is triggered. This interrupt can be cleared by writing to the RDTI bit with the RT bit (Register16,bit0). The ring detector (Register4,bit7). When the RDI bit (Register2, bit2) is output can be monitored in three ways. The first method uses the RGDT pin. The second method uses the set, an interrupt occurs on both the beginning and end register bits, RDTP, RDTN, and RDT (Register5). The of the ring pulse. Ring validation may be enabled when final method uses the DTX output. using the RDI bit. The ring detector mode is controlled by the RFWE bit The third method to monitor detection uses the DTX (Register18,bit1). When the RFWE bit is 0 (default data samples to transmit ring data. If the mode), the ring detector operates in half-wave rectifier communications link is active (PDL=0) and the device mode. In this mode, only positive ring signals are is not off-hook or in on-hook line monitor mode, the ring detected. A positive ring signal is defined as a voltage data is presented on DTX. The waveform on DTX greater than the ring threshold across RNG1-RNG2. depends on the state of the RFWE bit. Conversely, a negative ring signal is defined as a When RFWE is 0, DTX is –32768 (0x8000) while the voltage less than the negative ring threshold across RNG1-RNG2 voltage is between the thresholds. When RNG1-RNG2. When the RFWE bit is 1, the ring detector a ring is detected, DTX transitions to +32767 when the operates in full-wave rectifier mode. In this mode, both ring signal is positive, then goes back to –32768 when positive and negative ring signals are detected. the ring is near 0 and negative. Thus a near square The first method to monitor ring detection output uses wave is presented on DTX that swings from –32768 to the RGDT pin. When the RGDT pin is used, it defaults +32767 in cadence with the ring signal. to active low, but can be changed to active high by When RFWE is 1, DTX sits at approximately +1228 Rev. 1.06 29

Si3056 Si3018/19/10 while the RNG1-RNG2 voltage is between the  Delay period between when the ring signal is thresholds. When the ring becomes positive, DTX validated and when a valid ring signal is indicated to transitions to +32767. When the ring signal goes near 0, accommodate distinctive ringing. DTX remains near 1228. As the ring becomes negative, The RNGV bit (Register24, bit7) enables or disables the DTX transitions to –32768. This repeats in cadence the ring validation feature in normal operating mode and with the ring signal. low-power sleep mode. To observe the ring signal on DTX, watch the MSB of Ring validation affects the behavior of the RDT status the data. The MSB toggles at the same frequency as bit, the RDTI interrupt, the INT pin, and the RGDT pin. the ring signal independent of the ring detector mode. 1. When ring validation is enabled, the status bit seen This method is adequate for determining the ring in the RDT read-only bit (r5.2), represents the frequency. detected envelope of the ring. The ring validation 5.15. Ring Validation parameters are configurable so that this envelope may remain high throughout a distinctive-ring This feature prevents false triggering of a ring detection sequence. by validating the ring frequency. Invalid signals, such as 2. The RDTI interrupt fires when a validated ring a line voltage change when a parallel handset goes off- occurs. If RDI is zero (default), the interrupt occurs hook, pulse dialing, or a high-voltage line test are on the rising edge of RDT. If RDI is set, the interrupt ignored. Ring validation can be enabled during normal occurs on both rising and falling edges of RDT. operation and in low power sleep mode. The external MCLK signal is required in low power sleep mode for 3. The INT pin follows the RDTI bit with configurable ring validation. polarity. The ring validation circuit operates by calculating the The RGDT pin can be configured to follow the ringing time between alternating crossings of positive and signal envelope detected by the ring validation circuit by negative ring thresholds to validate that the ring setting RFWE to 0. If RFWE is set to 1, the RGDT pin frequency is within tolerance. High and low frequency follows an unqualified ring detect one-shot signal tolerances are programmable in the RAS[5:0] and initiated by a ring-threshold crossing and terminated by RMX[5:0] fields. The RCC[2:0] bits define how long the a fixed counter timeout of approximately 5 seconds. ring signal must be within tolerance. (This information is shown in Register18). Once the duration of the ring frequency is validated by 5.16. Ringer Impedance and Threshold the RCC bits, the circuitry stops checking for frequency The ring detector in many DAAs is ac coupled to the line tolerance and begins checking for the end of the ring with a large 1µF, 250V decoupling capacitor. The ring signal, which is defined by a lack of additional threshold detector on the Si3056 is resistively coupled to the line. crossings for a period of time configured by the This produces a high ringer impedance to the line of RTO[3:0] bits. When the ring frequency is first validated, approximately 20Mtomeet the majority of country a timer defined by the RDLY[2:0] bits is started. If the PTT specifications, including FCC and TBR21. RDLY[2:0] timer expires before the ring timeout, then the ring is validated and a valid ring is indicated. If the Several countries including Poland, and South Africa, ring timeout expires before the RDLY[2:0] timer, a valid may require a maximum ringer impedance that can be ring is not indicated. met with an internally synthesized impedance by setting the RZ bit (Register16, bit 1). Ring validation requires five parameters: Some countries also specify ringer thresholds  Timeout parameter to place a lower limit on the differently. The RT bit (Register 16, bit 0) selects frequency of the ring signal on the RAS[5:0] bits between two different ringer thresholds: 15V ±10% and (Register 24). This is measured by calculating the 21.5V ±10%. These two settings satisfy ringer time between crossings of positive and negative ring threshold requirements worldwide. The thresholds are thresholds. set so that a ring signal is guaranteed to not be detected  Minimum count to place an upper limit on the below the minimum, and a ring signal is guaranteed to frequency on the RMX[5:0] bits (Register 22). be detected above the maximum.  Time interval over which the ring signal must be the correct frequency on the RCC[2:0] bits (Register 23).  Timeout period that defines when the ring pulse has ended based on the most recent ring threshold crossing. 30 Rev. 1.06

Si3056 Si3018/19/10 5.17. Pulse Dialing and Spark Quenching enough to excessively reduce the line-derived power supply of the line-side device. Pulse dialing results from going off- and on-hook to generate make and break pulses. The nominal rate is The OVL bit (Register19) can be polled following a 10 pulses per second. Some countries have strict billing tone detection. The OVL bit indicates that the specifications for pulse fidelity that include make and billing tone has passed when it returns to 0. The BTD break times, make resistance, and rise and fall times. In and ROV bits are sticky, and must be written to 0 to be a traditional solid-state dc holding circuit, there are reset. After the billing tone passes, the DAA initiates an many problems in meeting these requirements. auto-calibration sequence that must complete before data can be transmitted or received. The Si3056 dc holding circuit actively controls the on- hook and off-hook transients to maintain pulse dialing Certain line events, such as an off-hook event on a fidelity. parallel phone or a polarity reversal, can trigger the ROV or the BTD bits. Look for multiple events before Spark quenching requirements in countries such as qualifying if billing tones are present. After the billing Italy, the Netherlands, South Africa, and Australia deal tone passes, the DAA initiates an auto-calibration with the on-hook transition during pulse dialing. These sequence that must complete before data can be tests provide an inductive dc feed resulting in a large transmitted or received. voltage spike. This spike is caused by the line inductance and the sudden decrease in current through Although the DAA remains off-hook during a billing tone the loop when going on-hook. The traditional solution to event, the received data from the line is corrupted when the problem is to put a parallel resistive capacitor (RC) a large billing tone occurs. If the user wishes to receive shunt across the hookswitch relay. However, the data through a billing tone, an external LC filter must be capacitor required is large (~1F, 250V) and relatively added. A manufacturer can provide this filter to users in expensive. In the Si3056, loop current can be controlled the form of a dongle that connects on the phone line to achieve three distinct on-hook speeds to pass spark before the DAA. This prevents the manufacturer from quenching tests without additional BOM components. having to include a costly LC filter to support multiple Through settings of four bits in three registers, OHS countries and customers. (Register 16), OHS2 (Register 31), SQ1 and SQ0 Alternatively, when a billing tone is detected, the system (Register 59), a slow ramp down of loop current can be software notifies the user that a billing tone has achieved which induces a delay between the time OH occurred. Notification prompts the user to contact the bit is cleared and the time the DAA actually goes on- telephone company to disable billing tones or to hook. purchase an external LC filter. To ensure proper operation of the DAA during pulse Disturbance on the line other than billing tones can also dialing, disable the automatic resistor calibration that is cause a receive overload. Some conditions may result in performed each time the DAA enters the off-hook state a loop current collapse to a level below the minimum by setting the RCALD bit (Register 25, bit 5). required operating current of the DAA. When this occurs, the dropout detect bit (DOD) is set, and an interrupt will 5.18. Billing Tone Protection and Receive be generated if the dropout detect interrupt mask bit Overload (DODM) is set. “Billing tones” or “metering pulses” generated by the 5.19. Billing Tone Filter (Optional) Central Office can cause modem connection difficulties. To operate without degradation during billing tones in The billing tone is typically either a 12or16kHz signal Germany, Switzerland, and South Africa, requires an and is sometimes used in Germany, Switzerland, and external LC notch filter. The Si3056 can remain off-hook South Africa. Depending on line conditions, the billing during a billing tone event, but line data is lost in the tone might be large enough to cause major errors in the presence of large billing tone signals. The notch filter line data. The Si3056 chipset can provide feedback design requires two notches, one at 12kHz and one at indicating the beginning and end of a billing tone. 16kHz. Because these components are expensive and Billing tone detection is enabled with the BTE bit few countries utilize billing tones, this filter is typically (Register17, bit2). Billing tones less than 1.1VPK on placed in an external dongle or added as a population the line are filtered out by the low pass digital filter on option for these countries. Figure22 shows an example the Si3056. The ROV bit is set when a line signal is billing tone filter. greater than 1.1V , indicating a receive overload PK condition. The BTD bit is set when a billing tone is large Rev. 1.06 31

Si3056 Si3018/19/10 5.21. Caller ID C1 The Si3056 can pass caller ID data from the phone line to a caller ID decoder connected to the serial port. C2 5.21.1. Type I Caller ID Type I Caller ID sends the CID data while the phone is L1 on-hook. TIP In systems where the caller ID data is passed on the phone line between the first and second rings, utilize the To From L2 following method to capture the caller ID data: DAA Line 1. After identifying a ring signal using one of the C3 methods described in "5.14.Ring Detection" on page RING 29, determine when the first ring is complete. 2. Assert the ONHM bit (Register5, bit3) to enable Figure 22. Billing Tone Filter caller ID data detection. The caller ID data passed L1 must carry the entire loop current. The series across the RNG 1/2 pins is presented to the host via resistance of the inductors is important to achieve a the SDO pin. narrow and deep notch. This design has more than 3. Clear the ONHM bit after the caller ID data is 25dB of attenuation at both 12kHz and 16kHz. received. In systems where the caller ID data is preceded by a Table 19. Component Values—Optional Billing line polarity (battery) reversal, use the following method Tone Filters to capture the caller ID data: Symbol Value 1. Enable full wave rectified ring detection (RFWE, Register18, bit 1). C1,C2 0.027µF, 50V, ±10% 2. Monitor the RDTP and RDTN register bits (or the C3 0.01µF, 250V, ±10% POLI bit) to identify whether a polarity reversal or ring signal has occurred. A polarity reversal trips L1 3.3mH, >120mA, <10 , ±10% either the RDTP or RDTN ring detection bits, and L2 10mH, >40mA, <10 , ±10% thus the full-wave ring detector must be used to distinguish a polarity reversal from a ring. The lowest The billing tone filter affects the ac termination and specified ring frequency is 15Hz; therefore, if a return loss. The global complex ac termination battery reversal occurs, the DSP should wait a (ACIM=1111) passes global return loss specifications minimum of 40ms to verify that the event observed with and without the billing tone filter by at least 3dB. is a battery reversal and not a ring signal. This time is greater than half the period of the longest ring 5.20. On-Hook Line Monitor signal. If another edge is detected during this 40ms The on-hook line monitor mode allows the Si3056 to pause, this event is characterized as a ring signal receive line activity when in an on-hook state. A low- and not a battery reversal. power ADC located on the line-side device digitizes the 3. Assert the ONHM bit (Register 5, bit 3) to enable the signal passed across the RNG1/2 pins and then sends caller ID data detection. The caller ID data passed the signal digitally across the communications link to the across the RNG 1/2 pins is presented to the host via host. This mode is typically used to detect caller ID data the SDO pin. and is enabled by setting the ONHM bit (Register5, 4. Clear the ONHM bit after the caller ID data is bit3). Caller ID data can be gained up or attenuated received. using the receive gain control bits in registers 39 and 5.21.2. Type II Caller ID 41. Type II Caller ID sends the CID data while the phone is off-hook and is often referred to as callerID/callwaiting (CID/CW). To receive the CID data while off-hook, use the following procedure (see Figure23): 1. The Caller Alert Signal (CAS) tone is sent from the Central Office (CO) and is digitized along with the 32 Rev. 1.06

Si3056 Si3018/19/10 line data. The host processor must detect the f. Set the OH bit to 1 (or drive the OFHK pin to the presence of this tone. active state) to return to an off-hook state. After returning to an off-hook state and waiting 8 ms 2. The DAA must then check for another parallel device on the same line. This is accomplished by briefly for the off-hook counter, normal data going on-hook, measuring the line voltage, and then transmission and reception can proceed. If a non-compliant parallel device is present, then a returning to an off-hook state. reply tone is not sent by the host tone generator a. Set the CALD bit (Register17, bit 5) to disable and the CO does not proceed with sending the the calibration that automatically occurs when CID data. If all devices on the line are Type II CID going off-hook. compliant, then the host must mute its upstream b. Set the RCALD bit (Register 25, bit 5) to disable data output to avoid propagation of its reply tone the resistor calibration from occurring when and the subsequent CID data. After muting its going off-hook. upstream data output, the host processor should c. Set the FOH[1:0] bits (Register 31, bits 6:5) to 11 then return an acknowledgement (ACK) tone to to reduce the off-hook counter time to 8ms. the CO to request the transmission of the CID d. Clear the OH bit (or drive the OFHK pin to the data. inactive state) to put the DAA in an on-hook 3. The CO then responds with the CID data and the state. The RXM bit (Register 19, bit 3) may also host processor unmutes the upstream data output be set to mute the receive path. and continues with normal operation. e. Read the LVS bits to determine the state of the 4. The muting of the upstream data path by the host line. processor mutes the handset in a telephone If the LVS bits read the typical on-hook line application so the user cannot hear the voltage, then no parallel devices are active on acknowledgement tone and CID data being sent. the line and CID data reception can be 5. The CALD and RCALD bits can be cleared to re- continued. enable the automatic calibration when going off- If the LVS bits read well below the typical on- hook. The FOH[1:0] bits also can be programmed to hook line voltage, then one or more devices are 01 to restore the default off-hook counter time. present and active on the same line that are not Because of the nature of the low-power ADC, the data compliant with Type II CID. Do not continue CID presented on SDO could have up to a 10% dc offset. data reception. The caller ID decoder must either use a high pass or a band pass filter to accurately retrieve the caller ID data. Rev. 1.06 33

Si3056 Si3018/19/10 1 2 3 4 Off-Hook Counter CAS Tone LINE On-Hook and Calibration Off-Hook On-Hook Off-Hook Counter Off-Hook Ack (402.75 ms nominally) Received (8 ms) FOH[1] Bit FOH[0] Bit RCALD Bit CALD Bit OH Bit6 Notes: 1. The off-hook counter and calibrations prevent transmission or reception of data for 402.75ms (default) for the line voltage to settle. 2. The caller alert signal (CAS) tone transmits from the CO to signal an incoming call. 3. The device is taken on-hook to read the line voltage in the LVS bits to detect parallel handsets. In this mode, no data is transmitted on the SDO pin. 4. When the device returns off-hook, the normal off-hook counter is reduced to 8ms. If the CALD and RCALD bits are set, then the automatic calibrations are not performed. 5. After allowing the off-hook counter to expire (8ms), normal transmission and reception can continue. If CID data reception is required, send the appropriate signal to the CO at this time. 6. This example uses the OH bit to put the Si3056 into an off-hook state. The OFHK pin can also be used to accomplish this. To use the OFHK pin instead of the OH bit, simply enable the OHE bit (Register5,bit1) and drive the OFHK pin low during the preceding sequence. This has the same effect as setting the OH bit. Figure 23. Implementing Type II Caller ID on the Si3056 34 Rev. 1.06

Si3056 Si3018/19/10 5.22. Overload Detection 5.23. Gain Control The Si3056 can be programmed to detect an overload The Si3056 supports different gain and attenuation condition that exceeds the normal operating power settings depending on the line-side device being used. range of the DAA circuit. To use the overload detection For both devices, gains of 0, 3, 6, 9, and 12 dB can be feature, the following steps should be followed: selected for the receive path with the ARX[2:0] bits. The 1. Set the OH bit (Register 5, bit 0) to go off-hook, and receive path can also be muted with the RXM bit. wait 25 ms to allow line transients to settle. Attenuations of 0, 3, 6, 9, and 12dB can also be selected for the transmit path with the ATX[2:0] bits. The 2. Enable overload detection by then setting the OPE transmit path also can be muted with the TXM bit bit high (Register 17, bit 3). (Register 15). If the DAA then senses an overload situation, it When using the Si3019 line-side device, the Si3056 automatically presents an 800 impedance to the line provides even more flexible gain and attenuation to reduce the hookswitch current. At this time, the DAA settings. The TXG2 and RXG2 bits (registers 38–39) also sets the OPD bit (Register 19, bit 0) to indicate that enable gain or attenuation in 1dB increments up to an overload condition exists. The line current detector 15dB for the transmit and receive paths. The TGA2 and within the DAA has a threshold that is dependant upon RGA2 bits select either gain or attenuation for these the ILIM bit (Register 26). When ILIM=0, the overload registers. The TXG3 and RXG3 bits (registers 40–41) detection threshold equals 160mA. When ILIM=1, the enable gain or attenuation in 0.1dB increments up to overload detection threshold equals 60mA. The OPE 1.5dB for the transmit and receive paths. The TGA3 bit should always be cleared before going off-hook. and RGA3 bits select either gain or attenuation for these registers. These additional gain/attenuation registers are active only when the ARX[2:0] and ATX[2:0] bits are set to all 0s. DAC ACT TX To Analog Link CO Si3056 Hybrid ADC Figure 24. Line-Side Device Signal Flow Diagram IIRE SDI TXG2 TTXXGA33 Digital TXA2 Filter 1 dB 0.1 dB 1 dB Gain Gain/ATT Attenuation Steps Steps Steps To Digital Link Line-side Hybrid Device 1 dB 0.1 dB 1 dB Attenuation Gain/ATT Gain Steps Steps Steps IIRE SDO RXA2 Digital RXG3 RXG2 RXA3 Filter Figure 25. Si3056 Signal Flow Diagram Rev. 1.06 35

Si3056 Si3018/19/10 5.24. Filter Selection N (Register8) and M (Register9) are 8-bit unsigned values. F is the frequency of the clock provided to The Si3056 supports additional filter selections for the MCLK the MCLK pin. receive and transmit signals as defined in Table11 and Table12 on page15. The IIRE bit (Register16, bit 4) Table20 lists several standard crystal oscillator rates selects between the IIR and FIR filters. The IIR filter that can be supplied to MCLK. This list represents a provides a shorter, but non-linear, group delay sample of MCLK frequency choices. Many others are alternative to the default FIR filter and only operates possible. with an 8kHz sample rate. Also, on the Si3019 line-side After PLL1 is programmed, the SRC[3:0] bits can device, the FILT bit (Register 31, bit 1) selects a–3dB achieve the standard modem sampling rates with a low frequency pole of 5 Hz when cleared and 200Hz single write to Register 7. See "Register 7.Sample Rate when set. The FILT bit affects the receive path only. Control" on page 54. 5.25. Clock Generation When programming the registers of the clock generator, the order of register writes is important. For PLL1 The Si3056 has an on-chip clock generator. Using a updates, N (Register8, bits 7:0) must be written first, single MCLK input frequency, the Si3056 generates all then immediately followed by a write to M (Register9, the desired standard modem sample rates. bits 7:0). The clock generator consists of two phase-locked loops The values shown in Table20 satisfy the preceding (PLL1 and PLL2) that achieve the desired sample equation. However, when programming the registers for frequencies. Figure26 illustrates the clock generator. N and M, the value placed in these registers must be The architecture of the dual PLL scheme provides fast one less than the value calculated from the equations. lock time on initial start-up, fast lock time when For example, with an MCLK of 46.08MHz, the values changing modem sample rates, high noise immunity, placed in the N and M registers are 0x0Dh and 0x1Fh, and can change modem sample rates with a single respectively. register write. Many MCLK frequencies between 1and60MHz are supported. MCLK should be from a Table 20. MCLK Examples clean source, preferably directly from a crystal with a constant frequency and no dropped pulses. MCLK (MHz) N M In serial mode 2 (refer to the “5.26.Digital Interface” 1.8432 3 160 section), the Si3056 operates as a slave device. The 4.0960 1 24 clock generator is configured based on the SRC register to generate the required internal clock frequencies. In 6.1440 1 16 this mode, PLL2 is powered-down. For further details of 8.1920 1 12 slave mode operation, see "5.27.Multiple Device 9.2160 3 32 Support" on page 38. 5.25.1. Programming the Clock Generator 10.3680 27 256 As shown in Figure26, PLL1 must output a clock equal 11.0592 9 80 to 98.304MHz (F ). The F is determined by BASE BASE 12.288 1 8 programming the following registers: 14.7456 3 20  Register 8: PLL1 N[7:0] divider.  Register 9: PLL1 M[7:0] divider. 18.4320 3 16 The main design consideration is the generation of a 24.5760 1 4 base frequency, defined as follows: 25.8048 21 80 F = -F---M-----C---L---K----------M---- = 98.304 MHz 44.2368 9 20 BASE N 46.0800 15 32 47.9232 39 80 56.0000 35 36 36 Rev. 1.06

Si3056 Si3018/19/10 5.25.2. PLL Lock Times for the required initial sample rate, typically 7200Hz. The Si3056 changes sample rates quickly. However, Rate changes are made by writing to SRC[3:0] lock time varies based on the programming of the clock (Register7, bits 3:0). generator. The following relationships describe the The final design consideration for the clock generator is boundaries on PLL locking time: the update rate of PLL1. The following criteria must be satisfied for the PLLs to remain stable: PLL1 lock time < 1ms PLL2 lock time 100s to 1ms For modem designs, Silicon Laboratories® F MCLK F = -------------------144kHz recommends that PLL1 be programmed during UP1 N initialization. No further programming of PLL1 is where F is shown in Figure26. UP1 necessary. The SRC[3:0] register can be programmed 1 SCLK MCLK FUP1 98.304 MHz 0 DIV PLL1 DIV 32.768 MHz DIV PLL2 DIV 8-bit 3 N2 16 8D-bIVit DMI2V Slave 0 1 0 1 N1 M1 Decoder Decoder SRATE Figure 26. Update Rate of PLL1 5.26. Digital Interface In serial mode 0 or 1, the Si3056 operates as a master, where the master clock (MCLK) is an input, the serial The Si3056 has two serial interface modes that support data clock (SCLK) is an output, and the frame sync most standard modem DSPs. The M0 and M1 mode signal (FSYNC) is an output. The MCLK frequency and pins select the interface mode. The key difference the value of the sample rate control registers 7, 8, and 9 between these two serial modes is the operation of the determine the sample rate (Fs). The serial port clock, FSYNC signal. Table21 summarizes the serial mode SCLK, runs at 256 bits per frame, where the frame rate definitions. is equivalent to the sample rate. See "5.25.Clock Generation" on page 36 for details on programming Table 21. Serial Modes sample rates. Mode M1 M0 Description The Si3056 transfers 16- or 15-bit telephony data in the primary timeslot and 16-bit control data in the secondary 0 0 0 FSYNC frames data timeslot. Figures 27 and 28 show the relative timing of the serial frames. Primary frames occur at the frame 1 0 1 FSYNC pulse starts data frame rate and are always present. To minimize overhead in the external DSP, secondary frames are present only 2 1 0 Slave mode when requested. 3 1 1 Reserved Two methods exist for requesting a secondary frame to transfer control information. The default powerup mode The digital interface consists of a single, synchronous uses the LSB of the 16-bit transmit (TX) data word as a serial link that communicates both telephony and flag to request a secondary transfer. Only 15-bit TX data control data. is transferred, which results in a small loss of SNR but Rev. 1.06 37

Si3056 Si3018/19/10 provides software control of the secondary frames. As frame communication must be requested via software in an alternative method, the FC pin can serve as a the LSB of the transmit (TX) data word. hardware flag for requesting a secondary frame. The Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be external DSP can turn on the 16-bit TX mode by setting supported on the serial bus. For each slave, the Si3056 the SB bit (Register1, bit 0). In the 16-bit TX mode, the generates an FSYNC to the DSP. In daisy-chain mode, hardware FC pin must be used to request secondary the polarity of the ring signal can be controlled by bit 1 transfers. (RPOL). When RPOL=1, the ring detect signal (now an Figures 29 and 30 illustrate the secondary frame read output on the FC/RGDT pin) is active high. cycle and write cycle, respectively. During a read cycle, The Si3056 supports a variety of codecs and additional the R/W bit is high and the 7-bit address field contains Si3056s. The type of slave codec(s) used is set by the the address of the register to be read. The contents of SSEL[1:0] bits (Register14, bits4:3) and determines the 8-bit control register are placed on the SDO signal. the type of signalling used in the LSB of SDO. This During a write cycle, the R/W bit is low and the 7-bit assists the host in isolating which data stream is the address field contains the address of the register to be master and which is the slave. If the LSB is used for written. The 8-bit data to be written immediately follows signalling, the master device has a unique setting the address on SDI. Only one register can be read or relative to the slave devices. The DSP can use this written during each secondary frame. See "6.Control information to determine which FSYNC marks the Registers" on page 48 for the register addresses and beginning of a sequence of data transfers. functions. The delayed frame sync (FSD) of each device is In serial mode 2, the Si3056 operates as a slave device, supplied as the FSYNC of each subsequent slave where MCLK is an input, SCLK is a no connect, and device in the daisy chain. The master Si3056 generates FSYNC is an input. In addition, the RGDT/FSD/M1 pin an FSYNC signal for each device every 16 or 32 SLCK operates as a delayed frame sync (FSD) and the FC/ periods. The delay period is set by FSD (Register14, RGDT pin operates as ring detect (RGDT). In this bit2). Figure31 on page 43 and Figure34 on page 46 mode, FC operation is not supported. For details on show the relative timing for daisy chaining operation. operating the Si3056 as a slave device, see Primary communication frames occur in sequence, “5.27.Multiple Device Support” . followed by secondary communication frames, if 5.27. Multiple Device Support requested. When writing/reading the master device via a secondary frame, all secondary frames of the slave The Si3056 supports the operation of up to seven devices also must be written. When writing/reading a additional devices on a single serial interface. Figure35 slave device via a secondary frame, the secondary shows the typical connection of the Si3056 and one frames of the master and all other slaves must be additional serial voice codec (Si3000). written also. “No operation” writes/reads to secondary The Si3056 must be the master in this configuration. frames are accomplished by writing/reading a 0 value to Configure the secondary codec as a slave device with address 0. the master’s SCLK used as the MCLK input to the If FSD is set for 16 SCLK periods between FSYNCs, codec, and the master’s frame sync delay signal (FSD) only serial mode 1 can be used. In addition, the slave used as the codec’s FSYNC input. On powerup, the devices must delay the tri-state to active transition of Si3056 master does not detect the additional codec on their SDO sufficiently from the rising edge of SCLK to the serial bus. The FC/RGDT pin is an input, operating avoid bus contention. as the hardware control for secondary frames, and the The Si3056 supports the operation of up to eight Si3056 RGDT/FSD/M1 pin is an output, operating as the active devices on a single serial bus. The master Si3056 must low ring detection signal. Program the master device for be configured in serial mode 1. Configure the slave(s) master/slave mode before enabling the isolation link, Si3056 in serial mode 2. Figure36 on page 47 shows a because a ring signal causes a false transition to the typical master/slave connection using three Si3056 slave device’s FSYNC. devices. Register14 provides the necessary control bits to When in serial mode 2, FSYNC becomes an input, configure the Si3056 for master/slave operation. Bit 0 RGDT/FSD/M1 becomes the delay frame sync output, (DCE) sets the Si3056 in master/slave mode, also and FC/RGDT becomes the ring detection output. The referred to as daisy-chain mode. When the DCE bit is serial interface runs at the MCLK input frequency fed set, the FC/RGDT pin becomes the ring detect output from a master device (such as a master Si3056's SCLK and the RGDT/FSD/M1 pin becomes the frame sync output). To achieve the proper sampling frequency, the delay output. When using multiple devices, secondary 38 Rev. 1.06

Si3056 Si3018/19/10 SRC[3:0] bits (Register 7, bits 3:0) must be The Si3056 also supports an additional powerdown programmed with the proper sample rate value before mode. When both the PDN (Register6, bit3) and PDL the sampled line data is valid. The SCLK pin of the (Register6, bit4) bits are set, the chipset enters a slave is a no connect in this configuration. complete powerdown mode and draws negligible The delay between FSYNC input and delayed frame current (deep sleep mode). Turn off the PLL2 before sync output (RGDT/FSD/M1) is 16 SCLK periods. The entering deep sleep mode (i.e., set Register9 to 0 and RGDT/FSD/M1 output has a waveform identical to the then Register6 to 0x18). In this mode, the Si3056 is FSYNC signal in serial mode 0. In addition, the LSB of non-functional. Normal operation is restored by the SDO is set to 0 by default for all devices in serial same process for taking the DAA out of sleep mode. mode2. 5.29. Calibration 5.28. Power Management The Si3056 initiates two auto-calibrations by default The Si3056 supports four basic power management when the device goes off-hook or experiences a loss in operation modes. The modes are normal operation, line power. A 17ms resistor calibration is performed to reset operation, sleep mode, and full powerdown mode. allow circuitry internal to the DAA to adjust to the exact PDN and PDL bits (Register6) control the power line conditions present at that time. This resistor management modes. calibration can be disabled by setting the RCALD bit (Register 25, bit5). A 256ms ADC calibration is also On powerup, or following a reset, the Si3056 is in reset performed to remove offsets that might be present in the operation. The PDL bit is set, and the PDN bit is on-chip A/D converter which could affect the A/D cleared. The Si3056 is operational, except for the dynamic range. The ADC auto-calibration is initiated isolation link. No communication between the Si3056 after the DAA dc termination stabilizes, and the resistor and line-side device can occur during reset operation. calibration completes. Because large variations in line Bits associated with the line-side device are not valid in conditions and line card behavior exist, it could be this mode. beneficial to use manual calibration instead of auto- In typical applications, the DAA will predominantly be calibration. operated in normal mode. In this mode, the PDL and Execute manual ADC calibration as close as possible to PDN bits are cleared. The Si3056 is operational and the 256ms before valid transmit/receive data is expected. isolation link is passing information between the Si3056 Take the following steps to implement manual ADC and the line-side device. calibration: The Si3056 supports a low-power sleep mode to 1. The CALD (auto-calibration disable—Register17) bit support ring validation and wake-on-ring features. The must be set to 1. clock generator registers 7, 8, and 9 must be programmed with valid, non-zero values and the PDL 2. The MCAL (manual calibration) bit must be toggled bit must be clear before enabling sleep mode. The PDN to 1 and then 0 to begin and complete the bit must then be set. When the Si3056 is in sleep mode calibration. the MCLK signal must remain active. In low-power 3. The calibration is completed in 256 ms. sleep mode with MCLK active, the Si3056 is non- 5.30. In-Circuit Testing functional except for the isolation link and the RGDT signal. To take the Si3056 out of sleep mode, pulse the With the Si3056’s advanced design the designer can reset pin (RESET) low. determine system functionality during production line In summary, the powerdown/up sequence for sleep tests, and during support for end-user diagnostics. Four mode is as follows: loopback modes allow thorough coverage of system 1. Ensure that Registers 7, 8, and 9 have valid non- components. Four of the test modes require a line-side zero values, and ensure the PDL bit (Register 6, bit power source. Although a standard phone line can be 4) is cleared. used, the test circuit in Figure1 on page 6 is adequate. In addition, an off-hook sequence must be performed to 2. Set the PDN bit (Register6, bit 3). connect the power source to the line-side device. 3. The device is now in sleep mode. MCLK must stay For the start-up loopback test mode, line-side power is active. not necessary and no off-hook sequence is required. 4. To exit sleep mode, reset the Si3056 by pulsing the The start-up test mode is enabled by default. When the RESET pin. PDL bit (Register6, bit4) is set (the default case), the 5. Program registers to desired settings. line-side is in a powerdown mode and the DSP-side is in a digital loop-back mode. Data received on SDI Rev. 1.06 39

Si3056 Si3018/19/10 passes through the internal filters and transmitted on When the HBE bit is cleared, this causes a dc offset that SDO which introduces approximately 0.9dB of affects the signal swing of the transmit signal. Silicon attenuation on the SDI signal received. The group delay Laboratories® recommends that the transmit signal be of both transmit and receive filters exists between SDI 12dB lower than normal transmit levels. A lower level and SDO. Clearing the PDL bit disables this mode and eliminates clipping from the dc offset that results from the SDO data is switched to the receive data from the disabling the hybrid. It is assumed in this test that the line-side. When the PDL bit is cleared, the FDT bit line ac impedance is nominally 600 (Register12, bit6) becomes active, indicating the Note: All test modes are mutually exclusive. If more than one successful communication between the line-side and test mode is enabled concurrently, the results are DSP-side. This can be used to verify that the isolation unpredictable. link is operational. 5.31. Exception Handling The digital data loop-back mode offers a way to input The Si3056 provides several mechanisms to determine data on the SDI pin and have the identical data be if an error occurs during operation. Through the output on the SDO pin by bypassing the transmit and secondary frames of the serial link, the controlling receive filters. Setting the DDL bit (Register 10, bit 0) systems can read several status bits. enables this mode. No line-side power or off-hook sequence is required for this mode. The digital data The bit of highest importance is the frame detect bit loopback mode is useful to verify communication (FDT, Register12, bit6), which indicates that the between the host processor/DSP and the DAA. system-side (Si3056) and line-side devices are communicating. The remaining test modes require an off-hook sequence to operate. The following sequence describes the off- During normal operation, the FDT bit can be checked hook procedure required for the following test modes: before reading bits for information about the line-side. If FDT is not set, the following bits related to the line-side 1. Powerup or reset. are invalid—RDT, RDTN, RDTP, LCS[4:0], LSID[1:0], 2. Program the clock generator to the chosen sample REVB[3:0], LCS2[7:0], LVS[7:0], ROV, BTD, DOD, and rate. OVL; the RGDT operation is also non-functional. 3. Enable line-side by clearing the PDL bit. Following Powerup and reset, the FDT bit is not set 4. Issue an off-hook command. because the PDL bit (Register6 bit4) defaults to 1. The 5. Delay 402.75ms to allow calibration to occur. communications link does not operate and no information about the line-side can be determined. The 6. Set the desired test mode. user must program the clock generator to a valid In the communications link loopback mode, the host configuration for the system and clear the PDL bit to sends a digital input test pattern on SDI and receives activate the communications link. As the system- and that digital test pattern back on SDO. To enable this line-side devices are establishing communication, the mode, set the IDL bit (Register1,bit1). In this mode, system-side device does not generate FSYNC signals. the communication link is tested. The digital stream is Establishing communication takes less than 10ms. delivered across the isolation capacitors, C1 and C2 of Therefore, if the controlling DSP serial interface is Figure16 on page 17, to the line-side device and interrupt driven based on the FSYNC signal, the returned across the same interface. In this mode, the controlling DSP does not require a special delay loop to 0.9dB attenuation and filter group delays also exist. wait for this event to complete. The final testing mode, internal analog loopback, allows The FDT bit also can indicate if the line-side device the system to test the operation of the transmit and executes an off-hook request successfully. If the line- receive paths through the line-side device and the side device is not connected to a phone line, the FDT bit external components shown in Figure16 on page 17. In remains cleared. The controlling DSP must provide this test mode, the host provides a digital test waveform sufficient time for the line-side to execute the off-hook on SDI. This data passes across the communications request. The maximum time for FDT to be valid link, is transmitted to and received from the line, passes following an off-hook request is 10ms. If the FDT bit is back across the communications link, and is presented high, the LCS[4:0] bits indicate the amount of loop to the host on SDO. To enable this mode, clear the HBE current flowing. If the FDT fails to be set following an off- bit (Register2, bit 1). hook request, the PDL bit (Register6) must be set high for at least 1ms to reset the line-side. 40 Rev. 1.06

Si3056 Si3018/19/10 5.32. Revision Identification With the Si3056 the system designer can determine the revision of the Si3056 and/or the line-side device. The REVA[3:0] bits (Register11, bits 3:0) identify the revision of the Si3056. The REVB[3:0] bits (Register13, bits 3:0) identify the revision of the line-side device. Table22 lists revision values for all devices and might contain future revisions not yet in existence. Table 22. Revision Values Revision Si3056 Si3018 Si3019 Si3010 A 0001 0001 0001 0001 B 0010 0010 0010 0010 C 0011 0011 0011 0011 D 0100 0100 0100 0100 E 0101 0101 0101 0101 F 0110 0110 0110 0110 Communications Frame 1 (CF1) (CF2) FSYNC Primary Secondary Primary FC 0 D15 –D1 D0 = 1 (Software FC Bit) D15 –D1 D0 = 0 (Software FC Bit) SDI XMT Data Secondary XMT Data Data SDO RCV Data Secondary RCV Data Data 16 SCLKS 128 SCLKS 256 SCLKS Figure 27. Software FC/RGDT Secondary Request Rev. 1.06 41

Si3056 Si3018/19/10 Communications Frame 1 (CF1) (CF2) FSYNC Primary Secondary Primary FC 0 D15–D0 SDI XMT Data Secondary XMT Data Data SDO RCV Data Secondary RCV Data Data 16 SCLKS 128 SCLKS 256 SCLKS Figure 28. Hardware FC/RGDT Secondary Request FSYNC (mode 0) FSYNC (mode 1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D0 SDI 1 A A A A A A A R/W D7 D6 D5 D4 D3 D2 D1 D0 SDO D D D D D D D D Figure 29. Secondary Communication Data Format—Read Cycle 42 Rev. 1.06

Si3056 Si3018/19/10 FSYNC (mode 0) FSYNC (mode 1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI 0 A A A A A A A D D D D D D D D R/W SDO Figure 30. Secondary Communication Data Format—Write Cycle Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary Frame (Data) Secondary Frame (Control) 128 SCLKs 128 SCLKs Master FSYNC 32 SCLKs 32 SCLKs Master FSD/ Slave1 FSYNC SDI [0] 1 1 Master Slave1 SDI [15..1] Master Slave1 Master Slave1 SDO [0] 1 0 Master Slave1 SDO[15..1] Master Slave1 Master Slave1 Comments Primary frames with secondary frame requested via SDI[0] = 1 Figure 31. Daisy Chaining of a Single Slave (Pulse FSD) Rev. 1.06 43

Si3056 Si3018/19/10 Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary Frame (Data) Secondary Frame (Control) 128 SCLKs 128 SCLKs Master FSYNC Master FSD/ 16 SCLKs 16 SCLKs 16 SCLKs 16 SCLKs Slave1 FSYNC SDI [0] 1 1 Master Slave1 SDI [15..1] Master Slave1 Master Slave1 SDO [0] 1 0 Master Slave1 SDO[15..1] Master Slave1 Master Slave1 Comments Primary frames with secondary frame requested via SDI[0] = 1 Figure 32. Daisy Chaining of a Single Slave (Frame FSD) 44 Rev. 1.06

Si3056 Si3018/19/10 ave7ave7 ave7ave7 SlSl SlSl ave6ave6 ave6ave6 SlSl SlSl ave5ave5 ave5ave5 ol) SlSl SlSl ntr o econdary Frame (C 128 SCLKs Slave3Slave4Slave3Slave4 Slave3Slave4Slave3Slave4 S ave2ave2 ave2ave2 As SlSl SlSl A D ave1ave1 ave1ave1 ht SlSl SlSl g i E asteraster asteraster of MM MM g n i n 1ave7 0ave7 ai Sl Sl h C 1Slave6 0Slave6 aisy D 1Slave5 0Slave5 33. e Serial Mode 1Reg 14: NSLV = 7, SSEL = 2, FSD = 1, DCE = 1 Serial Mode 2Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary Frame (Data) 128 SCLKs 16 SCLKs 11111Slave4Slave3Slave2Slave1Master 00001Slave4Slave3Slave2Slave1Master Primary frames with secondary frame requested via SDI[0] = 1 Figur Master Slave 1 MasterFSYNC Master FSD/Slave1 FSYNC Slave1 FSD/Slave2 FSYNC Slave2 FSD/Slave3 FSYNC Slave3 FSD/Slave4 FSYNC Slave4 FSD/Slave5 FSYNC Slave5 FSD/Slave6 FSYNC Slave6 FSD/Slave7 FSYNC SDI [0]SDI [15..1] SDO [0]SDO[15..1] Comments Rev. 1.06 45

Si3056 Si3018/19/10 Master Serial Mode 0 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary Frame (Data) Secondary Frame (Control) 128 SCLKs 128 SCLKs 16 SCLKs Master FSYNC Master FSD/ Slave1 FSYNC SDI [0] 1 1 Master Slave1 SDI [15..1] Master Slave1 Master Slave1 SD0 [0] 1 0 Master Slave1 SD0 [15..1] Master Slave1 Master Slave1 Comments Primary frames with secondary frame requested via SDI[0] = 1 Figure 34. Daisy Chaining with Framed FSYNC and Framed FSD MCLK Host Si3056 MCLK SCLK SCLK SDO SDI SDI SDO FSYNC FSYNC INT0 FC/RGDT VCC RGDT/FSD/M1 M0 47 k 47 k 47 k +5 V 47 k Si3000 SCLK MCLK FSYNC SDI SDO Voice Codec Figure 35. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem) 46 Rev. 1.06

Si3056 Si3018/19/10 MCLK Host Si3056—Master MCLK SCLK SCLK SDO SDI SDI SDO FSYNC FSYNC INTO FC/RGDT RGDT/FSD/M1 VCC M0 47 k 47 k 47 k Si3056—Slave 1 MCLK NC SCLK FSYNC SDI SDO VCC 47 k RGDT/FSD/M1 M0 Si3056—Slave 2 MCLK NC SCLK FSYNC SDI SDO VCC 47 k RGDT/FSD/M1 M0 Figure 36. Typical Connection for Multiple DAAS Rev. 1.06 47

Si3056 Si3018/19/10 6. Control Registers Table 23. Register Summary Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Control 1 SR PWMM[1:0] PWME IDL SB 2 Control 2 INTE INTP WDTEN RDI HBE RXE 3 Interrupt Mask RDTM ROVM FDTM BTDM DODM LCSOM DLCSM POLM 4 Interrupt Source RDTI ROVI FDTI BTDI DODI LCSOI DLCSI POLI 5 DAA Control 1 RDTN RDTP OPOL ONHM RDT OHE OH 6 DAA Control 2 PDL PDN 7 Sample Rate Control SRC[3:0] 8 PLL Divide N N[7:0] 9 PLL Divide M M[7:0] 10 DAA Control 3 DDL 11 System-Side and Line-Side Revision LSID[3:0] REVA[3:0] 12 Line-Side Device Status FDT LCS[4:0] 13 Line-Side Device Revision 0 REVB[3:0] 14 Serial Interface Control NSLV[2:0] SSEL[1:0] FSD RPOL DCE 15 TX/RX Gain Control 1 TXM ATX[2:0] RXM ARX[2:0] 16 International Control 1 ACT22 OHS ACT2 IIRE RZ RT 17 International Control 2 CALZ MCAL CALD OPE BTE ROV BTD 18 International Control 3 RFWE 19 International Control 4 OVL DOD OPD 20 Call Progress Rx Attenuation ARM[7:0] 21 Call Progress Tx Attenuation ATM[7:0] 22 Ring Validation Control 1 RDLY[1:0] RMX[5:0] 23 Ring Validation Control 2 RDLY[2] RTO[3:0] RCC[2:0] 24 Ring Validation Control 3 RNGV RAS[5:0] 25 Resistor Calibration RCALS RCALM RCALD RCAL[3:0] 26 DC Termination Control DCV[1:0] MINI[1:0] ILIM DCR 27 Reserved 28 Loop Current Status LCS2[7:0] 29 Line Voltage Status LVS[7:0] 30 AC Termination Control FULL21 ACIM[3:0]1 31 DAA Control 4 FULL1 FOH[1:0] OHS2 FILT1 LVFD1 32–37 Reserved 38 TX Gain Control 2 TGA21 TXG2[3:0]1 39 RX Gain Control 2 RGA21 RXG2[3:0]1 40 TX Gain Control 3 TGA31 TXG3[3:0]1 41 RX Gain Control 3 RGA31 RXG3[3:0]1 42 Reserved 43 Line Current/Voltage Threshold CVT[7:0]1 Interrupt 44 Line Current/Voltage Threshold CVI1 CVS1 CVM1 CVP1 Interrupt Control 45–52 Programmable Hybrid Register 1–8 HYB1–8[7:0] 53–58 Reserved 59 Spark Quenching Control TB3 SQ1 SQ0 RG1 GCE Notes: 1. Bit is available for Si3019 line-side device only. 2. Bit is available for Si3010 and Si3018 line-side device only. 48 Rev. 1.06

Si3056 Si3018/19/10 Register 1. Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name SR PWMM[1:0] PWME IDL SB Type R/W R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7 SR Software Reset. 0=Enables the DAA for normal operation. 1=Sets all registers to their reset value. Note: Bit automatically clears after being set. 6 Reserved Read returns zero. 5:4 PWMM[1:0] Pulse Width Modulation Mode. Used to select the type of signal output on the call progress AOUT pin. 00=PWM output is clocked at 16.384MHz as a delta-sigma data stream. A local density of 1s and 0s tracks the combined transmit and receive signals. 01=Balanced conventional PWM output signal has high and low portions of the modulated pulse that are centered on the 16kHz sample clock. 10=Conventional PWM output signal returns to logic 0 at regular 32kHz intervals and rises at a time in the 32kHz period proportional to its instantaneous amplitude. 11=Reserved. 3 PWME Pulse Width Modulation Enable. Sums the transmit and receive audio paths and presents it as a CMOS digital-level output of PWM data. Use the circuit in “Figure18.AOUT PWM Circuit for Call Progress” . 0=Pulse width modulation signal for AOUT disabled. 1=Pulse width modulation signal for call progress analog output (AOUT) enabled. 2 Reserved Read returns zero. 1 IDL Isolation Digital Loopback. 0=Digital loopback across the isolation barrier is disabled. 1=Enables digital loopback mode across the isolation barrier. The line-side device must be enabled and off hook before setting this mode. This data path includes the TX and RX filters. 0 SB Serial Digital Interface Mode. 0=Operation is in 15-bit mode, and the LSB of the data field indicates that a secondary frame is required. 1=The serial port is operating in 16-bit mode and requires a secondary frame sync signal, FC, to initiate control data reads/writes. Rev. 1.06 49

Si3056 Si3018/19/10 Register 2. Control 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name INTE INTP WDTEN RDI HBE RXE Type R/W R/W R/W R/W R/W R/W Reset settings=0000_0011 Bit Name Function 7 INTE Interrupt Pin Enable. 0=The AOUT/INT pin functions as an analog output for call progress monitoring purposes. 1=The AOUT/INT pin functions as a hardware interrupt pin. 6 INTP Interrupt Polarity Select. 0=The AOUT/INT pin, when used in hardware interrupt mode, is active low. 1=The AOUT/INT pin, when used in hardware interrupt mode, is active high. 5 Reserved Returns to zero. 4 WDTEN Watchdog Timer Enable. When set, this bit can only be cleared by a hardware reset. The watchdog timer monitors register accesses. If no register accesses occur within a 4second window, the DAA is put into an on-hook state. A write of a DAA register restarts the watchdog timer counter. If the watchdog timer times out, the OH and OHE bits are cleared, placing the DAA into an on-hook state. Setting the OH bit or setting the OHE bit and asserting the OFHK pin places the DAA back into an off-hook state. 0=Watchdog timer disabled. 1=Watchdog timer enabled. 3 Reserved Returns to zero. 2 RDI Ring Detect Interrupt Mode. This bit operates in conjunction with the RDTM and RDTI bits. This bit is selected if one or two interrupts are generated for every ring burst. 0=An interrupt is generated at the beginning of every ring burst. 1=An interrupt is generated at the beginning and end of every ring burst. The interrupt at the beginning of the ring burst must be serviced (by writing a 0 to the RDTI bit) before the end of the ring burst for both interrupts to occur. 1 HBE Hybrid Enable. 0=Disconnects hybrid in transmit path. 1=Connects hybrid in transmit path. 0 RXE Receive Enable. 0=Receive path disabled. 1=Enables receive path. 50 Rev. 1.06

Si3056 Si3018/19/10 Register 3. Interrupt Mask Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RDTM ROVM FDTM BTDM DODM LCSOM DLCSM POLM Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7 RDTM Ring Detect Mask. 0=A ring signal does not cause an interrupt on the AOUT/INT pin. 1=A ring signal causes an interrupt on the AOUT/INT pin. 6 ROVM Receive Overload Mask. 0=A receive overload does not cause an interrupt on the AOUT/INT pin. 1=A receive overload causes an interrupt on the AOUT/INT pin. 5 FDTM Frame Detect Mask. 0=The communications link achieving frame lock does not cause an interrupt on the AOUT/ INT pin. 1=The communications link achieving frame lock causes an interrupt on the AOUT/INT pin. 4 BTDM Billing Tone Detect Mask. 0=A detected billing tone does not cause an interrupt on the AOUT/INT pin. 1=A detected billing tone causes an interrupt on the AOUT/INT pin. 3 DODM Drop Out Detect Mask. 0=A line supply dropout does not cause an interrupt on the AOUT/INT pin. 1=A line supply dropout causes an interrupt on the AOUT/INT pin. 2 LCSOM Loop Current Sense Overload Mask. 0=An interrupt does not occur when the LCS bits are all 1s. 1=An interrupt occurs when the LCS bits are all 1s. 1 DLCSM Delta Loop Current Sense Mask. 0=An interrupt does not occur when the LCS bits change. 1=An interrupt does occur when the LCS bits change. 0 POLM Polarity Reversal Detect Mask. Generated from bit7 of the LVS register. When this bit transitions, it indicates that the polarity of TIP and RING was switched. 0=A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin. 1=A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin. Rev. 1.06 51

Si3056 Si3018/19/10 Register 4. Interrupt Source Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RDTI ROVI FDTI BTDI DODI LCSOI DLCSI POLI Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7 RDTI Ring Detect Interrupt. 0=A ring signal is not occurring. 1=A ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard- ware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. The RDI bit (Register2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a ring pulse as well. This bit should be cleared after clearing the PDL bit (Register6) because pow- ering up the line-side device may cause this interrupt to be triggered. 6 ROVI Receive Overload Interrupt. 0=An excessive input level on the receive pin is not occurring. 1=An excessive input level on the receive pin is detected. If the ROVM and INTE bits are set a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. This bit is identical in function to the ROV bit (Register 17). Clearing this bit also clears the ROV bit. 5 FDTI Frame Detect Interrupt. 0=Frame detect is established on the communications link. 1=This bit is set when the communications link does not have frame lock. If the FDTM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to a 0 to be cleared. 4 BTDI Billing Tone Detect Interrupt. 0=A billing tone has not occurred. 1=A billing tone has been detected. If the BTDM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. 3 DODI Drop Out Detect Interrupt. 0=The line-side power supply has not collapsed. 1=The line-side power supply has collapsed (The DOD bit in Register 19 has fired). If the DODM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared. This bit should be cleared after clearing the PDL bit (Register6) because powering as the line-side device can cause this interrupt to be triggered. 2 LCSOI Loop Current Sense Overload Interrupt. 0=The LCS bits have not reached max value (all ones). 1=The LCS bits have reached max value. If the LCSOM bit (Register3) and the INTE bit are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared. LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent sit- uation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI inter- rupt fires, the OPD bit should be checked to determine if an overcurrent situation exists. 52 Rev. 1.06

Si3056 Si3018/19/10 Bit Name Function 1 DLCSI Delta Loop Current Sense Interrupt 0=The LCS bits have not changed value. 1=The LCS bits have changed value; a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. 0 POLI Polarity Reversal Detect Interrupt. 0=Bit 7 of the LVS register does not change states. 1=Bit 7 of the LVS register changes from a 0 to a 1, or from a 1 to a 0, indicating the polarity of TIP and RING is switched. If the POLM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. To clear the interrupt, write this bit to 0. Register 5. DAA Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RDTN RDTP OPOL ONHM RDT OHE OH Type R R R/W R/W R R/W R/W Reset settings=0000_0000 Bit Name Function 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative. 0=No negative ring signal is occurring. 1=A negative ring signal is occurring. 5 RDTP Ring Detect Signal Positive. 0=No positive ring signal is occurring. 1=A positive ring signal is occurring. 4 OPOL Off-hook Polarity. 0=Off-hook pin is active low. 1=Off-hook pin is active high. 3 ONHM On-Hook Line Monitor. 0=Normal on-hook mode. 1=Enables low-power on-hook monitoring mode allowing the host to receive line activity without going off-hook. This mode is used for caller-ID detection. 2 RDT Ring Detect. 0=Reset either 5 seconds after last positive ring is detected or when the system executes an off-hook. Only a positive ring sets this bit when RFWE=0. When RFWE=1, either a positive or negative ring sets this bit. 1=Indicates a ring is occurring. 1 OHE Off-hook Pin Enable. 0=Off-hook pin is ignored. 1=Enables operation of the off-hook pin. 0 OH Off-Hook. 0=Line-side device on-hook. 1=Causes the line-side device to go off-hook. This bit operates independently of the OHE bit and is a logic OR with the off-hook pin when enabled. Rev. 1.06 53

Si3056 Si3018/19/10 Register 6. DAA Control 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PDL PDN Type R/W R/W Reset settings=0001_0000 Bit Name Function 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device. 0=Normal operation. Program the clock generator before clearing this bit. 1=Places the line-side device in lower power mode. 3 PDN Powerdown System-Side Device. 0=Normal operation. 1=Powers down the system-side device. A pulse on RESET is required to restore normal operation. 2:0 Reserved Read returns zero. Register 7. Sample Rate Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name SRC[3:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:4 Reserved Read returns zero. 3:0 SRC[3:0] Sample Rate Control. Sets the sample rate of the line-side device. 0000=7200Hz 0001=8000Hz 0010=8229Hz 0011=8400Hz 0100=9000Hz 0101=9600Hz 0110=10286Hz 0111=12000Hz 1000=13714Hz 1001=16000Hz 1010–1111=Reserved 54 Rev. 1.06

Si3056 Si3018/19/10 Register 8. PLL Divide N Bit D7 D6 D5 D4 D3 D2 D1 D0 Name N[7:0] Type R/W Reset settings=0000_0000 (serial mode 0, 1) Reset settings=0001_0011 (serial mode 2) Bit Name Function 7:0 N[7:0] PLL N Divider. Contains the (value –1) for determining the output frequency on PLL1. Register 9. PLL Divide M Bit D7 D6 D5 D4 D3 D2 D1 D0 Name M[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 M[7:0] PLL M Divider. Contains the (value –1) for determining the output frequency on PLL1. Register 10. DAA Control 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name DDL Type R/W Reset settings=0000_0000 Bit Name Function 7:1 Reserved Read returns zero. 0 DDL Digital Data Loopback. 0=Normal operation. 1=Audio data received on SDI and loops it back out to SDO before the TX and RX filters. Outputted data is identical to inputted data. Rev. 1.06 55

Si3056 Si3018/19/10 Register 11. System-Side and Line-Side Device Revision Bit D7 D6 D5 D4 D3 D2 D1 D0 Name LSID[3:0] REVA[3:0] Type R R Reset settings=xxxx_xxxx Bit Name Function 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on which line-side device is used. LSID[3:0] Si3018 0001 Si3019 0011 Si3010 0101 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the system-side device. Register 12. Line-Side Device Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FDT LCS[4:0] Type R R Reset settings=0000_0000 Bit Name Function 7 Reserved Read returns zero. 6 FDT Frame Detect. 0=Indicates the communications link has not established frame lock. 1=Indicates the communications link frame lock is established. 5 Reserved Read returns zero. 4:0 LCS[4:0] Loop Current Sense. 5-bit value returning the loop current when the DAA is in an off-hook state. 00000=Loop current is less than required for normal operation. 00100=Minimum loop current for normal operation. 11111=Loop current is >127mA, and a current overload condition may exist. 56 Rev. 1.06

Si3056 Si3018/19/10 Register 13. Line-Side Device Revision Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 0 REVB[3:0] Type R Reset settings=xxxx_xxxx Bit Name Function 7 Reserved Read returns zero. 6 0 This bit always reads a zero. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the revision of the line-side device. 1:0 Reserved Read returns zero. Rev. 1.06 57

Si3056 Si3018/19/10 Register 14. Serial Interface Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name NSLV[2:0] SSEL[1:0] FSD RPOL DCE Type R/W R/W R/W R/W R/W Reset settings=0000_0000 (serial mode 0,1) Reset settings=0011_1101 (serial mode 2) Bit Name Function 7:5 NSLV[2:0] Number of Slaves devices. 000=0 slaves. Redefines the FC/RGDT and RGDT/FSD pins. 001=1 slave device 010=2 slave devices 011=3 slave devices 100=4 slave devices (For four or more slave devices, the FSD bit MUST be set.) 101=5 slave devices 110=6 slave devices 111=7 slave devices 4:3 SSEL[1:0] Slave device select. 00=16-bit SDO receive data 01=Reserved 10=15-bit SDO receive data, LSB=1 11=15-bit SDO receive data, LSB=0 2 FSD Delayed Frame Sync Control. 0=Sets the number of SCLK periods between frame syncs to 32. 1=Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when Si3056 devices are slaves. For the master Si3056, only serial mode 1 is allowed when this bit is set. 1 RPOL Ring Detect Polarity. 0=The FC/RGDT pin (operating as ring detect) is active low. 1=The FC/RGDT pin (operating as ring detect) is active high. 0 DCE Daisy-Chain Enable. 0=Daisy-chaining disabled. 1=Enables the Si3056 to operate with slave devices on the same serial bus. The FC/RGDT signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the delayed frame sync signal. ALL other bits in this register are ignored if DCE=0. 58 Rev. 1.06

Si3056 Si3018/19/10 Register 15. TX/RX Gain Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name TXM ATX[2:0] RXM ARX[2:0] Type R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7 TXM Transmit Mute. 0=Transmit signal is not muted. 1=Mutes the transmit signal. 6:4 ATX[2:0] Analog Transmit Attenuation. 000=0dB attenuation 001=3dB attenuation 010=6dB attenuation 011=9dB attenuation 1xx = 12dB attenuation Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38–41 available only with the Si3019 line-side device. 3 RXM Receive Mute. 0=Receive signal is not muted. 1=Mutes the receive signal. 2:0 ARX[2:0] Analog Receive Gain. 000=0dB gain 001=3dB gain 010=6dB gain 011=9dB gain 1xx=12dB gain Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38–41 available only with the Si3019 line-side device. Rev. 1.06 59

Si3056 Si3018/19/10 Register 16. International Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ACT2 OHS ACT IIRE RZ RT Type RW R/W R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7 ACT2 AC Termination Select 2 (Si3018 line-side device only). Works with the ACT bit to select one of four ac terminations: ACT2 ACT AC Termination 0 0 Real, 600 0 1 Global complex impedance 1 0 Global complex impedance, except New Zealand 1 1 New Zealand complex impedance The global complex impedance meets minimum return loss requirements in countries that require a complex ac termination. For improved return loss performance, the other complex impedances can be used. 6 OHS On-Hook Speed. This bit, in combination with the OHS2 bit (Register31) and the SQ[1:0] bits (Register 59), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5ms 0 1 00 3ms ±10% (meets ETSI standard) 1 X 11 26ms ±10% (meets Australia spark quenching spec) 5 ACT AC Termination Select. (Si3018 line-side device only). When the ACT2 bit is cleared, the ACT bit selects the following: 0=Selects the real ac impedance (600 1=Selects the global complex impedance. 4 IIRE IIR Filter Enable. 0=FIR filter enabled for transmit and receive filters. See Figures 7–10 on page16. 1=IIR filter enabled for transmit and receive filters. See Figures 11–16 on page17. 3:2 Reserved Read returns zero. 1 RZ Ringer Impedance. 0=Maximum (high) ringer impedance. 1=Synthesized ringer impedance enabled. See "5.16.Ringer Impedance and Threshold" on page 30. 0 RT Ringer Threshold Select. This bit is used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. RT RT Lower level RT Upper level 0 13.5V 16.5V rms rms 1 19.35V 23.65V rms rms 60 Rev. 1.06

Si3056 Si3018/19/10 Register 17. International Control 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CALZ MCAL CALD OPE BTE ROV BTD Type R/W R/W R/W R/W R/W R/W R Reset settings=0000_0000 Bit Name Function 7 CALZ Clear ADC Calibration. 0=Normal operation. 1=Clears the existing calibration data. This bit must be written back to 0 after being set. 6 MCAL Manual ADC Calibration. 0=No calibration. 1=Initiate manual ADC calibration. 5 CALD ADC Auto-Calibration Disable. 0=Enable auto-calibration. 1=Disable auto-calibration. 4 Reserved Read returns zero. 3 OPE Overload Protect Enable. 0=Disabled. 1=Enabled. The OPE bit should always be cleared before going off-hook. 2 BTE Billing Tone Detect Enable. When set, the DAA can detect a billing tone signal on the line and maintain on off-hook state through the billing tone. If a billing tone is detected, the BTD bit (Register 17) is set to indicate the event. Writing this bit to zero clears the BTD bit. 0=Billing tone detection disabled. The BDT bit is not function. 1=Billing tone detection enabled. The BDT is functional. 1 ROV Receive Overload. This bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). Writing a zero to this location clears this bit and the ROVI bit (Register4, bit6). 0=Normal receive input level. 1=Excessive receive input level. 0 BTD Billing Tone Detected. This bit is set if a billing tone is detected. Writing a zero to BTE clears this bit. 0=No billing tone detected. 1=Billing tone detected. Rev. 1.06 61

Si3056 Si3018/19/10 Register 18. International Control 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RFWE Type R/W Reset settings=0000_0000 Bit Name Function 7:2 Reserved Read returns zero or one. 1 RFWE Ring Detector Full-Wave Rectifier Enable. When RNGV (Register24) is disabled, this bit controls the ring detector mode and the asser- tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter time- out of approximately five seconds. RNGV RFWE RGDT 0 0 Half-Wave 0 1 Full-Wave 1 0 Validated Ring Envelope 1 1 Ring Threshold Crossing One-Shot 0 Reserved Read returns zero or one. 62 Rev. 1.06

Si3056 Si3018/19/10 Register 19. International Control 4 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name OVL DOD OPD Type R R R Reset settings=0000_0000 Bit Name Function 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV in Register 17, but clears itself after the overload is removed. See “5.18.Billing Tone Protection and Receive Overload” on page31. This bit is only masked by the off-hook counter and is not affected by the BTE bit. 0=Normal receive input level. 1=Excessive receive input level. 1 DOD Recal/Dropout Detect. When the line-side device is off-hook, it is powered from the line itself. This bit will read 1 when loop current is not flowing. For example, if the line-derived power supply collapses, such as when the line is disconnected, this bit is set to 1. Additionally, when on-hook and the line- side device is enabled, this bit is set to 1. 0=Normal operation. 1=Line supply dropout detected when off-hook. 0 OPD Overload Protection Detect. This bit is used to indicate that the DAA has detected a loop current overload. The detector fir- ing threshold depends on the setting of the ILIM bit (Register26). OPD ILIM Overcurrent Threshold Overcurrent Status 0 0 160mA No overcurrent condition exists 0 1 60mA No overcurrent condition exists 1 0 160mA An overcurrent condition has been detected 1 1 60mA An overcurrent condition has been detected Rev. 1.06 63

Si3056 Si3018/19/10 Register20. Call Progress Receive Attenuation Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ARM[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT receive path. Attenuation=20log(ARM[7:0]/64) 1111_1111=+12dB (gain) 0111_1111=+6dB (gain) 0100_0000=0dB 0010_0000=–6dB (attenuation) 0001_0000=–12dB . . . 0000_0000=Mute Register21.Call Progress Transmit Attenuation Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ATM[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 ATM[7:0] AOUT Transmit Path Attenuation. When decremented from the default settings, these bits linearly attenuate the AOUT trans- mit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT transmit path. Attenuation=20 log(ATM[7:0]/64) 1111_1111=+12dB (gain) 0111_1111=+6dB (gain) 0100_0000=0dB 0010_0000=–6dB (attenuation) 0001_0000=–12dB . . . 0000_0000=Mute 64 Rev. 1.06

Si3056 Si3018/19/10 Register22.Ring Validation Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RDLY[1:0] RMX[5:0] Type R/W R/W Reset settings=1001_0110 Bit Name Function 7:6 RDLY[1:0] Ring Delay Bits 1 and 0. These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2] RDLY[1:0] Delay 0 00 0ms 0 01 256ms 0 10 512ms . . . 1 11 1792ms 5:0 RMX[5:0] Ring Assertion Maximum Count. These bits set the maximum ring frequency for a valid ring signal within a 10% margin of error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then the frequency of the ring is too high and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual- ify as a ring, in binary-coded increments of 2.0ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20Hz, TIP/RING events would occur every 1/ (2x20Hz)=25ms. To calculate the correct RMX[5:0] value for a frequency range [f_min, f_max], the following equation should be used: 1 RMX5:0RAS5:0 – ---------------------------------------------RMXRAS 2f_max2 ms To compensate for error margin and ensure a sufficient ring detection window, it is recom- mended that the calculated value of RMX[5:0] be incremented by 1. Rev. 1.06 65

Si3056 Si3018/19/10 Register23. Ring Validation Control 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RDLY[2] RTO[3:0] RCC[2:0] Type R/W R/W R/W Reset settings=0010_1101 Bit Name Function 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2] RDLY[1:0] Delay 0 00 0ms 0 01 256ms 0 10 512ms . . . 1 11 1792ms 6:3 RTO[3:0] Ring Timeout. These bits set when a ring signal is determined to be over after the most recent ring thresh- old crossing. RTO[3:0] Ring Timeout 0000 80ms 0001 128ms 0010 256ms . . . 1111 1920ms 2:0 RCC[2:0] Ring Confirmation Count. These bits set the amount of time that the ring frequency must be within the tolerances set by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal. RCC[2:0] Ring Confirmation Count Time 000 100ms 001 150ms 010 200ms 011 256ms 100 384ms 101 512ms 110 640ms 111 1024ms 66 Rev. 1.06

Si3056 Si3018/19/10 Register24.Ring Validation Control 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RNGV RAS[5:0] Type R/W R R/W Reset settings=0001_1001 Bit Name Function 7 RNGV Ring Validation Enable. 0=Ring validation feature is disabled. 1=Ring validation feature is enabled in both normal operating mode and low-power mode. 6 Reserved Reserved and may read either a 1 or 0. 5:0 RAS[5:0] Ring Assertion Time. These bits set the minimum ring frequency for a valid ring signal within a 10% margin of error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then the frequency of the ring is too high and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual- ify as a ring, in binary-coded increments of 2.0ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20Hz, TIP/RING events would occur every 1/ (2x20Hz)=25ms. To calculate the correct RMX[5:0] value for a frequency range [f_min, f_max], the following equation should be used: 1 RMX5:0RAS5:0 – -------------------------------------------RMXRAS 2f_min2 ms To compensate for error margin and ensure a sufficient ring detection window, it is recom- mended that the calculated value of RMX[5:0] be incremented by 1. Rev. 1.06 67

Si3056 Si3018/19/10 Register 25. Resistor Calibration Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RCALS RCALM RCALD RCAL[3:0] Type R R/W R/W R R/W Reset settings=xx0x_xxxx Bit Name Function 7 RCALS Resistor Auto Calibration. 0=Resistor calibration is not in progress. 1=Resistor calibration is in progress. 6 RCALM Manual Resistor Calibration. 0=No calibration. 1=Initiate manual resistor calibration. (After a manual calibration has been initiated, this bit must be cleared within 1ms.) 5 RCALD Resistor Calibration Disable. 0=Internal resistor calibration enabled. 1=Internal resistor calibration disabled. 4 Reserved Do not write to this register bit. This bit always reads a zero. 3:0 RCAL[3:0] Always write back the value read. 68 Rev. 1.06

Si3056 Si3018/19/10 Register 26. DC Termination Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name DCV[1:0] MINI[1:0] ILIM DCR Type R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7:6 DCV[1:0] TIP/RING Voltage Adjust. Adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING voltage on the line. Low voltage countries should use a lower TIP/RING voltage. Raising the TIP/ RING voltage improves signal headroom. DCV[1:0] DCT Pin Voltage 00 3.1V 01 3.2V 10 3.35V 11 3.5V 5:4 MINI[1:0] Minimum Operational Loop Current. Adjusts the minimum loop current so the DAA can operate. Increasing the minimum opera- tional loop current improves signal headroom at a lower TIP/RING voltage. MINI[1:0] Min Loop Current 00 10mA 01 12mA 10 14mA 11 16mA 3:2 Reserved Do not write to these register bits. 1 ILIM Current Limiting Enable. 0=Current limiting mode disabled. 1=Current limiting mode enabled. Limits loop current to a maximum of 60mA per the TBR21 standard. 0 DCR DC Impedance Selection. 0=50 dc termination is selected. Use this mode for all standard applications. 1=800 dc termination is selected. Rev. 1.06 69

Si3056 Si3018/19/10 Register 27. Reserved Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Type Reset settings=xxxx_xxxx Bit Name Function 7:0 Reserved Do not read or write. Register 28. Loop Current Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name LCS2[7:0] Type R Reset settings=0000_0000 Bit Name Function 7:0 LCS2[7:0] Loop Current Status. Eight-bit value returning the loop current. Each bit represents 1.1mA of loop current. 0000_0000=Loop current is less than required for normal operation. Register 29. Line Voltage Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name LVS[7:0] Type R Reset settings=0000_0000 Bit Name Function 7:0 LVS[7:0] Line Voltage Status. Eight-bit value returning the loop voltage. Each bit represents 1V of loop voltage. This regis- ter operates in on-hook and off-hook modes. Bit seven of this register indicates the polarity of the TIP/RING voltage. When this bit changes state, it indicates that a polarity reversal has occurred. The value returned is represented in 2s compliment format. 0000_0000=No line is connected. 70 Rev. 1.06

Si3056 Si3018/19/10 Register 30. AC Termination Control (Si3019 line-side device only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FULL2 ACIM[3:0] Type R/W R/W Reset settings=0000_0000 Bit Name Function 7:5 Reserved Read returns zero. 4 FULL2 Enhanced Full Scale (2X) Transmit and Receive Mode (Si3019 line-side Revision E or later). 0=Default 1=Transmit/Receive 2X Full Scale This bit changes the full scale of the ADC and DAC from 0min to +6dBm into 600 load (or 1.5dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26) should be set to all 1s to avoid distortion at low loop currents. 3:0 ACIM[3:0] AC Impedance Selection (Si3019 line-side device only). The off-hook ac termination is selected from the following: 0000=600 0001=900 0010=270 + (750|| 150nF) (TBR21) and 275 + (780 || 150nF) 0011=220 + (820|| 120nF) (Australia/New Zealand) and 220 + (820|| 115nF) (Slovakia/Slovenia/South Africa/Germany/Austria/Bulgaria) 0100=370 + (620 || 310nF) (New Zealand #2/India) 0101=320 + (1050 || 230nF) (England) 0110=370 + (820 || 110nF) 0111=275 + (780 || 115nF) 1000=120 + (820 || 110nF) 1001=350 + (1000 || 210nF) 1010=0 + (900 || 30nF) (line-side Revision C or earlier) 1010=200 + (680 || 100nF) (China) (line-side Revision E or later) 1011=600 + 2.16µF 1100=900 + 1µF 1101=900 + 2.16µF 1110=600 + 1µF 1111=Global impedance Rev. 1.06 71

Si3056 Si3018/19/10 Register 31. DAA Control 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FULL FOH[1:0] OHS2 FILT LVFD Type R/W R/W R/W R/W R/W Reset settings=0010_0000 Bit Name Function 7 FULL Full Scale Transmit and Receive Mode (Si3019 line-side device only). 0=Default. 1=Transmit/receive full scale. This bit changes the full scale of the ADC and DAC from 0 min to +3.2dBm into a 600 load (or 1dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26) should be set to all 1s to avoid distortion at low loop currents. 6:5 FOH[1:0] Fast Off-Hook Selection. These bits determine the length of the off-hook counter. The default setting is 128ms. 00=512ms. 01=128ms. 10=64ms. 11=8ms. 4 Reserved Read returns zero. 3 OHS2 On-Hook Speed 2. This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5ms 0 1 00 3ms ±10% (meets ETSI standard) 1 X 11 26ms ±10% (meets Australia spark quenching spec) 2 Reserved Read returns zero. 1 FILT Filter Pole Selection (Si3019 line-side device only). 0=The receive path has a low –3dBFS corner at 5Hz. 1=The receive path has a low –3dBFS corner at 200Hz. 0 LVFD Line Voltage Force Disable (Si3019 line-side device only). 0=Normal operation. 1=The circuitry that forces the LVS register (Register29) to all 0s at 3V or less is disabled. The LVS register may display unpredictable values at voltages between 0 to 2V. All 0s are displayed if the line voltage is 0V. 72 Rev. 1.06

Si3056 Si3018/19/10 Register 32-37.Reserved Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Type Reset settings=0000_0000 Bit Name Function 7:0 Reserved Read returns zero. Register38. TX Gain Control 2 (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name TGA2 TXG2[3:0] Type R/W R/W Reset settings=0000_0000 Bit Name Function 7:5 Reserved Read returns zero. 4 TGA2 Transmit Gain or Attenuation 2. 0=Incrementing the TXG2[3:0] bits results in gaining up the transmit path. 1=Incrementing the TXG2[3:0] bits results in attenuating the transmit path. 3:0 TXG2[3:0] Transmit Gain 2. Each bit increment represents 1dB of gain or attenuation, up to a maximum of +12dB and –15dB respectively. For example: TGA2 TXG2[3:0] Result X 0000 0dB gain or attenuation is applied to the transmit path. 0 0001 1dB gain is applied to the transmit path. 0 : 0 11xx 12dB gain is applied to the transmit path. 1 0001 1dB attenuation is applied to the transmit path. 1 : 1 1111 15dB attenuation is applied to the transmit path. Rev. 1.06 73

Si3056 Si3018/19/10 Register 39. RX Gain Control 2 (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RGA2 RXG2[3:0] Type R/W R/W Reset settings=0000_0000 Bit Name Function 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation 2. 0=Incrementing the RXG2[3:0] bits results in gaining up the receive path. 1=Incrementing the RXG2[3:0] bits results in attenuating the receive path. 3:0 RXG2[3:0] Receive Gain 2. Each bit increment represents 1dB of gain or attenuation, up to a maximum of +12dB and – 15dB respectively. For example: RGA2 RXG2[3:0] Result X 0000 0dB gain or attenuation is applied to the receive path. 0 0001 1dB gain is applied to the receive path. 0 : 0 11xx 12dB gain is applied to the receive path. 1 0001 1dB attenuation is applied to the receive path. 1 : 1 1111 15dB attenuation is applied to the receive path. 74 Rev. 1.06

Si3056 Si3018/19/10 Register 40. TX Gain Control 3 (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name TGA3 TXG3[3:0] Type R/W R/W Reset settings=0000_0000 Bit Name Function 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation 3. 0=Incrementing the TXG3[3:0] bits results in gaining up the transmit path. 1=Incrementing the TXG3[3:0] bits results in attenuating the transmit path. 3:0 TXG3[3:0] Transmit Gain 3. Each bit increment represents 0.1dB of gain or attenuation, up to a maximum of 1.5dB. For example: TGA3 TXG3[3:0] Result X 0000 0dB gain or attenuation is applied to the transmit path. 0 0001 0.1dB gain is applied to the transmit path. 0 : 0 1111 1.5dB gain is applied to the transmit path. 1 0001 0.1dB attenuation is applied to the transmit path. 1 : 1 1111 1.5dB attenuation is applied to the transmit path. Rev. 1.06 75

Si3056 Si3018/19/10 Register 41. RX Gain Control 3 (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RGA3 RXG3[3:0] Type R/W R/W Reset settings=0000_0000 Bit Name Function 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation 2. 0=Incrementing the RXG3[3:0] bits results in gaining up the receive path. 1=Incrementing the RXG3[3:0] bits results in attenuating the receive path. 3:0 RXG3[3:0] Receive Gain 3. Each bit increment represents 0.1dB of gain or attenuation, up to a maximum of 1.5dB. For example: RGA3 RXG3[3:0] Result X 0000 0dB gain or attenuation is applied to the receive path. 0 0001 0.1dB gain is applied to the receive path. 0 : 0 1111 1.5dB gain is applied to the receive path. 1 0001 0.1dB attenuation is applied to the receive path. 1 : 1 1111 1.5dB attenuation is applied to the receive path. Register 42. Reserved Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Type Reset settings=0000_0000 Bit Name Function 7:0 Reserved Read returns zero. 76 Rev. 1.06

Si3056 Si3018/19/10 Register 43. Line Current/Voltage Threshold Interrupt (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CVT[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 CVT[7:0] Current/Voltage Threshold. Determines the threshold at which an interrupt is generated from either the LCS or LVS regis- ter. Generate this interrupt to occur when the line current or line voltage rises above or drops below the value in the CVT[7:0] register. Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CVI CVS CVM CVP Type R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7:4 Reserved Read returns zero. 3 CVI Current/Voltage Interrupt. 0=The current / voltage threshold has not been crossed. 1=The current / voltage threshold is crossed. If the CVM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared. 2 CVS Current/Voltage Select. 0=The line current shown in the LCS2 register generates an interrupt. 1=The line voltage shown in the LVS register generates an interrupt. 1 CVM Current/Voltage Interrupt Mask. 0=The current / voltage threshold being triggered does not cause a hardware interrupt on the AOUT/INT pin. 1=The current / voltage threshold being triggered causes a hardware interrupt on the AOUT/ INT pin. 0 CVP Current/Voltage Interrupt Polarity. 0=The current / voltage threshold is triggered by the absolute value of the number in either the LCS2 or LVS register falling below the value in the CVT[7:0] register. 1=The current / voltage threshold is triggered by the absolute value of the number in the either the LCS2 or LVS register rising above the value in the CVT[7:0] Register. Rev. 1.06 77

Si3056 Si3018/19/10 Register 45. Programmable Hybrid Register 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB1 [7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the first tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Bal- ance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 46. Programmable Hybrid Register 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB2[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB2[7:0] Programmable Hybrid Register 2. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the second tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. 78 Rev. 1.06

Si3056 Si3018/19/10 Register 47. Programmable Hybrid Register 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB3[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the third tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 48. Programmable Hybrid Register 4 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB4[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB4[7:0] Programmable Hybrid Register 4. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fourth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Rev. 1.06 79

Si3056 Si3018/19/10 Register 49. Programmable Hybrid Register 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB5[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fifth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Bal- ance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 50. Programmable Hybrid Register 6 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB6[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB6[7:0] Programmable Hybrid Register 6. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the sixth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See"5.13.Transhybrid Bal- ance" on page 29 for more information on selecting coefficients for the programmable hybrid. 80 Rev. 1.06

Si3056 Si3018/19/10 Register 51. Programmable Hybrid Register 7 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB7[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the seventh tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 52. Programmable Hybrid Register 8 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB8[7:0] Type R/W Reset settings=0000_0000 Bit Name Function 7:0 HYB8[7:0] Programmable Hybrid Register 8. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the eighth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 53-58Reserved Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Type Reset settings=xxxx_xxxx Bit Name Function 7:0 Reserved Do not write to these register bits. Rev. 1.06 81

Si3056 Si3018/19/10 Register59.Spark Quenching Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name TB3 SQ1 SQ0 RG1 GCE Type R/W R/W R/W R/W R/W Reset settings=0000_0000 Bit Name Function 7 TB3 For South Korea PTT compliance, set this bit, in addition to the RZ bit, to synthesize a ringer impedance to meet South Korea ringer impedance requirements. This bit should only be set to meet South Korea PTT requirements and should only be set in conjunction with the RZ bit. 6 SQ1 Spark Quenching. This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5ms 0 1 00 3ms ±10% (meets ETSI standard) 1 X 11 26ms ±10% (meets Australia spark quenching spec) 5 Reserved Always write this bit to zero. 4 SQ0 Spark Quenching. This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5ms 0 1 00 3ms ±10% (meets ETSI standard) 1 X 11 26ms ±10% (meets Australia spark quenching spec) 3 Reserved Always write this bit to zero. 2 RG1 Receive Gain 1 (Line-side Revision E or later). This bit enables receive path gain adjustment. 0=No gain applied to hybrid, full scale RX on line=0dBm. 1=1dB of gain applied to hybrid, full scale RX on line=–1dBm. 1 GCE Guarded Clear Enable (Line-side Revision E or later). This bit (in conjunction with the RZ bit set to 1), enables the Si3056 to meet BT’s Guarded Clear Spec (B56450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw approximately 2.5mA of current from the line while on-hook. 0=default, DAA does not draw loop current. 1=Guarded Clear enabled, DAA draws 2.5mA while on-hook to meet Guarded Clear requirement. 0 Reserved Always write this bit to zero. 82 Rev. 1.06

Si3056 Si3018/19/10 7. Pin Descriptions: Si3056 MCLK 1 16 OFHK FSYNC 2 15 RGDT/FSD/M1 SCLK 3 14 M0 V 4 13 V D A SDO 5 12 GND SDI 6 11 AOUT/INT FC/RGDT 7 10 C1A RESET 8 9 C2A Table 24. Si3056 Pin Descriptions Pin # Pin Name Description 1 MCLK Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or modem/DSP. 2 FSYNC Frame Sync Output. Data framing signal that indicates the start and stop of a communication/data frame. 3 SCLK Serial Port Bit Clock Output. Controls the serial data on SDO and latches the data on SDI. 4 VD Digital Supply Voltage. Provides the 3.3V digital supply voltage to the Si3056. 5 SDO Serial Port Data Out. Serial communication data that is provided by the Si3056 to the modem/DSP. 6 SDI Serial Port Data In. Serial communication and control data that is generated by the modem/DSP and pre- sented as an input to the Si3056. 7 FC/RGDT Secondary Transfer Request Input/Ring Detect. An optional signal to instruct the Si3056 that control data is being requested in a sec- ondary frame. When daisy chain is enabled, this pin becomes the ring detect output. Produces an active low rectified version of the ring signal. 8 RESET Reset Input. An active low input that resets all control registers to a defined, initialized state. Also used to bring the Si3056 out of sleep mode. 9 C2A Isolation Capacitor 2A. Connects to one side of the isolation capacitor C2. Used to communicate with the line- side device. 10 C1A Isolation Capacitor 1A. Connects to one side of the isolation capacitor C1. Used to communicate with the line- side device. Rev. 1.06 83

Si3056 Si3018/19/10 Table 24. Si3056 Pin Descriptions (Continued) Pin # Pin Name Description 11 AOUT/INT Analog Speaker Out/Interrupt. Provides an analog output signal for driving a call progress speaker or a hardware interrupt for multiple sources of interrupts. 12 GND Ground. Connects to the system digital ground. 13 VA Analog Supply Voltage. Provides the analog supply voltage for the Si3056. 14 M0 Mode Select 0. The first of two mode select pins that selects the operation of the serial port/DSP inter- face. 15 RGDT/FSD/M1 Ring Detect/Delayed Frame Sync/Mode Select 1. Output signal that indicates the status of a ring signal. Produces an active low rectified version of the ring signal. When daisy chain is enabled, this signal becomes a delayed frame sync to drive a slave device. It is also the second of two mode select pins that selects the operation of the serial port/DSP interface when RESET is deasserted. 16 OFHK Off-Hook. An active low input control signal that provides a termination across TIP and RING for line seizing and pulse dialing, 84 Rev. 1.06

Si3056 Si3018/19/10 8. Pin Descriptions: Si3018/19/10 QE 1 16 DCT2 DCT 2 15 IGND RX 3 14 DCT3 IB 4 13 QB C1B 5 12 QE2 C2B 6 11 SC VREG 7 10 VREG2 RNG1 8 9 RNG2 Table 25. Si3018/19/10 Pin Descriptions Pin # Pin Name Description 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network. 3 RX Receive Input. Serves as the receive side input from the telephone network. 4 IB Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. Used to communicate with the system- side device. 5 C1B Internal Bias. Provides internal bias. 6 C2B Isolation Capacitor 2B. Connects to one side of the isolation capacitor C2. Used to communicate with the system-side device. 7 VREG Voltage Regulator. Connects to an external capacitor to provide bypassing for an internal power supply. 8 RNG1 Ring 1. Connects through a resistor to the RING lead of the telephone line. Provides the ring and caller ID signals to the system-side device. 9 RNG2 Ring 2. Connects through a resistor to the TIP lead of the telephone line. Provides the ring and caller ID signals to the system-side device. 10 VREG2 Voltage Regulator 2. Connects to an external capacitor to provide bypassing for an internal power supply. 11 SC Circuit Enable. Enables transistor network. Should be tied through a 0 resistor to I . GND 12 QE2 Transistor Emitter 2. Connects to the emitter of transistor Q4. Rev. 1.06 85

Si3056 Si3018/19/10 Table 25. Si3018/19/10 Pin Descriptions (Continued) Pin # Pin Name Description 13 QB Transistor Base. Connects to the base of transistor Q4. 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground on the line-side interface. 16 DCT2 DC Termination 2. Provides dc termination to the telephone network. 86 Rev. 1.06

Si3056 Si3018/19/10 1,2 9. Ordering Guide System Side Part Number Package Lead Free Temp Range Si3056-KS SOIC-16 No 0 to 70°C Si3056-X-FS SOIC-16 Yes 0 to 70°C Line Side Part Number Package Lead Free Temp Range Si3010-X-FS SOIC-16 Yes 0 to 70°C Si3018-X-FS SOIC-16 Yes 0 to 70°C Si3019-X-FS SOIC-16 Yes 0 to 70°C Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel. Rev. 1.06 87

Si3056 Si3018/19/10 10. Evaluation Board Ordering Guide Part Number Line-Side Platform Intended Use Includes Includes Device Platform DAA Board? Daughter Card? Si3056PPT-EVB Si3018 Parallel Port Direct Connection to a PC to use with included Windows®- Yes Yes Si3056PPT1-EVB Si3019 Parallel Port based SW program. (PPT) Si3056PPT2-EVB Si3010 Parallel Port Si3056SSI-EVB Si3018 Serial Interface with Buffer Direct Connection to processor or DSP (in customer application Yes (SSI) Yes Si3056SSI1-EVB Si3019 Serial Interface with Buffer or to another EVB). Si3056SSI2-EVB Si3010 Serial Interface with Buffer Si3056DC-EVB Si3018 Daughtercard Only Direct Connection to processor or DSP (in customer applica- No Yes Si3056DC1-EVB Si3019 Daughtercard Only tion). Si3056DC2-EVB Si3010 Daughtercard Only 88 Rev. 1.06

Si3056 Si3018/19/10 11. Package Outline: 16-Pin SOIC Figure37 illustrates the package details for the Si3056/18/19/10. Table26 lists the values for the dimensions shown in the illustration. 16 9 h E H bbb B -B-  1 8 B L aaa C A B Detail F -A- D -C- A C e A1 See Detail F Seating Plane  Figure37.16-pin Small Outline Integrated Circuit (SOIC) Package Table 26. Package Diagram Dimensions Millimeters Symbol Min Max A 1.35 1.75 A1 .10 .25 B .33 .51 C .19 .25 D 9.80 10.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h .25 .50 L .40 1.27  0.10  0º 8º aaa 0.25 bbb 0.25 Rev. 1.06 89

Si3056 Si3018/19/10 APPENDIX—UL1950 3RD EDITION Although designs using the Si3056 comply with the UL1950 3rd edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure38 shows two designs that can pass the UL1950 overvoltage tests and electromagnetic emissions. The top schematic shows the configuration in which the ferrite beads (FB1 and FB2) are on the unprotected side of the sidactor (RV1). For this configuration, the current rating of the ferrite beads needs to be 6A. However, the higher current ferrite beads are less effective in reducing electromagnetic emissions. The bottom schematic of Figure38 shows the configuration in which the ferrite beads (FB1 and FB2) are on the protected side of the sidactor (RV1). For this design, the ferrite beads can be rated at 200mA. In a cost-optimized design, compliance to UL1950 does not always require overvoltage tests. Plan ahead to know which overvoltage tests apply to the system. System-level elements in the construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. Consult with a professional testing agency during the design of the product to determine which tests apply to the system. C8 75 @ 100 MHz, 6 A 1.25 A FB1 TIP RV1 75 @ 100 MHz, 6 A FB2 RING C9 C8 600 at 100 MHz, 200 mA FB1 1.25 A TIP RV1 600 at 100 MHz, 200 mA FB2 RING C9 Figure 38. Circuits that Pass all UL1950 Overvoltage Tests 90 Rev. 1.06

Si3056 Si3018/19/10 SILICON LABORATORIES Si3056 SUPPORT DOCUMENTATION Refer to www.silabs.com for a current list of support documents for this chipset.  “AN13: Silicon DAA Software Guidelines”  “AN16: Multiple Device Support for the Si3034/35/44/56”  “AN17: Designing for International Safety Compliance”  “AN67: Si3050/52/54/56 Layout Guidelines”  “AN72: Ring Detection/Validation with the Si305x DAAs”  “AN84: Digital Hybrid with the Si305x DAAs”  Si30xxPPT-EVB Data Sheet  Si30xxSSI-EVB Data Sheet Rev. 1.06 91

Si3056 Si3018/19/10 DOCUMENT CHANGE LIST  Updated the following bit descriptions: R4.7 Revision 0.2 to Revision 0.71 R12.4–0 R14.2  Updated list of applications on cover page, including R17.4 ability to support V.92 modems. R20-21  Updated Transmit Full Scale Level test condition and R28 note in Table4 (AC Characteristics) for description of R29 VCID and DRCID. R31.0,3,7  Updated specifications in Table7, Table8, and R38–41 Table9 (Switching Characteristics) and Figure3,  Updated “Ordering Guide.” Figure4, and Figure5.  Added list of support documentation.  Updated “3.Bill of Materials” with revised values for C3, (10% to 20% tolerance relaxation on same value Revision 0.71 to Revision 1.0 cap) Q4-5 (voltage rating was misstated at 60V,  Added Si3010 to data sheet title, and to Line-Side changed to correct 80V value), R51-52 power rating device support functional description, and relaxed from 1/10W to 1/16W, and updated application circuit. recommended ferrite bead part numbers.  Updated Tables 2, 3, & 4 based on production test  Fixed several grammatical errors in functional results. descriptions, and globally replaced all instances of  Updated Table 4 with footnotes to explain expected CTR21 with TBR21. DR and THD when using the Si3056 with the Si3010  Added new functional description “5.1.Upgrading low-speed line-side device. from the Si3034/35/44 to Si3056” to describe new  Updated BOM. features and changes to consider when migrating to  Updated Country Specific Register Settings. the Si3056.  Updated the following functional descriptions:  Updated “Power Supplies” functional description to reflect 5V tolerance on Si3056 input pins. Line Voltage/Loop Current Sensing Interrupts  Updated “5.6.Transmit/Receive Full Scale Level DC Termination (Si3019 Line-Side Only)” functional description. Ring Detection  Updated“5.8.Line Voltage/Loop Current Sensing” Ring Validation functional description. Ringer Impedance and Threshold  Updated “5.15.Ring Validation” functional Caller ID description. Overload Detection  Updated “5.21.2.Type II Caller ID” functional Gain Control (added diagram) description. Power Management  Updated “5.23.Gain Control” functional description. Revision Identification  Updated “5.26.Digital Interface” functional  Updated Register Summary description and Figure29.  Updated the following Register Descriptions  Updated “Power Management” functional description Register 1 bit 1 to qualify description to qualify wake-on-ring support Register 3 bit 1 (added bit description) in low-power sleep mode. Register 4 bit 1 (added bit description)  Updated “5.30.In-Circuit Testing” functional Register 5 bit 2 description. Register 12 bits 4:0  Updated “5.6.Transmit/Receive Full Scale Level Register 13 bit 6 (Si3019 Line-Side Only)” functional description. Register 16 bit 0  Updated “5.8.1.Line Voltage Measurement” Register 18 bit 1 functional description. Register 19 bit 1  Updated “5.10.Interrupts” functional description. Register 24 bits 5:0  Updated “5.11.DC Termination” functional Register 31 bit 7 description.  Updated ordering guide  Updated “6.Control Registers” to reflect LVFD bit  Added Evaluation Board ordering guide available exclusively with the Si3019 line-side. 92 Rev. 1.06

Si3056 Si3018/19/10 Revision 1.0 to Revision 1.01  Updated "3.Bill of Materials" on page 19.  Removed “Confidential” watermark. Changed recommended case size of FB1, FB2. Revision 1.03 to Revision 1.05 Revision 1.01 to Revision 1.02  Updated voltage rating from 60 to 80V for Q4, Q5 in  Updated Table2, “Loop Characteristics,” on page6. bill of materials. This is the actual rating of the  Updated Table4, “AC Characteristics,” on page8 specified component. This change only corrects the  Updated "3.Bill of Materials" on page 19 typo in the data sheet. Added optional caller ID circuit components in  Updated Figure25 on page 35. footnotes.  Updated reset settings for R.59. Removed R14.  Added support for TB3 bit to meet South Korea  Updated Line Voltage/Loop Current Sensing ringer impedance requirements. functional description.  Updated Ordering Guide on page87.  Updated "9.Ordering Guide1,2" on page 87. Removed product selection and product identification  Updated "11.Package Outline: 16-Pin SOIC" on sections. page 89. Revision 1.05 to Revision 1.06  Updated Table26, “Package Diagram Dimensions,” on page89.  Updated "3.Bill of Materials" on page 19 with new diode information. Revision 1.02 to Revision 1.03  Updated Table4 on page8.  Updated Table6 on page10 to add MCLK jitter tolerance.  Added Table10 on page14.  Updated Table13 on page20.  Updated Table15 on page23. Changed recommended country settings for Australia, Austria, Bahrain, Bulgaria, China, Croatia, Cyprus, Czech Republic, Egypt, Germany, Hungary, Israel, India, Japan, Jordan, Kazakhstan, Latvia, Lebanon, Malyasia, Malta, Morocco, Nigeria, Oman, Pakistan, Philippines, Poland, Romania, Russia, Slovakia, Slovenia, South Africa, South Korea, Taiwan, Thailand.  Updated Table18 on page28 (changed act for ACIM = 1010).  Added Figure6 on page 14.  Updated "5.25.Clock Generation" on page 36.  Updated Table23, “Register Summary,” on page48.  Updated Table24, “Si3056 Pin Descriptions,” on page83.  Updated Figure19 on page 26.  Updated "5.6.Transmit/Receive Full Scale Level (Si3019 Line-Side Only)" on page 25 of Functional description to include new enhanced full scale mode.  The following bits have been added, but will only be supported with Si3018/19/10 Revision E or later line- side devices. Added FULL2 bit on p. 73. Added RG1 and GCE bits on p. 89.  Updated Table24 on page83.  Updated "9.Ordering Guide1,2" on page 87.  Update “12.Product Identification”. Rev. 1.06 93

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