Si2316DS Vishay Siliconix N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY • Halogen-free Option Available V (V) R (Ω) I (A) DS DS(on) D (cid:129) TrenchFET® Power MOSFET Pb-free 0.050 at VGS = 10 V 3.4 Available 30 0.085 at VGS = 4.5 V 2.6 APPLICATIONS RoHS* COMPLIANT (cid:129) Battery Switch TO-236 (SOT-23) G 1 3 D S 2 Top View Si2316DS (C6)* * Marking Code Ordering Information: Si2316DS-T1 Si2316DS-T1-E3 (Lead (Pb)-free) Si2316DS-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol 5 s Steady State Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a, b TTAA == 2750 °°CC ID 32..47 22..93 A Pulsed Drain Currentb IDM 16 Continuous Source Current (Diode Conduction)a, b IS 0.8 TA = 25 °C 0.96 0.7 Power Dissipationa, b PD W TA = 70 °C 0.6 0.45 Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit t ≤ 5 s 100 130 Maximum Junction-to-Ambienta RthJA Steady State 140 175 °C/W Maximum Junction-to-Foot (Drain) Steady State RthJF 60 75 Notes: a. Surface Mounted on 1" x 1" FR4 board. b. Pulse width limited by maximum junction temperature. * Pb containing terminations are not RoHS compliant, exemptions may apply. Document Number: 71798 www.vishay.com S-80642-Rev. C, 24-Mar-08 1

Si2316DS Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted A Limits Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 µA 30 V Gate-Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 0.8 Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA VDS = 30 V, VGS = 0 V 0.5 Zero Gate Voltage Drain Current IDSS µA VDS = 30 V, VGS = 0 V, TJ = 55 °C 10 VDS ≥ 4.5 V, VGS = 10 V 6 On-State Drain Currenta ID(on) A VDS ≥ 4.5 V, VGS = 4.5 V 4 VGS = 10 V, ID = 3.4 A 0.042 0.050 Drain-Source On-Resistancea RDS(on) Ω VGS = 4.5 V, ID = 2.6 A 0.068 0.085 Forward Transconductancea gfs VDS = 4.5 V, ID = 3.4 A 6.0 S Diode Forward Voltage VSD IS = 0.8 A, VGS = 0 V 0.8 1.2 V Dynamicb Total Gate Charge Qg 4.3 7 Gate-Source Charge Qgs VDS = 15 V, VGS = 10 V, ID = 3.4 A 0.65 nC Gate-Drain Charge Qgd 1.2 Input Capacitance Ciss 215 Output Capacitance Coss VDS = 15 V, VGS = 0 V, f = 1 MHz 90 pF Reverse Transfer Capacitance Crss 55 Switching Turn-On Delay Time td(on) 9 15 Rise Time tr VDD = 15 V, RL = 15 Ω 9 15 ns Turn-Off Delay Time td(off) ID ≅ 1.0 A, VGEN = 10 V, RG = 6 Ω 14 20 Fall Time tf 6 12 Notes: a. Pulse test; PW ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 16 16 VGS = 10 thru 5 V 14 14 12 12 A) 4 V A) nt ( 10 nt ( 10 e e urr urr C 8 C 8 n n ai ai Dr 6 Dr 6 - - D 3 V D I 4 I 4 TC = 125 °C 2 2 25 °C 2 V - 55 °C 0 0 0 2 4 6 8 10 0 1 2 3 4 5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics www.vishay.com Document Number: 71798 2 S-80642-Rev. C, 24-Mar-08

Si2316DS Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.5 350 300 )Ω 0.4 stance ( 0.3 e (pF) 250 Ciss On-Resi pacitanc 125000 - 0.2 Ca S(on) C - 100 Coss RD VGS = 4.5 V Crss 0.1 VGS = 10 V 50 0.0 0 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance 10 2.0 VDS = 15 V VGS = 10 V ID = 3.4 A ID = 3.4 A V) 8 age ( nce 1.5 Source Volt 6 On-Resista malized) 1.0 Gate-to- 4 - DS(on)(Nor - R 0.5 GS 2 V 0 0.0 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 30 0.5 10 )Ω 0.4 ent (A) TJ = 150 °C stance ( 0.3 ID = 3.4 A urr esi C R e n- Sourc 1 TJ = 25 °C - On) 0.2 - IS RDS(o 0.1 0.1 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Document Number: 71798 www.vishay.com S-80642-Rev. C, 24-Mar-08 3

Si2316DS Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.4 10 0.2 8 ID = 250 µA e (V) 0.0 Varianc -0.2 wer (W) 6 TA = 25 °C h) Po 4 S(t G -0.4 V 2 -0.6 -0.8 0 -50 -25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 600 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 2 1 nt Duty Cycle = 0.5 e ctive Transimpedance 0.2 Notes: zed Effehermal I 0.1 00..105 PDM maliT t1 Nor 0.02 1. Duty Cyclet,2 D = t1 t2 2. Per Unit Base = RthJA = 166°C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?71798. www.vishay.com Document Number: 71798 4 S-80642-Rev. C, 24-Mar-08

Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 E 1 2 e S e1 D 0.10 mm C A A2 0.004" C q 0.25 mm Gauge Plane Seating Plane Seating Plane A1 C L L1 MILLIMETERS INCHES Dim Min Max Min Max A 0.89 1.12 0.035 0.044 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 0.055 e 0.95 BSC 0.0374 Ref e1 1.90 BSC 0.0748 Ref L 0.40 0.60 0.016 0.024 L1 0.64 Ref 0.025 Ref S 0.50 Ref 0.020 Ref q 3° 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 www.vishay.com 09-Jul-01 1

AN807 Vishay Siliconix (cid:1) Mounting LITTLE FOOT SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated ambient air. This pattern uses all the available area underneath the circuit and small-signal packages which have been been modified body for this purpose. to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. 0.114 2.9 0.081 See Application Note 826, Recommended Minimum Pad 2.05 Patterns With Outline Drawing Access for Vishay Siliconix 0.150 3.8 MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET 0.059 footprint . In converting this footprint to the pad set for a power 1.5 device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.0394 0.037 1.0 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional Since surface-mounted packages are small, and reflow soldering function of providing the thermal connection from the package to is the most common way in which these are affixed to the PC the PC board. The total cross section of a copper trace connected board, “thermal” connections from the planar copper to the pads to the drain may be adequate to carry the current required for the have not been used. Even if additional planar copper area is used, application, but it may be inadequate thermally. Also, heat spreads there should be no problems in the soldering process. The actual in a circular fashion from the heat source. In this case the drain pin solder connections are defined by the solder mask openings. By is the heat source when looking at heat spread on the PC board. combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. Figure 1 shows the footprint with copper spreading for the SOT-23 A final item to keep in mind is the width of the power traces. The package. This pattern shows the starting point for utilizing the absolute minimum power trace width must be determined by the board area available for the heat spreading copper. To create this amount of current it has to carry. For thermal reasons, this pattern, a plane of copper overlies the drain pin and provides minimum width should be at least 0.020 inches. The use of wide planar copper to draw heat from the drain lead and start the traces connected to the drain plane provides a low-impedance process of spreading the heat so it can be dissipated into the path for heat to move away from the device. Document Number: 70739 www.vishay.com 26-Nov-03 1

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SOT-23 0.037 0.022 (0.950) (0.559) 6 2) 9 5) 0 9 4 4 1 6 0 2 0. 2. 0. 1. ( ( 9 4) 2 2 0 7 0. 0. ( 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index A P P L I C A T I O N N O T E Document Number: 72609 www.vishay.com Revision: 21-Jan-08 25

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