SC195 3.5MHz, 500mA Synchronous Step Down DC-DC Regulator POWER MANAGEMENT Features Description  Input Voltage — 2.9V to 5.5V The SC195 is a high efficiency, 500mA step down regula-  Output Voltage — 0.8V to 3.3V tor designed to operate with an input voltage range of  Output current capability — 500mA 2.9V to 5.5 V. The input voltage range makes it ideal for  Efficiency up to 94% battery operated applications with space limitations. The  15 Programmable output voltages SC195 also includes fifteen programmable output voltage  High light-load efficiency via automatic PSAVE mode settings that can be selected using the four control pins,  Fast transient response eliminating the need for external feedback resistors. The  Oscillator frequency — 3.5MHz output voltage can be fixed to a single setting or dynami-  100% duty cycle capability cally switched between different levels. Pulling all four  Quiescent current — 38µA typ control pins low disables the output.  Shutdown Current — 0.1µA typ  Internal soft-start The SC195 operates at a fixed 3.5MHz switching frequency  Over-voltage protection in normal PWM (Pulse-Width Modulation) mode. A vari-  Current limit and short circuit protection able frequency PSAVE (power-save) mode is used to  Over-temperature protection optimize efficiency at light loads for each output setting.  Under-voltage lockout Built-in hysteresis prevents chattering between the two  Floating control pin protection modes.  MLPQ-UT8 1.5 x 1.5 x 0.6 (mm) package  Pb free, halogen free, and RoHS/WEEE compliant The SC195 provides several protection features to safe- guard the device under stressed conditions. These Applications include short circuit protection, over-temperature protec- tion, under-voltage lockout, and soft-start to control  Smart phones and cellular phones in-rush current. These features, coupled with the small  MP3/Personal media players 1.5 x 1.5 x 0.6 (mm) package make the SC195 a versatile  Personal navigation devices device ideal for step-down regulation in products needing  Digital cameras high efficiency and a small PCB footprint.  Single Li-ion cell or 3 NiMH/NiCd cell devices  Devices with 3.3V or 5V internal power rails Typical Application Circuit SC195 VIN IN LX 2.9V to 5.5V 1.0µH CIN LX VOUT 4.7µF 0.8V to 3.3V OUT CTL3 C OUT 10µF CTL2 Control Logic GND Lines CTL1 CTL0 Rev 2.1 © 2015 Semtech Corporation 1

SC195 Pin Configuration Ordering Information Device Package CTL3 SC195ULTRT(1)(2) MLPQ-UT8 1.5 x 1.5 SC195EVB Evaluation Board 8 Notes: CTL2 1 7 IN (1) Available in tape and reel only. A reel contains 3,000 devices. TOP VIEW (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. CTL1 2 6 LX CTL0 3 5 GND 4 OUT MLPQ-UT8; 1.5 x 1.5, 8 LEAD θ = 116°C/W JA Table 1 – Output Voltage Settings CTL3 CTL2 CTL1 CTL0 Vout Marking Information 0 0 0 0 Shutdown 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.20 0 1 0 0 1.40 0 1 0 1 1.50 0J 0 1 1 0 1.60 0 1 1 1 1.80 yw 1 0 0 0 1.85 1 0 0 1 1.90 1 0 1 0 2.00 1 0 1 1 2.20 1 1 0 0 2.50 0J = SC195 1 1 0 1 2.80 yw = Date code 1 1 1 0 3.00 1 1 1 1 3.30 2

SC195 Absolute Maximum Ratings Recommended Operating Conditions IN (V) ...................................... -0.3 to +6.0 Input Voltage Range (V) ..................... +2.9 to +5.5 LX Voltage (V) ............................-1.0 to V +0.5 IN Other Pins (V) ............................-0.3 to V + 0.3 IN Output Short Circuit to GND ................ Continuous Thermal Information ESD Protection Level(1) (kV) .......................... 2.5 Thermal Resistance, Junction to Ambient(2) (°C/W) .... 116 Junction Temperature Range (°C) ........... -40 to +150 Storage Temperature Range (°C) ............ -65 to +150 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards. Electrical Characteristics Unless otherwise specified: V = 3.6V, C =4.7µF, C =10µF, L=1µH, V =1.8V, T =125°C, T= -40 to +85 °C. Typical values are T=+25 °C IN IN OUT X OUT J(MAX) A A Parameter Symbol Condition Min Typ Max Units Output Voltage Range V 0.8 3.3 (1) V OUT I = 200mA -2.0 2.0 OUT Output Voltage Tolerance V % OUT_TOL PSAVE mode 1.5 Line Regulation ΔV 2.9 ≤ V ≤ 5.5V, I = 200mA 0.3 %/V LINEREG IN OUT Load Regulation ΔV 200mA ≤ I ≤ 500mA -1 %/A LOADREG OUT Output Current Capability I 500 mA OUT Current Limit Threshold I 800 1300 mA LIMIT Foldback Current Limit I I > I 150 mA FB_LIM LOAD LIMIT Rising V 2.9 V IN Under-Voltage Lockout V UVLO Hysteresis 200 mV Quiescent Current I No switching, I = 0mA 38 60 µA Q OUT Shutdown Current I V = 0V 0.1 1.0 µA SD CTL 0-3 LX Leakage Current I Into LX pin 0.1 1.0 µA LX High Side Switch Resistance(2) R I = 100mA 250 DSON_P OUT mΩ Low Side Switch Resistance(3) R I = 100mA 350 DSON_N OUT 3

SC195 Electrical Characteristics (continued) Parameter Symbol Condition Min Typ Max Units Switching Frequency f 2.8 3.5 4.2 MHz SW Soft-Start t V = 90% of final value 100 500 µs SS OUT Thermal Shutdown T Rising temperature 160 °C OT Thermal Shutdown Hysteresis T 20 °C HYST Logic Inputs - CTL0, CTL1, CTL2, and CTL3 Input High Voltage V 1.2 V IH Input Low Voltage V 0.4 V IL Input High Current I V = V -2.0 5.0 µA IH CTL 0-3 IN Input Low Current I V = GND -2.0 2.0 µA IL CTL 0-3 Notes (1) Maximum output voltage is limited to VIN if the input is less than 3.3V. (2) Measured from IN to LX. (3) Measured from LX to GND. 4

SC195 Typical Characteristics V = 4.0V for V = 3.3V, V = 3.6V for all others. C = 4.7µF, C = 10µF, L = 1µH, T = 25°C unless otherwise noted. IN OUT IN IN OUT X A Efficiency vs. I (T = -40°C) Efficiency vs. V (T = -40°C) OUT A OUT A 100 100 IOUT = 200mA 90 3.3V 95 3.6V 80 2.8V 4.2V 1.8V 5.0V 70 90 Efficiency (%)456000 1V Efficiency (%) 8805 30 75 20 70 10 0 65 0.1 1 10 100 1000 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Load Current (mA) VOUT (V) Efficiency vs. I (T = 25°C) Efficiency vs. V (T = 25°C) OUT A OUT A 100 100 IOUT = 200mA 90 3.3V 95 3.6V 80 2.8V 4.2V 1.8V 5.0V 70 90 %)60 1V %) Efficiency (4500 Efficiency ( 8805 30 75 20 70 10 0 65 0.1 1 10 100 1000 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Load Current (mA) VOUT (V) Efficiency vs. I (T = 85°C) Efficiency vs. V (T = 85°C) OUT A OUT A 100 100 IOUT = 200mA 90 3.3V 95 80 2.8V 3.6V 4.2V 70 1.8V 90 5.0V %)60 1V %) Efficiency (5400 Efficiency (8805 30 75 20 70 10 0 65 0.1 1 10 100 1000 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Load Current (mA) VOUT (V) 5

SC195 Typical Characteristics (continued) V = 4.0V for V = 3.3V, V = 3.6V for all others. C = 4.7µF, C = 10µF, L = 1µH, T = 25°C unless otherwise noted. IN OUT IN IN OUT X A Frequency vs. Temperature Efficiency vs. V (V =1.8V) IN OUT 4 IOUT = 200mA 90 -40°C 89 3.8 1V 1.8V 3.3V 88 z) MH3.6 %) 87 uency ( 2.8V ciency ( 86 25°C Freq3.4 Effi 85 85°C 84 3.2 83 3 82 -40 -20 0 20 40 60 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Temperature (°C) VIN (V) Load Regulation (V = 1.8V) Line Regulation (V =1.8V) OUT OUT 1.86 1.86 IOUT = 200mA 1.84 1.84 V) e (1.82 1.82 put Voltag1.80 85°C V (V)OUT1.80 -40°C Out 25°C 2855°°CC -40°C 1.78 1.78 1.76 1.76 0 100 200 300 400 500 600 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Load Current (mA) VIN (V) 6

SC195 Typical Characteristics (continued) Light Load Switching — V = 1.0V Light Load Switching — V = 1.8V OUT OUT V (50mV/div) V (50mV/div) OUT OUT V (2V/div) LX V (2V/div) LX ILX (200mA/div) ILX (200mA/div) Time (400ns/div) Time (400ns/div) Light Load Switching — V = 2.8V Light Load Switching — V = 3.3V OUT OUT VOUT (50mV/div) VOUT (50mV/div) V (2V/div) V (2V/div) LX LX ILX (200mA/div) ILX (200mA/div) Time (400ns/div) Time (400ns/div) Heavy Load Switching — V = 1.0V Heavy Load Switching — V = 1.8V OUT OUT V (50mV/div) V (50mV/div) OUT OUT V (2.0V/div) V (2V/div) LX LX I (200mA/div) LX I (200mA/div) LX Time (200ns/div) Time (200ns/div) 7

SC195 Typical Characteristics (continued) Heavy Load Switching — V = 2.8V Heavy Load Switching — V = 3.3V OUT OUT V (50mV/div) V (50mV/div) OUT OUT V (2V/div) LX V (2V/div) LX I (200mA/div) LX I (200mA/div) LX Time (200ns/div) Time (200ns/div) Heavy Load Soft-start Light Load Soft-start I = 500mA I = 10mA LOAD LOAD I (200mA/div) IN I (200mA/div) IN V (1.0V/div) V (1.0V/div) OUT out I (500mA/div) I (500mA/div) LX LX Time (40μs/div) Time (40μs/div) Load Transient Response — 10 to 80mA Load Transient Response — 10 to 500mA V (50mV/div) OUT V (100mV/div) OUT I (200mA/div) LX I (500mA/div) LX ILOAD (50mA/div) ILOAD (500mA/div) Time (20μs/div) Time (20μs/div) 8

SC195 Typical Characteristics (continued) Load Transient Response — 200 to 500mA VID Transient Response — PWM 1.2V to 1.8V transition V (100mV/div) OUT V (500mV/div) OUT I (500mA/div) LX I (200mA/div) LX I (500mA/div) LOAD V (2.0V/div) CTL2 Time (20μs/div) Time (20μs/div) VID Transient Response — PSAVE Shutdown Transient Response 1.2V to 1.8V transition V (2V/div) OUT V (500mV/div) OUT I (200mA/div) LX I (200mA/div) LX V (2V/div) CTL3-0 V (2.0V/div) CTL2 Time (20μs/div) Time (20μs/div) Line Transient Response — PWM Line Transient Response — PSAVE 3.5V to 4.0V transition on V 3.5V to 4.0V transition on V IN IN V (100mV/div) OUT V (100mV/div) OUT I (200mA/div) LX I (200mA/div) LX V 500mV/div) V (500mV/div) IN IN Time (20μs/div) Time (40μs/div) 9

SC195 Pin Descriptions Pin Pin Name Pin Function Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at 1 CTL2 reset that is removed when CTL2 is pulled above the logic high threshold. Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at 2 CTL1 reset that is removed when CTL1 is pulled above the logic high threshold. Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at 3 CTL0 reset that is removed when CTL0 is pulled above the logic high threshold. Output voltage sense pin — output voltage regulation point (connection node of inductor and output 4 OUT capacitor). 5 GND Ground reference and power ground for the SC195. 6 LX Switching output — connect an inductor between this pin and the load to filter the pulsed output current. 7 IN Input power supply pin — connect a bypass capacitor from this pin to GND. Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at 8 CTL3 reset that is removed when CTL3 is pulled above the logic high threshold. 10

SC195 Block Diagram Plimit Amp 8 IN Current Amp OSC & Slope Generator Control 7 LX Logic PWM Comp 500mV Ref Error Amp PSAVE Comp Nlimit Amp 6 GND CTL3 4 CTL2 3 Voltage Select CTL1 2 CTL0 1 OUT 5 11

SC195 Applications Information General Description GND or IN. This option allows dynamic voltage adjust- The SC195 is a synchronous step-down Pulse Width ment for systems that reduce the supply voltage when Modulated (PWM) DC-DC regulator utilizing a 3.5MHz entering sleep states. Note that applying all zeros to the fixed-frequency voltage mode architecture. The device is CTL pins when changing the output voltages will tempo- designed to operate in fixed-frequency PWM mode and rarily disable the device, so it is important to avoid this enter power save (PSAVE) mode utilizing pulse frequency combination when dynamically changing levels. modulation under light load conditions to maximize effi- ciency. The device requires only two capacitors and a Adjustable Output Voltage Selection single inductor to be implemented in most systems. The If an output voltage other than one of the 15 program- switching frequency has been chosen to minimize the size mable settings is needed, an external resistor divider of the inductor and capacitors while maintaining high network can be added to the SC195 to adjust the output efficiency. The output voltage is programmable, eliminat- voltage setting. This network scales the output based on ing the need for external programming resistors. Loop the resistor ratio and the programmed output setting. compensation is also internal, eliminating the need for The resistor values can be determined using the equation external components to control stability. Programmable Output Voltage (cid:170)R (cid:14)R (cid:186) V (cid:32)V (cid:117)(cid:171) FB1 FB2(cid:187)(cid:14)I (cid:117)R The SC195 has 15 fixed output voltage levels which can be OUT SET (cid:172) R (cid:188) LEAK FB1 FB2 individually selected by programming the CTL control pins (CTL3-0 — see Table 1 on page 2 for settings). The where V is the desired output voltage, V is the voltage device is disabled whenever all four CTL pins are pulled OUT SET setting selected by the CTL pins, R is the resistor low and enabled whenever at least one of the CTL pins is FB1 between the output capacitor and the OUT pin, R is the pulled high. This configuration eliminates the need for a FB2 resistor between the OUT pin and ground, and I is the dedicated enable pin. Each CTL pin is internally pulled LEAK leakage current into the OUT pin during normal opera- down via 1MΩ if V is below 1.5V or if the voltage on the IN tion. The current into the OUT pin is typically 1µA, so the control pin is below the input high voltage. This ensures last term of the equation can be neglected if the current that the output is disabled when power is applied if there through R is much larger than 1µA. Selecting a resistor are no inputs to the CTL pins. Each weak pull-down is dis- FB2 value of 10kΩ or lower will simplify the design. If I is abled whenever its pin is pulled high and remains disabled LEAK neglected and R is fixed, R can be determined using until all CTL pins are pulled low. FB2 FB1 the equation The output voltage can be set using different approaches. V (cid:16)V R (cid:32)R (cid:117) OUT SET If a static output voltage is required, the CTL pins can be FB1 FB2 V SET tied to either IN or GND to set the desired voltage when- ever power is applied at IN. If enable control is required, Inserting resistance in the feedback loop will adversely each CTL pin can be tied to either GND or to a micropro- affect the system’s transient performance if feed-forward cessor I/O line to create the desired control code whenever capacitance is not included in the circuit. The circuit in the control signal is forced high. This approach is equiva- Figure 1 illustrates how the resistor divider and feed- lent to using the CTL pins collectively as a single enable forward capacitor can be added to the SC195 schematic. pin. A third option is to connect each of the four CTL pins The value of feed-forward capacitance needed can be to individual microprocessor I/O lines. Any of the 15 determined using the equation output voltages can be programmed using this approach. If only two output voltages are needed, the CTL pins can V (cid:11)V (cid:16)0.5(cid:12)2 C (cid:32) 4(cid:117)10(cid:16)6(cid:117) SET OUT be combined in a way that will reduce the number of I/O FF R (cid:11)V (cid:16)V (cid:12)(cid:11)V (cid:16)0.5(cid:12) FB1 OUT SET SET lines to 1, 2, or 3, depending on the control code for each desired voltage. Other CTL pins could be hard wired to 12

SC195 Applications Information (continued) increases as V decreases to maintain output voltage SC195 LX regulation. AsIN the input voltage approaches the pro- VIN IN LX VOUT CFF grammed output voltage, the duty cycle approaches CIN 100% (PMOS always on) and the device enters a pass- OUT CTL3 RFB1 COUT through mode until the input voltage increases or the RFB2 load decreases enough to allow PWM switching to CTL2 GND resume. Enable CTL1 CTL0 Power Save Mode Operation When the load current decreases below the PSAVE threshold, PWM switching stops and the device auto- Figure 1 — Application Circuit with External Resistors matically enters PSAVE mode. This threshold varies depending on the input voltage and output voltage To simplify the design, it is recommended to program the setting, optimizing efficiency for all possible load currents output setting to 1.0V, use resistor values smaller than in PWM or PSAVE mode. While in PSAVE mode, output 10kΩ, and include a feed-forward capacitance calculated voltage regulation is controlled by a series of switching with the equation above. If the output voltage is set to bursts. During a burst, the inductor current is limited to a 1.0V, the previous equation reduces to peak value which controls the on-time of the PMOS switch. After reaching this peak, the PMOS switch is dis- (cid:11)V (cid:16)0.5(cid:12)2 abled and the inductor current decreases to near 0mA. C (cid:32)8(cid:117)10(cid:16)6(cid:117) OUT FF R (cid:11)V (cid:16)1(cid:12) Switching bursts continue until the output voltage climbs FB1 OUT to V +2.5% or until the PSAVE current limit is reached. OUT Example: Switching is then stopped to eliminate switching losses, An output voltage of 1.3V is desired, but this is not a pro- enhancing overall efficiency. Switching resumes when grammable option. What external component values for the output voltage reaches the lower threshold of V OUT Figure 1 are needed? and continues until the upper threshold again is reached. Note that the output voltage is regulated hysteretically Solution: To keep the circuit simple, set R to 10kΩ so while in PSAVE mode between V and V + 2.5%. The FB2 OUT OUT current into the OUT pin can be neglected and set the period and duty cycle while in PSAVE mode are solely CTL3-0 pins to 0010 (1.0V setting). The necessary compo- determined by V and V until PWM mode resumes. This IN OUT nent values for this situation are can result in the switching frequency being much lower than the PWM mode frequency. V (cid:16)V R (cid:32)R (cid:117) OUT SET (cid:32)3k(cid:58) FB1 FB2 V If the output load current increases enough to cause V SET OUT to decrease below the PSAVE exit threshold (V -2%), OUT (cid:11)V (cid:16)0.5(cid:12)2 the device automatically exits PSAVE and operates in C (cid:32)8(cid:117)10(cid:16)6(cid:117) OUT (cid:32)5.69nF FF R (cid:11)V (cid:16)1(cid:12) continuous PWM mode. Note that the PSAVE high and FB1 OUT low threshold levels are both set at or above V to mini- OUT mize undershoot when the SC195 exits PSAVE. Figure 2 PWM Operation illustrates the transitions from PWM mode to PSAVE Normal PWM operation occurs when the output load mode and back to PWM mode. current exceeds the PSAVE threshold. In this mode, the PMOS high side switch is activated with the duty cycle required to produce the output voltage programmed by the CTL pins. An internal synchronous NMOS rectifier eliminates the need for an external Schottky diode on the LX pin. The duty cycle (percentage of time PMOS is active) 13

SC195 Applications Information (continued) disabled. Switching does not resume until V has fallen Load OUT below the regulation voltage by 2%. Demand (I ) OUT OFF Current Limit V +2.5% OUT The SC195 switching stage is protected by a current limit V OUT function. If the output load exceeds the PMOS current VOUT -2% limit for 32 consecutive switching cycles, the device enters BURST fold-back current limit mode and the output current is limited to approximately 150mA. Under these conditions, the output voltage will be the product of I and the load VLX FB-LIM PSAVE resistance. The load must fall below I for the device to EXIT FB-LIM exit fold-back current limit mode. This function makes the PWM Mode at PSAVE Mode at PWM Mode at device capable of sustaining an indefinite short circuit on Medium/High Light Load Medium/High its output under fault conditions. Load Load Time Thermal Shutdown Figure 2 — Transitions Between PWM and PSAVE Modes The SC195 has a thermal shutdown feature to protect the device if the junction temperature exceeds 160°C. During Protection Features thermal shutdown, the PMOS and NMOS switches are The SC195 provides the following protection features: both disabled, tri-stating the LX output. When the junc- tion temperature drops by the hysteresis value (20°C), the • Soft-Start Operation device goes through the soft-start process and resumes • Over-Voltage Protection normal operation. • Current Limit • Thermal Shutdown Under-Voltage Lockout • Under-Voltage Lockout Under-Voltage Lockout (UVLO) activates when the supply voltage drops below the UVLO threshold. This prevents Soft-Start the device from entering an ambiguous state in which The soft-start sequence is activated after a transition from regulation cannot be maintained. Hysteresis of approxi- an all zeros CTL code to a non-zero CTL code enables the mately 200mV is included to prevent chattering near the device. At start-up, the PMOS current limit is stepped threshold. through four levels: 25%, 40%, 60%, and 100%. Each step is maintained for 60μs following an internal reference start Inductor Selection up of 20μs, resulting in a total nominal start-up period of The SC195 is designed to operate with a 1µH inductor 260μs. If V reaches 90% of the target within the first 2 OUT between the LX pin and the OUT pin. Other values may steps, the device continues in PSAVE mode at the end of lead to instability, malfunction, or out-of-specification soft-start; otherwise, it goes into PWM mode. Note the performance. The specified current levels for PSAVE entry, V ripple in PSAVE mode can be larger than the ripple in OUT PSAVE exit, and current limit are dependent on the induc- PWM mode. tor value. Over-Voltage Protection The SC195 converter has internal loop compensation. The Over-voltage protection ensures the output voltage does compensation is designed to work with a specific single- not rise to a level that could damage its load. When V OUT exceeds the regulation voltage by 15%, the PWM drive is 14

SC195 Applications Information (continued) pole output filter corner frequency defined by the the ripple component of the inductor is a small percent- equation age of the DC load. AC losses in the inductor core and winding do not contribute significantly to the total (cid:20) losses. (cid:73) (cid:32) (cid:38) (cid:21)(cid:83) (cid:47)(cid:117)(cid:38) (cid:50)(cid:56)(cid:55) Magnetic fields associated with the output inductor can where L = 1μH and C = 10μF. OUT interfere with nearby circuitry. This can be minimized by the use of low-noise shielded inductors which use the When selecting output filter components, the LC product minimum gap possible to limit the distance that magnetic should not vary over a wide range. Selection of smaller fields can radiate from the inductor. Shielded inductors, inductor and capacitor values will move the corner fre- however, typically have a higher DCR and are, therefore, quency, potentially impacting system stability. DCR Rated L at Rated Dimensions less efficient than a similar sized non-shielded inductor. L Manufacturer/Part No. Max Current Current LxWxH (μH) (Ω) (A) (μH) (mm) It is also important to consider the change in inductance Final inductor selection depends on various design con- with DC bias current when choosing an inductor. The Murata 1±20% 0.13 1.5 0.78 2.5x2.0x1.2 siderations such as efficiency, EMI, size, and cost. Table 2 LQM2HPN1R0 inductor saturation current is specified as the current at lists the manufacturers of recommended inductor options. Murata 1±20% 0.07 1.7 0.78 3.0x3.0x1.5 which the inductance drops a specific percentage from LQH3NPN1R0 The inductors with larger packages tend to provide better the nominal value (approximately 30%). Except for short- Coilcraft overall efficiency, while the smaller package inductors 1±20% 0.036 1.9 0.8 4.8x4.8x1.5 LPO4815 circuit or other fault conditions, the peak current must provide decent efficiency with reduced footprint or height. Coilcraft 3.0x3.0x1.0 always be less than the saturation current specified by the LPS3010 1±20% 0.085 1.6 0.7 shielded The saturation current ratings and DC characteristics are manufacturer. The peak current is the maximum load also shown. FDK 1.5±30% 0.09 1.2 0.9 3.2x2.6x0.8 current plus one half of the inductor ripple current at the MIPWT3226D1R5 FDK maximum input voltage. Load and/or line transients can Table 2 — Recommended Inductors 1.5±30% 0.07 1.5 0.9 3.2x2.6x0.8 MIPF2520D1R5 cause the peak current to exceed this level for short dura- Tayo Yuden 1.5±20% 0.13 1 0.5 3.2x1.6x0.8 tions. Maintaining the peak current below the inductor Manufacturer L DCR Saturation L at Dimensions CKP32161R5M Current 400mA LxWxH saturation specification keeps the inductor ripple current Part Number (μH) (Ω) (mA) (μH) (mm) and the output voltage ripple at acceptable levels. Murata 1.0±20% 0.19 800 0.75 2.0x1.25x0.55 Manufacturers often provide graphs of actual inductance LQM21PN1R0MC0 and saturation characteristics versus applied inductor Murata 1.0±20% 0.09 1500 0.95 2.5x2.0x1.1 LQM2HPN1R0MJ0 current. The saturation characteristics of the inductor can Murata vary significantly with core temperature. Core and 1.0±20% 0.12 1200 0.95 3.2x1.6x0.85 LQM31PN1R0M00 ambient temperatures should be considered when exam- Taiyo Yuden ining the core saturation characteristics. CKP25201R0M-T 1.0±20% 0.08 800 0.88 2.5x2.0x1.0 Toko 1.0±30% 0.08 1350 1.00 2.0x1.25x1.0 When the inductor value has been determined, the DC MDT2012-CR1R0N resistance (DCR) must be examined. Efficiency can be FDK 1.0±30% 0.09 1100 1.00 2.0x1.25x1.0 MIPSZ2012D1R0 optimized by lowering the inductor’s DCR as much as pos- sible. Low DCR in an inductor requires either more surface FDK 1.0±30% 0.08 1300 0.78 2.5x2.0x0.5 MIPSU2520D1R0 area for the increased wire diameter or fewer turns to FDK reduce the length of the copper winding. Fewer turns 1.3±30% 0.09 1200 1.20 2.5x2.0x1.2 MIPSA2520D1R0 requires an inductor core with a larger cross-sectional area Taiyo Yuden 1.0±20% 0.18 850 0.90 1.6x0.8x0.8 in order to maintain the same saturation characteristics. BRC1608T1R0M The inductor size must always be considered when exam- ining the inductor DCR to determine the best compromise between DCR and component area on a PCB. Note that 15

SC195 Applications Information (continued) C Selection In this example, using a standard 10µF capacitor would be OUT The internal voltage loop compensation in the SC195 adequate to keep voltage droop less than the desired limits the minimum output capacitor value to 10μF. This limit. Note that if the voltage droop limit were decreased is due to its influence on the the loop crossover frequency, from 50mV to 25mV, the output capacitance would need phase margin, and gain margin. Increasing the output to be increased to at least 12µF (twice as much capaci- capacitor above this minimum value will reduce the cross- tance for half the droop). Capacitance will decrease from over frequency and provide greater phase margin. the nominal value when a ceramic capacitor is biased with a DC current, so it is important to select a capacitor whose The output capacitor determines the output voltage value exceeds the necessary capacitance value at the pro- ripple and contributes load current during large step load grammed output voltage. Check the manufacturer’s transitions. A capacitor between 10μF and 22μF will capacitance vs. DC voltage graphs when selecting an usually be adequate in stabilizing the output during large output capacitor to ensure the capacitance will be load transitions. adequate. Capacitors with X7R or X5R ceramic dielectric are recom- Table 3 lists the manufacturers of recommended output mended for their low ESR and superior temperature and capacitor options. voltage characteristics. Y5V capacitors should not be used Table 3 — Recommended Output Capacitors as their temperature coefficients make them unsuitable for this application. Manufacturer Value Rated Dimensions Type Voltage LxWxH (mm) In addition to ensuring stability, the output capacitor Part Nunber (μF) (VDC) Case Size serves other important functions. This capacitor deter- Murata 1.6x0.8x0.8 10±20% X5R 6.3 mines the output voltage ripple — as capacitance GRM188R60J106ME47D 0603 increases, ripple voltage decreases. It also supplies current Murata 2.0x1.25x1.25 10±10% X5R 6.3 GRM21BR60J106K 0805 during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). Taiyo Yuden 10±20% X5R 6.3 1.6x0.8x0.8 JMK107BJ106MA-T 0603 Once the loop responds, regulation is restored and the TDK 1.6x0.8x0.8 desired output is reached. During the period prior to PWM C1608X5R0J106MT 10±20% X5R 6.3 0603 operation resuming, the relationship between output voltage and output capacitance can be approximated C Selection IN using the equation The SC195 input source current will appear as a DC supply current with a triangular ripple imposed on it. To prevent 3(cid:117)(cid:39)I large input voltage ripple, a low ESR ceramic capacitor is C (cid:32) LOAD OUT V (cid:117)f required. A minimum value of 4.7μF should be used. It is DROOP important to consider the DC voltage coefficient charac- teristics when determining the actual required value. For This equation can be used to approximate the minimum example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC output capacitance needed to ensure voltage does not applied may exhibit a capacitance as low as 4.5μF. The droop below an acceptable level. For example, a load step value of required input capacitance is estimated by deter- from 50mA to 400mA requiring droop less than 50mV mining the acceptable input ripple voltage and calculating would require the minimum output capacitance to be the minimum value required for C using the equation IN COUT (cid:32) 0.053(cid:117)(cid:117)40.(cid:117)4106 (cid:32)6.0(cid:80)F VOUT (cid:168)(cid:168)(cid:167)1(cid:16) VOUT(cid:184)(cid:184)(cid:183) V (cid:169) V (cid:185) C (cid:32) IN IN IN (cid:167)(cid:39)V (cid:183) (cid:168)(cid:168) (cid:16)ESR(cid:184)(cid:184)f (cid:169)I (cid:185) OUT 16

SC195 Applications Information (continued) The input voltage ripple is at maximum level when the 2. Keep the LX pin traces as short as possible to minimize input voltage is twice the output voltage (50% duty cycle pickup of high frequency switching edges to other scenario). parts of the circuit. C and L should be connected OUT X as close as possible between the LX and GND pins, The input capacitor provides a low impedance loop for with a direct return to the GND. the edges of pulsed current drawn by the PMOS switch. 3. Use a ground plane referenced to the GND pin. Use Low ESR/ESL X5R ceramic capacitors are recommended several vias to connect to the component side ground for this function. To minimize stray inductance, the capaci- to further reduce noise and interference on sensitive tor should be placed as closely as possible to the IN and circuit nodes. GND pins of the SC195. Table 4 lists the recommended 4. Route the output voltage feedback/sense path away input capacitor options from different manufacturers. from the inductor and LX node to minimize noise and magnetic interference. Table 4 — Recommended Input Capacitors 5. Minimize the resistance from the OUT and GND pins to the load. This will reduce errors in DC regulation Manufacturer Value Rated Dimensions Type Voltage LxWxH (mm) due to voltage drops in the traces. Part Nunber (μF) (VDC) Case Size Murata 1.6x0.8x0.8 4.7±10% X5R 6.3 GRM188R60J475K 0603 4.8mm Murata 1.6x0.8x0.8 10±10% X5R 6.3 GRM188R60J106K 0603 Taiyo Yuden 1.6x0.8x0.8 4.7±10% X5R 6.3 JMK107BJ475KA 0603 CIN TDK 1.6x0.8x0.8 C1608X5R0J475KT 4.7±10% X5R 6.3 0603 LX CTL3 3mm CTL2 PCB Layout Considerations The layout diagram in Figure 3 shows a recommended CTL1 SC195 PCB top-layer for the SC195 and supporting components. CTL0 COUT Specified layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contrib- Figure 3 — Recommended PCB Layout ute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can result. The following guidelines are recommended for designing a PCB layout: 1. C should be placed as close to the IN and GND pins IN as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to minimize trace impedance. This will also minimize EMI and input voltage ripple by localizing the high frequency current pulses. 17

SC195 Outline Drawing — MLPQ-UT8 A D B DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A .020 - .024 0.50 - 0.60 A1 .000 - .002 0.00 - 0.05 A2 (.006) (0.1524) PIN 1 E b .006 .008 .010 0.15 0.20 0.25 INDICATOR (LASER MARK) D .059 BSC 1.50 BSC E .059 BSC 1.50 BSC e .016 BSC 0.40 BSC L 0.12 .014 0.16 0.30 0.35 0.40 N 8 8 aaa .004 0.10 bbb .004 0.10 A2 A SEATING aaa C PLANE C A1 LxN e 2 0.20 1 0.25 N bxN 0.17 bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 18

SC195 Land Pattern — MLPQ-UT8 Z DIMENSIONS G DIM INCHES MILLIMETERS C (.057) (1.45) G .028 0.70 P P .016 0.40 2X (C) (G) (Z) R .004 0.10 X .008 0.20 Y .030 0.75 X Z .087 2.20 R Y NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 19

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