Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 TMS570LS Series 16/32-BIT RISC Flash Microcontroller 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller 1.1 Features 1 • High-PerformanceAutomotiveGrade • CommunicationInterfaces MicrocontrollerforSafetyCriticalApplications – ThreeMulti-bufferedSerialPeripheralInterface – DualCPUsrunninginLockstep (MibSPI)eachwith: – ECConFlashandSRAM – FourChipSelectsandoneEnablepin – CPUandMemoryBIST(Built-InSelfTest) – 128bufferswithparity – ErrorSignalingModule(ESM)w/ErrorPin – Onewithparallelmode • ARM®Cortex™-R4F32-BitRISCCPU – TwoUART(SCI)interfaceswithLocal – Efficient1.6DMIPS/MHzwith8-stagepipeline InterconnectNetworkInterface(LIN2.0) – FloatingPointUnitwithSingle/DoublePrecision – ThreeCAN(DCAN)Controller – MemoryProtectionUnit(MPU) – Twowith64mailboxes,onewith32 – OpenArchitectureWithThird-PartySupport – ParityonmailboxRAM • OperatingFeatures – DualChannelFlexRay™Controller – Upto160-MHzSystemClock – 8K-BytemessageRAMwithparity – CoreSupplyVoltage(V ):1.5V – TransferUnitwithMPUandparity CC – I/OSupplyVoltage(V ):3.3V • High-EndTimer(NHET) CCIO • IntegratedMemory – 32ProgrammableI/OChannels – 1M-Byteor2M-ByteFlashwithECC – 128WordsHigh-EndTimerRAMwithparity – 128K-Byteor160K-ByteRAMwithECC – TransferUnitwithMPUandparity • MultipleCommunicationinterfacesincluding • Two12-BitMulti-BufferedADCs(MibADC) FlexRay,CAN,andLIN – 24totalADCInputchannels • NHETTimerand2x12-bitADCs – Eachhas64Bufferswithparity • ExternalMemoryInterface(EMIF) • TraceandCalibrationInterfaces – 16bitData,22bitAddress,4ChipSelects – EmbeddedTraceModule(ETMR4) • CommonTMS470/570PlatformArchitecture – DataModificationModule(DMM) – ConsistentMemoryMapacrossthefamily – RAMTracePort(RTP) – Real-TimeInterrupt(RTI)OSTimer – ParameterOverlayModule(POM) – VectoredInterruptModule(VIM) • On-ChipemulationlogicincludingIEEE1149.1 – CyclicRedundancyChecker(CRC,2Channels) JTAG,BoundaryScanandARMCoresight components • DirectMemoryAccess(DMA)Controller • FullDevelopmentKitAvailable – 32DMArequestsand16Channels/Control Packets – DevelopmentBoards – ParityonControlPacketMemory – CodeComposerStudioIntegratedDevelopment Environment(IDE) – DedicatedMemoryProtectionUnit(MPU) – HaLCoGenCodeGenerationTool • Frequency-ModulatedZero-PinPhase-Locked Loop(FMzPLL)-BasedClockModule – HETAssemblerandSimulator – OscillatorandPLLclockmonitor – nowFlashFlashProgrammingTool • Upto115PeripheralIOpins • PackagesSupported – 16DedicatedGIO-8w/ExternalInterrupts – 144-PinQuadFlatPack(PGE)[Green] – ProgrammableExternalClock(ECLK) – 337-PinBallGridArray(ZWT)[Green] • CommunityResources – TIE2E™OnlineCommunity 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 1.2 Description The TMS570LS series is a high performance automotive grade microcontroller family. The safety architecture includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash and the data SRAM, parity on peripheral memories, and loop back capability on peripheral IOs. TheTMS570LSfamilyintegratestheARM® Cortex™-R4FFloatingPointCPUwhichoffersanefficient1.6 DMIPS/MHz, and has configurations which can run up to 160 MHz providing more than 250 DMIPS. The TMS570LS series also provides different Flash (1MB or 2MB) and data SRAM (128KB or 160KB) options withsinglebiterrorcorrectionanddoublebiterrordetection. The TMS570LS devices feature peripherals for real-time control-based applications, including up to 32 nHET timer channels and two 12-bit A to D converters supporting up to 24 inputs. There are multiple communication interfaces including a 2-channel FlexRay, 3 CAN controllers supporting 64 mailboxes each,and2LIN/UARTcontrollers. With integrated safety features and a wide choice of communication and control peripherals, the TMS570LSseriesisanidealsolutionforhighperformancerealtimecontrolapplicationswithsafetycritical requirements. ThedevicesincludedintheTMS570LSseriesanddescribedinthisdocumentare: • TMS570LS20216 • TMS570LS20206 • TMS570LS10216 • TMS570LS10206 • TMS570LS10116 • TMS570LS10106 TheTMS570LSseriesmicrocontrollerscontainthefollowing: • DualTMS57016/32-BitRISC(ARMCortex™-R4F)inLockstep • Upto2M-ByteProgramFlashwithECC • Upto160K-ByteStaticRAM(SRAM)withECC • Real-TimeInterrupt(RTI)OperatingSystemTimer • VectoredInterruptModule(VIM) • CyclicRedundancyChecker(CRC)withParallelSignatureAnalysis(PSA) • DirectMemoryAccess(DMA)Controller • Frequency-ModulatedPhase-LockedLoop(FMzPLL)-BasedClockModuleWithPrescaler • ThreeMulti-bufferedSerialPeripheralInterfaces(MibSPI) • TwoUARTs(SCI)withLocalInterconnectNetworkInterfaces(LIN) • ThreeCANControllers(DCAN) • High-EndTimer(NHET)withdedicatedTransferUnit(HTU) • AvailableFlexRayControllerwithdedicatedPLLandTransferUnit(FTU) • ExternalClockPrescale(ECP)Module • Two16-Channel12-BitMulti-BufferedADCs(MibADC)-8sharedchannelsbetweenthetwoADCs • AddressBusParitywithFailureDetection • ErrorSignalingModule(ESM)withexternalerrorpin • VoltageMonitor(VMON)withoutofrangeresetassertion • EmbeddedTraceModule(ETMR4) • DataModificationModule(DMM) • RAMTracePort(RTP) • ParameterOverlayModule(POM) 2 TMS570LSSeries16/32-BITRISCFlashMicrocontroller Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 • 16DedicatedGeneral-PurposeI/O(GIO)PinsforZWT;8DedicatedGIOPinsforPGE • 115TotalPeripheralI/OsforZWT;68TotalPeripheralI/OsforPGE • 16-BitExternalMemoryInterface(EMIF) The devices utilize the big-endian format where the most significant byte of a word is stored at the lowest numberedbyteandtheleastsignificantbyteatthehighestnumberedbyte. The device memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, halfword, and word modes. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline mode,theflashoperateswithasystemclockfrequencyofupto160MHz. The device has nine communication interfaces: three MibSPIs, two LIN/SCIs, three DCANs and one FlexRay™ controller (optional). The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The FlexRay uses a dual channel serial, fixed time base multimaster communication protocol with communication rates of 10 megabits per second (Mbps) per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from main CPU memory. Transfers are protectedbyadedicated,built-inMemoryProtectionUnit(MPU). The NHET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The NHET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer Transfer Unit (HET-TU) provides features to transfer NHET data to or from main memory. A Memory ProtectionUnit(MPU)isbuiltintotheHET-TUtoprotectagainsterroneoustransfers. The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Eight channels are shared between the two ADCs. There are three separate groupings, two of which are triggerable by an external event. Each sequence can be converted oncewhentriggeredorconfiguredforcontinuousconversionmode. The frequency-modulated phase-locked loop (FMzPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides one of the six possible clock source inputs to the global clock module (GCM). The GCM module provides system clock (HCLK), real-time interrupt clock (RTICLK1), CPU clock (GCLK), NHET clock (VCLK2), DCAN clock (AVCLK1),andperipheralinterfaceclock(VCLK)toallotherperipheralmodules. The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral interfaceclock(VCLK)frequency. The Direct Memory Access Controller (DMA) has 32 DMA requests, 16 Channels/ Control Packets and parity protection on its memory. The DMA provides memory to memory transfer capabilities without CPU interaction. A Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous transfers. The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or externalErrorpinistriggeredwhenafaultisdetected. Copyright©2010–2018,TexasInstrumentsIncorporated TMS570LSSeries16/32-BITRISCFlashMicrocontroller 3 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com The External Memory Interface (EMIF) provides a memory extension to asynchronous memories or other slavedevices. Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built in ARM Cortex™-R4F CoreSight™ debug features, an External Trace Macrocell (ETM) providesinstructionanddatatraceofprogramexecution.Forinstrumentationpurposes,aRAMTracePort Module (RTP) is implemented to support high-speed output of RAM accesses by the CPU or any other master. A Direct Memory Module (DMM) gives the ability to write external data into the device memory. BoththeRTPandDMMhavenooronlyminimumimpactontheprogramexecutiontimeoftheapplication code. A Parameter Overlay Module (POM) can re-route Flash accesses to the EMIF, thus avoiding the re- programmingstepsnecessaryforparameterupdatesinFlash. 4 TMS570LSSeries16/32-BITRISCFlashMicrocontroller Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 1.3 Functional Block Diagram ETMDATA[31:0] TRST ETMTRACECTL ETM DAP TMS TCK CCM-R4 ETMTRACECLKOUT with RTCK ETMTRACECLKIN ICEPick TDI RAM TDO LIN1RX Flash P Cortex-R4F 160kB LIN1 LIN1TX FVLCTCPP11 2.0MB O withMPU withECC LIN2 LLIINN22RTXX FLTP2 withECC M Cortex-R4F FlexRay FRAYRX1 STC FRAYTX1 withMPU 8kByte FRAYTXEN1 LBIST 32Regions MsgRAM FRAYRX2 FRAYTX2 withParity FRAYTXEN2 DMA NHET DMMENA DMMSYNC 16Channels FlexRay HET TU 128Words NHET[31:0] DMMCLK DMM 1Port TU 8DCP withParity DMMDATA[1:0] withParity withMPU withMPU DMMDATA[15:2]* withMPU withParity withParity RST SYS PORRST SCR SCR TEST 1 2 ECLK ERROR ESM MiBSPI1 MIBSPI1SIMO Primary SCR 8Transfer MIBSPI1SOMI Groups MIBSPI1CLK 128Buffers MIBSPI1SCS[3:0] withParity MIBSPI1ENA EMIFDQM[1:0] EMIFDATA[15:0] MiBSPI3 MIBSPI3SIMO EMIFADD[21:0] SCR CRC Periph Bridge 8Transfer MIBSPI3SOMI EMIFBADD[1:0] EMIF 2Channel 12G8rBouupffsers MIBSPI3CLK EMIFCS[3:0] withParity MIBSPI3SCS[3:0] EMIFWE PCR MIBSPI3ENA EMIFOE MiBSPIP5 MIBSPI5SIMO[3:0]* MIBSPI5SOMI[3:0]* 8Transfer Groups MIBSPI5CLK* FMzPLL 128Buffers MIBSPI5SCS[3:0]* OSC RTI withParity MIBSPI5ENA* OSCIN OSCOUT Clock FPLL VIM DCAN1 CAN1RX Kelvin_GND Monitor 64Messages CAN1TX forFlexRay 64Channel withParity withParity DCAN2 CAN2RX 64Messages CAN2TX withParity RTP MiBADC1 MiBADC2 DCAN3 CAN3RX Vcc VMON 64Words 64Words 64Words 32wMithePssaarigtyes CAN3TX VccIO 2RAMblocks withParity withParity 12Bit 12Bit GIO GIOA[7:0]/INT[7:0] GIOB[7:0] Note: Priorities RTPENARTPSYNC RTPCLKDATA[15:0] AD1IN[7:0]AD1EVT DSIN[15:8] VCCADVSSADADREFHIADREFLO AD2IN[7:0]AD2EVT *SSSMCCCIBRRRS21P: ::IPrr1o5o=uupDninnMddsAraro,or be2bi=minnDuMltiMple, x3e=dDAP P A withDMMDATA[15:2]pins T R Copyright©2010–2018,TexasInstrumentsIncorporated TMS570LSSeries16/32-BITRISCFlashMicrocontroller 5 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table of Contents 1 TMS570LSSeries16/32-BITRISCFlash 5.2 Die-ID Registers..................................... 60 Microcontroller........................................... 1 ....................................... 5.3 PLLRegisters 61 1.1 Features.............................................. 1 6 DeviceElectricalSpecifications..................... 62 1.2 Description............................................ 2 6.1 OperatingConditions................................ 62 ........................... 1.3 FunctionalBlockDiagram 5 6.2 AbsoluteMaximumRatingsOverOperatingFree- 2 DeviceOverview......................................... 7 AirTemperatureRange(unlessotherwisenoted).. 62 2.1 TermsandAcronyms................................. 7 6.3 DeviceRecommendedOperatingConditions....... 62 2.2 Device Characteristics................................ 8 6.4 ElectricalCharacteristicsOverOperatingFree-Air ................................ ............................................... TemperatureRange 63 2.3 Memory 9 .................................... 7 PeripheralandElectricalSpecifications........... 67 2.4 PinAssignments 18 ............................................... .................................. 7.1 Clocks 67 2.5 TerminalFunctions 23 .................................. ...................................... 7.2 ECLKSpecification 71 2.6 DeviceSupport 36 ......................... 3 Reset/AbortSources................................. 38 7.3 RSTAndPORRSTTimings 72 .................................... ............................... 7.4 TESTPinTiming 74 3.1 Reset/AbortSources 38 ................. 4 Peripherals............................................... 41 7.5 DAP-JTAGScanInterfaceTiming 75 ...................................... ...................... 7.6 OutputTimings 76 4.1 ErrorSignalingModule(ESM) 41 ........................................ ...................... 7.7 InputTimings 77 4.2 DirectMemoryAccess(DMA) 44 ....................................... ............ 7.8 FlashTimings 78 4.3 HighEndTimerTransferUnit(HET-TU) 45 ............... .................. 7.9 SPIMasterModeTimingParameters 79 4.4 VectoredInterruptManager(VIM) 46 ................ .................... 7.10 SPISlaveModeTimingParameters 83 4.5 MIBADCEventTriggerSources 48 ...................... .............................................. 7.11 CANControllerModeTimings 87 4.6 MIBSPI 49 .............................. ................................................. 7.12 SCI/LINModeTimings 87 4.7 ETM 51 ................... ................................. 7.13 FlexRayControllerModeTimings 87 4.8 DebugScanChains 52 ........................................ ................................................. 7.14 EMIFTimings 88 4.9 CCM 53 ........................................ ................................................. 7.15 ETMTimings 90 4.10 LPM 54 ........................................ ..................................... 7.16 RTPTimings 92 4.11 VoltageMonitor 54 ........................................ ................................................. 7.17 DMMTimings 94 4.12 CRC 54 ............................................. ............................. 7.18 MibADC 95 4.13 SystemModuleAccess 54 ......................................... 8 Revision History...................................... 101 4.14 Debug ROM 55 ............. 9 MechanicalPackagingandOrderable 4.15 CPUSelfTestController:STC/LBIST 56 Information............................................. 102 5 DeviceRegisters....................................... 58 ...................................... 9.1 ThermalData 102 ................. 5.1 DeviceIdentificationCodeRegister 58 ............................. 9.2 PackagingInformation 102 6 TableofContents Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 2 Device Overview 2.1 Terms and Acronyms Table2-1.TermsandAcronyms TermsandAcronyms Description Comments ADC AnalogToDigitalConverter AHB AdvancedHigh-performanceBus PartoftheR4core CCM-R4 CPUCompareModuleforCortexTM-R4F CRC CyclicRedundancyCheckController DAP DebugAccessPort DAPisanimplementationofanARMDebugInterface. DCAN ControllerAreaNetwork DMA DirectMemoryAccess DMM DataModificationModule ECC ErrorCorrectionCode EMIF ExternalMemoryInterface ESM ErrorSignalingModule ETM EmbeddedTraceModule FMzPLL Frequency-ModulatedZero-PinPhase-Locked Loop FPLL FlexRayPhase-LockedLoop GIO General-PurposeInput/Output HET High-EndTimer ICEPICK InCircuitEmulationTAP(TestAccessPort) ICEPickcanconnectorisolateamodulelevelTAPtoorfroma SelectionModule higherlevelchipTAP.ICEPickwasdesignedwithboth emulationandtestrequirementsinmind. JTAG JointTestAccessGroup IEEECommitteeresponsibleforTestAccessPorts LBIST LogicBuilt-InSelfTest TesttheintegrityofR4CPU LIN LocalInterconnectNetwork VIM VectoredInterruptManager MibSPI Multi-BufferedSerialPeripheralInterface MPU MemoryProtectionUnit OSC Oscillator PBIST ProgrammableBuilt-InSelfTest TesttheintegrityofSRAM PCR PeripheralCentralResource POM ParameterOverlayModule ThePOMprovidesamechanismtoredirectaccessestonon- volatilememoryintoavolatilememoryexternaltothedevice. PSA ParallelSignatureAnalysis RTI Real-TimeInterrupt RTP RAMTracePort SCR SwitchCentralResource SCI SerialCommunicationInterface SECDED SingleErrorCorrectionandDoubleError Detection STC SelfTestController SYS SystemModule TU TransferUnit VBUS VirtualBus OneoftheprotocolsthatcomprisesCBA(CommonBus Architecture) VBUSP VirtualBus-Pipelined OneoftheprotocolsthatcomprisesCBA(CommonBus Architecture) VMON VoltageMonitor Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 7 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 2.2 Device Characteristics ThetablebelowshowsthedifferentconfigurationsoptionsofferedintheTMS570LSseriesofdevices: Table2-2.CharacteristicsoftheTMS570LSSeriesDevices Feature TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Package 337 144QFP 337 144QFP 337 144QFP 337 144QFP 337 144QFP 337 144QFP BGA BGA BGA BGA BGA BGA Type (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) Speed 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz Flash 2MB 2MB 2MB 2MB 1MB 1MB 1MB 1MB 1MB 1MB 1MB 1MB Size RAMSize 160KB 160KB 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB FlexRay 2ch 2ch - - 2ch 2ch - - 2ch 2ch - - CAN 3 2 3 2 3 2 3 2 3 2 3 2 MibSPI 3 3 3 3 3 3 3 3 3 3 3 3 UART/ 2 2 2 2 2 2 2 2 2 2 2 2 LIN NHET 32 25 32 25 32 25 32 25 32 25 32 25 Channels 12-Bit 24 20 24 20 24 20 24 20 24 20 24 20 ADC Channels EMIF 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - GIO 16 8 16 8 16 8 16 8 16 8 16 8 ETM 32-bit - 32-bit - 32-bit - 32-bit - 32-bit - 32-bit - RTP 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - DMM 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 8 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 2.3 Memory 2.3.1 Memory Map The memory map, including all available Flash and RAM memory configurations for the device family, are shown below. Figure 2-1 applies to TMS570LS20216 and TMS570LS20206. Figure 2-2 applies to TMS570LS10216andTMS570LS10206.Figure2-3appliestoTMS570LS10106andTMS570LS10116. 0xFFFFFFFF SYSTEM Modules 0xFFF80000 0xFFF7FFFF Peripherals 0xFF000000 0xFEFFFFFF CRC 0xFE000000 RESERVED 0x6FFFFFFF CS3 CS2 EMIF (256MB) CS1 0x603FFFFF POM (4MB) 00xx6600000000000000 CS0 00xx6600000000000000 RESERVED 00xx220044FFFFFFFFFF 00xx220044FFFFFFFFFF Flash - ECC (2MB Mirrored Image) 00xx2200440000000000 00xx2200440000000000 RESERVED 00xx220011FFFFFFFFFF 00xx220011FFFFFFFFFF Flash (2MB) (Mirrored Image) 00xx2200000000000000 00xx2200000000000000 RESERVED 00xx0088442277FFFFFF 00xx0088442277FFFFFF RAM - ECC(160kB) 00xx0088440000000000 00xx0088440000000000 RESERVED 00xx0088002277FFFFFF 00xx0088002277FFFFFF RAM (160kB) 00xx0088000000000000 00xx0088000000000000 RESERVED 00xx000044FFFFFFFFFF 00xx000044FFFFFFFFFF Flash-ECC (2MB) 00xx0000440000000000 00xx0000440000000000 RESERVED 00xx000011FFFFFFFFFF 00xx000011FFFFFFFFFF Flash (2MB) 00xx0000000000000000 00xx0000000000000000 Figure2-1.MemoryMapofTMS570LS20216andTMS570LS20206 Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 0xFFFFFFFF SYSTEM Modules 0xFFF80000 0xFFF7FFFF Peripherals 0xFF000000 0xFEFFFFFF CRC 0xFE000000 RESERVED 0x6FFFFFFF CS3 CS2 EMIF (256MB) CS1 0x603FFFFF CS0 POM (4MB) 0x60000000 0x60000000 RESERVED 0x2047FFFF 0x2047FFFF Flash - ECC (1MB Mirrored Image) 0x20400000 0x20400000 RESERVED 0x200FFFFF 0x200FFFFF Flash (1MB) (Mirrored Image) 0x20000000 0x20000000 RESERVED 0x08427FFF 0x08427FFF RAM - ECC(160kB) 0x08400000 0x08400000 RESERVED 0x08027FFF 0x08027FFF RAM (160kB) 0x08000000 0x08000000 RESERVED 0x0047FFFF 0x0047FFFF Flash-ECC (1MB) 0x00400000 0x00400000 RESERVED 0x000FFFFF 0x000FFFFF Flash (1MB) 0x00000000 0x00000000 Figure2-2.MemoryMapofTMS570LS10216andTMS570LS10206 10 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 0xFFFFFFFF SYSTEM Modules 0xFFF80000 0xFFF7FFFF Peripherals 0xFF000000 0xFEFFFFFF CRC 0xFE000000 RESERVED 0x6FFFFFFF CS3 CS2 EMIF (256MB) CS1 0x603FFFFF POM (4MB) 0x60000000 CS0 0x60000000 RESERVED 0x2047FFFF 0x2047FFFF Flash - ECC (1MB Mirrored Image) 0x20400000 0x20400000 RESERVED 0x200FFFFF 0x200FFFFF Flash (1MB) (Mirrored Image) 0x20000000 0x20000000 RESERVED 0x0841FFFF 0x0841FFFF RAM - ECC(128kB) 0x08400000 0x08400000 RESERVED 0x0801FFFF 0x0801FFFF RAM (128kB) 0x08000000 0x08000000 RESERVED 0x0047FFFF 0x0047FFFF Flash-ECC (1MB) 0x00400000 0x00400000 RESERVED 0x000FFFFF 0x000FFFFF Flash (1MB) 0x00000000 0x00000000 Figure2-3.MemoryMapofTMS570LS10116andTMS570LS10106 The Parameter Overlay memory space maps to the lower 4MB of the EMIF CS0 memory space. ECC must be disabled by software via the CPU CP15 register if POM is used to overlay the program memory to the EMIF space; otherwise ECC errors will be generated. The contents of memory connected to the EMIF are not guaranteed after a power on reset. The addressable EMIF memory range is limited to the lower32MBofeachEMIFchipselectfor16bitmemories,andtothelower16MBofeachEMIFchipselect for8bitmemories.ThedefaultEMIFdatawidthis16bit.TheEMIFpinsdonothaveGIOfunctionality. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 2.3.2 Flash Memory The F035 (130nm Flash Process) Flash memory is a nonvolatile electrically erasable and programmable memory.TheFlashhasastatemachineforsimplifyingtheprogramanderasefunctions. This device’s 2M-Byte flash memory contains four 512K-Byte memory arrays (or banks) consisting of 22 total sectors. 1M-Byte versions of the device contain only the first two 512K-Byte banks (Bank 0 and Bank 1) and have a total of 14 sectors. The bank and sector configurations are shown in Flash Memory Banks and Sectors . When in pipeline mode, the Flash operates with a system clock frequency of up to 160MHz (versus a system clock in non-pipeline mode of up to 36MHz). The flash in pipeline mode is capable of accessing128bitsatatimeandprovidestwo64-bitpipelinedwordstotheCPU.Theminimumsizeforan erase operation is one sector. A single program operation can program either one 32-bit word or one 16- bithalfwordatatime. Table2-3.FlashMemoryBanksandSectors MEMORYARRAYS(OR SectorNO. Segment LowAddress Highaddress BANKS) Bank0:512KBytes 0 32KBytes 0x0000_0000 0x0000_7FFF 1 32KBytes 0x0000_8000 0x0000_FFFF 2 32KBytes 0x0001_0000 0x0001_7FFF 3 8KBytes 0x0001_8000 0x0001_9FFF 4 8KBytes 0x0001_A000 0x0001_BFFF BANK0(512KBytes) 5 16KBytes 0x0001_C000 0x0001_FFFF 6 64KBytes 0x0002_0000 0x0002_FFFF 7 64KBytes 0x0003_0000 0x0003_FFFF 8 128KBytes 0x0004_0000 0x0005_FFFF 9 128KBytes 0x0006_0000 0x0007_FFFF Bank1:512KBytes 0 128KBytes 0x0008_0000 0x0009_FFFF 1 128KBytes 0x000A_0000 0x000B_FFFF BANK1(512KBytes) 2 128KBytes 0x000C_0000 0x000D_FFFF 3 128KBytes 0x000E_0000 0x000F_FFFF Bank2:512KBytes 0 128KBytes 0x0010_0000 0x0011_FFFF 1 128KBytes 0x0012_0000 0x0013_FFFF BANK2(512KBytes) 2 128KBytes 0x0014_0000 0x0015_FFFF 3 128KBytes 0x0016_0000 0x0017_FFFF Bank3:512KBytes 0 128KBytes 0x0018_0000 0x0019_FFFF 1 128KBytes 0x001A_0000 0x001B_FFFF BANK3(512kBytes) 2 128KBytes 0x001C_0000 0x001D_FFFF 3 128KBytes 0x001E_0000 0x001F_FFFF 12 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 NOTE • The external flash pump voltage (VccP) is required for all flash operations (program, erase,andread). • After a system reset, pipeline mode is disabled (FRDCNTL[2:0] is a "000"). In other words,thedevicepowersupandcomesoutofresetinnon-pipelinemode. • The user must program proper ECC bits throughout the entire flash memory to avoid ECCerrorsduetoCortexR4speculativefetchesifflashECCisenabled. • TheflashonthisdevicedoesnotsupportEEPROMemulation. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 2.3.3 System Modules Assignment This table shows the memory map for the Cyclic Redundancy Check (CRC) module, the Cortex™-R4F CoreSight™debugmodule,andtheSystemmodules. Table2-4.SystemModulesAssignment FrameName AddressRange FrameStartAddress FrameEndingAddress CRC 0xFE00_0000 0xFEFF_FFFF CoreSightDebugROMRegister 0xFFA0_0000 0xFFA0_0FFF Cortex-R4FDebugRegister 0xFFA0_1000 0xFFA0_1FFF ETM-R4Register 0xFFA0_2000 0xFFA0_2FFF CoreSightTPIURegister 0xFFA0_3000 0xFFA0_3FFF POMRegister 0xFFA0_4000 0xFFA0_4FFF DMARAM 0xFFF8_0000 0xFFF8_0FFF VIMRAM 0xFFF8_2000 0xFFF8_2FFF RTPRAM 0xFFF8_3000 0xFFF8_3FFF FlashWrapperRegister 0xFFF8_7000 0xFFF8_7FFF PCRRegister 0xFFFF_E000 0xFFFF_E0FF FlexRayPLL/STCCLKRegister 0xFFFF_E100 0xFFFF_E1FF PBISTRegister 0xFFFF_E400 0xFFFF_E5FF STCRegister 0xFFFF_E600 0xFFFF_E6FF EMIFRegister 0xFFFF_E800 0xFFFF_E8FF DMARegister 0xFFFF_F000 0xFFFF_F3FF ESMRegister 0xFFFF_F500 0xFFFF_F5FF CCMR4Register 0xFFFF_F600 0xFFFF_F6FF DMMRegister 0xFFFF_F700 0xFFFF_F7FF RAMECCevenRegister 0xFFFF_F800 0xFFFF_F8FF RAMECCoddRegister 0xFFFF_F900 0xFFFF_F9FF RTPRegister 0xFFFF_FA00 0xFFFF_FAFF RTIRegister 0xFFFF_FC00 0xFFFF_FCFF VIMParityRegister 0xFFFF_FD00 0xFFFF_FDFF VIMRegister 0xFFFF_FE00 0xFFFF_FEFF SystemRegister 0xFFFF_FF00 0xFFFF_FFFF 14 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 2.3.4 Peripheral Selects The peripheral frame contains the memory map for the peripheral registers as well as the peripheral memories. The first table shows the memory map for the peripheral module registers and following table showsthememorymapfortheperipheralmodulememories. Table2-5.PeripheralSelectAssignment PeripheralModule AddressRange PeripheralSelects BaseAddress EndingAddress MIBSPIP5 0xFFF7_FC00 0xFFF7_FDFF PS[0] MIBSPI3 0xFFF7_F800 0xFFF7_F9FF PS[1] MIBSPI1 0xFFF7_F400 0xFFF7_F5FF PS[2] LIN2 0xFFF7_E500 0xFFF7_E5FF PS[6] LIN1 0xFFF7_E400 0xFFF7_E4FF DCAN3 0xFFF7_E000 0xFFF7_E1FF PS[7] DCAN2 0xFFF7_DE00 0xFFF7_DFFF PS[8] DCAN1 0xFFF7_DC00 0xFFF7_DDFF FlexRay 0xFFF7_C800 0xFFF7_CFFF PS[12]+PS[13] MIBADC2 0xFFF7_C200 0xFFF7_C3FF PS[15] MIBADC1 0xFFF7_C000 0xFFF7_C1FF GIO 0xFFF7_BC00 0xFFF7_BCFF PS[16] NHET 0xFFF7_B800 0xFFF7_B8FF PS[17] HETTU 0xFFF7_A400 0xFFF7_A4FF PS[22] FlexRayTU 0xFFF7_A000 0xFFF7_A1FF PS[23] Table2-6.PeripheralMemorySelects PeripheralModuleMemory AddressRange PeripheralSelects BaseAddress EndingAddress MIBSPIP5RAM 0xFF0A0000 0xFF0BFFFF PCS[5] MIBSPI3RAM 0xFF0C0000 0xFF0DFFFF PCS[6] MIBSPI1RAM 0xFF0E0000 0xFF0FFFFF PCS[7] DCAN3RAM 0xFF1A0000 0xFF1BFFFF PCS[13] DCAN2RAM 0xFF1C0000 0xFF1DFFFF PCS[14] DCAN1RAM 0xFF1E0000 0xFF1FFFFF PCS[15] MIBADC2RAM 0xFF3A0000 0xFF3BFFFF PCS[29] MIBADC1RAM 0xFF3E0000 0xFF3FFFFF PCS[31] NHETRAM 0xFF460000 0xFF47FFFF PCS[35] HETTURAM 0xFF4E0000 0xFF4FFFFF PCS[39] FlexRayTURAM 0xFF500000 0xFF51FFFF PCS[40] Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 2.3.5 Memory Auto-Initialization This device allows some of the on-chip memories to be initialized via the memory hardware initialization control registers in the System module. The purpose of having the hardware initialization is to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC). The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized. Please refer to the Architecture chapter oftheTechnicalReferenceManual(TRM)formoreinformation. The mapping of the different memories to the specific bits in the MSINENA register is shown in the followingtable. Table2-7.MemoryInitialization ConnectingModule AddressRange RAMSelect BaseAddress EndingAddress RAM 0x08000000 0x0801FFFF 0 MIBSPIP5RAM 0xFF0A0000 0xF0BFFFFF 12 MIBSPI3RAM 0xFF0C0000 0xFF0DFFFF 11 MIBSPI1RAM 0xFF0E0000 0xFF0FFFFF 7 DCAN3RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1RAM 0xFF1E0000 0xFF1FFFFF 5 FlexRayRAM RAMisnotvisible 9(1) MIBADC2RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1RAM 0xFF3E0000 0xFF3FFFFF 8 NHETRAM 0xFF460000 0xFF47FFFF 3 HETTURAM 0xFF4E0000 0xFF4FFFFF 4 DMARAM 0xFFF80000 0xFFF80FFF 1 VIMRAM 0xFFF82000 0xFFF82FFF 2 FlexRayTURAM 0xFF500000 0xFF51FFFF 13 (1) reservedonly;theFlexRayRAMhasitsownInitializationmechanism. TheassociatedECCRAMwillgetinitializedaswell,iftheECCfunctionalityisenabled. TheassociatedParityRAMwillgetinitializedaswell,iftheParityfunctionalityisenabled. NOTE The user must initialize entire SRAM with ECC bits to avoid ECC errors due to Cortex R4 speculativefetchesifSRAMECCisenabled. 16 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 2.3.6 PBIST RAM Self Test The PBIST (Programmable Built-In Self Test) architecture provides a run-time-programmable memory BIST engine for varying levels of test coverage across the device’s embedded RAM memory. The PBIST architecture consists of a small CPU with an instruction set targeted specifically towards testing RAM memories. This CPU includes both control and instruction registers necessary to execute the individual memory algorithms. In order to minimize test load overhead, once an algorithm is loaded into the instruction registers, it can be run on multiple memories of different sizes or types. The memory configuration information and test algorithm code is stored in an on-chip ROM. The PBIST RAM groups implemented on this device are shown in the following table. More information about memory self test can befoundinthePBISTchapterofthedeviceTRM. Table2-8.PBISTRAMGrouping RAM Module MemoryType RGS TestPattern(Algorithm) Group /RDS(1) Triple Triple March Down1A Pre- Map DTXN2A PMOS slow fastread 13N [HCLK/ charge column [HCLK/ open read [ROM [HCLK/ VCLK(2) [HCLK/ [HCLK/ VCLK(2) [HCLK/ [ROM clock VCLK(2) cycles] VCLK(2) VCLK(2) cycles] VCLK(2) clock cycles] cycles] cycles] cycles] cycles] cycles] 1 PBIST ROM 0/1 12290 4098 ROM 2 STC ROM 13/1 24578 8194 ROM 3 DCAN1 SP 1/0..2 12600 2637 2064 1914 5490 11544 4 DCAN2 SP 2/0..2 12600 2637 2064 1914 5490 11544 5 DCAN3 SP 3/0..2 6360 1341 1104 1146 2754 5016 6 ESRAM SP,multi-strobe 4/21..22 266320 52254 41120 33212 181260 409616 w/pagemode 7 MibSPI SP 5/0..5 50160 10458 7968 6900 21924 52272 8 VIM SP 6/0 4200 879 688 638 1830 3848 9 MibADC 2P,syncwrite 7/0..1 8400 1758 1376 1276 3660 7696 asyncread 10 DMA 2P,syncwrite 8/0..5 18960 4410 3072 2772 6084 Not asyncread Available 11 NHET 2P,syncwrite 9/0..11 25440 5940 4224 4008 8136 20064 asyncread 12 HETTU 2P,syncwrite 10/0..5 6480 1530 1152 1236 2052 4272 asyncread 13 RTP 2P,syncwrite 11/0..8 37800 8775 6048 5310 12150 34632 asyncread 14 FlexRay SP 12/0..7 175040 34872 27296 22608 108912 246336 15 ESRAM SP,multi-strobe 4/20 133160 26127 20560 16606 90630 204808 w/pagemode SP=SinglePortRAM;2P=TwoPortRAM (1) RGS(RAMgroupselect)andRDS(returndataselect)standforanuniqueRAMselectid.MoreinformationabouttheRGSandthe RDScanbefoundinthetechnicalreferencemanual(TRM) (2) ThetestclockforESRAM,DMAandRTPisHCLK;thetestclockforothermodulesisVCLK. NOTE • TheMarch13Ntestalgorithmisrecommendedforapplicationtesting. • ThemaximumPBISTtestexecutionspeedislimitedto100MHz. • ThesupplycurrentwhileperformingPBISTselftestisdifferentthanthedeviceoperating mode current. These values can be found in the I section of the device electrical cc specifications. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 2.4 Pin Assignments 2.4.1 PGE QFP Package Pinout (144 pin) (TOPVIEW) 5SOMI[3]5SOMI[2]5SOMI[1]5SOMI[0]5SIMO[3]5SIMO[2]SIMO[1]SIMO[0]5ENA5CS[1]5CS[0]CLK SPISPISPISPISPISPIPI5PI5SPISPISPIPI5 BBBBBBSSBBBS 15]/MI14]/MI13]/MI12]/MI11]/MI10]/MI9]/MIB8]/MIB7]/nMI6]/nMI5]/nMI4]/MIB CCIOSSIOHET[28]HET[0]CCSSMMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[MMDATA[CCIOSSIOCLKCCSSRSTD1EVTD1IN[0]D1IN[1]D1IN[2]D1IN[3]D1IN[4]D1IN[5]D1IN[6]D1IN[7]DSIN[8]DSIN[9]DSIN[10] VVNNVVDDDDDDDDDDDDVVEVVnAAAAAAAAAAAA 87 6543 21 0 98 76 5 4321 09876 5 432109 876 5 43 00 0000 00 0 99 99 9 999998888 8 888887 777 7 77 11 1111 11 1 NHET[7] 109 72 ADSIN[11] GIOA[4]/INT[4] 110 71 ADSIN[12] GIOA[5]/INT[5] 111 70 ADSIN[13] NHET[8] 112 69 ADSIN[14] NHET[15] 113 68 ADSIN[15] VCC 114 67 VCCAD VSS 115 66 ADREFHI NHET[10] 116 65 ADREFLO NHET[11] 117 64 VSSAD GIOA[0]/INT[0] 118 63 AD2IN[3] VCCIO 119 62 AD2IN[2] VSSIO 120 61 AD2IN[1] NHET[4] 121 60 AD2IN[0] FLTP1 122 59 AD2EVT FLTP2 123 58 TEST FRAYTX1 124 57 NHET[9] FRAYTXEN1 125 56 NHET[2] FRAYRX1 126 55 CAN2RX VSS 127 54 CAN2TX VCCP 128 53 LIN1RX FRAYTX2 129 52 LIN1TX FRAYTXEN2 130 51 GIOA[7]/INT[7] FRAYRX2 131 50 CAN1TX VCCIO 132 49 CAN1RX VSSIO 133 48 NHET[6] GIOA[1]/INT[1] 134 47 VCC VCC 135 46 VSS VSS 136 45 NHET[20] NHET[30] 137 44 NHET[5] NHET[14] 138 43 NHET[24] LIN2TX 139 42 NHET[1] LIN2RX 140 41 NHET[3] GIOA[2]/INT[2] 141 40 VCCIO NHET[16] 142 39 VSSIO nERROR 143 38 VSS GIOA[3]/INT[3] 144 37 VCC 01234567 890 1 23 456789 01 23 45 6 1 2345678911111111 112 2 22 222222 33 33 33 3 VCCIOVSSIOBSPI3CLKSPI3SIMOSPI3SOMIBSPI3ENASPI3CS[0]NHET[12]NHET[22]NHET[18]NHET[21]NHET[23]SPI1SOMISPI1SIMOVCCIOVSSIOBSPI1CLK BSPI1ENAVCCOSCINOSCOUTVSSSPI1CS[0]SPI1CS[1]SPI1CS[2]NHET[13]A[6]/INT[6]nPORRSTnTRSTTCKVCCVSSTDOTDIRTCKTMS MIMIBMIBnMIMIB MIBMIB MI nMI MIBMIBMIB GIO N nnn Figure2-4.PGEPinout(144pin)[TopView] 18 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 2.4.2 ZWT BGA Package Pinout (337 ball) A B C D E F G H J K L NHET MIBSPI5 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 NHET DMM 19 VSS VSS TMS 19 [10] CS[0] SIMO ENA CLK SIMO[0] [28] DATA[0] NHET MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 NHET DMM 18 VSS TCK TDO TRST [08] CLK SOMI ENA SOMI[0] [0] DATA[1] 18 EMIF_ EMIF MIBSPI5 DMM MIBSPI5 MIBSPI5 NHET EMIF_ EMIF_ 17 TDI RST ADDR[21] _WE SOM[1] CLK SIMO[3] SIMO[2] [31] CS[1] CS[0] 17 FRAY EMIF_ EMIF_ MIBSPI5 DMM MIBSPI5 MIBSPI5 DMM EMIF_ EMIF_ 16 RTCK 16 TXEN1 ADDR[20] BA[1] SIMO[1] ENA SOMI[3] SOMI[2] SYNC DATA[0] DATA[1] FRAY FRAY EMIF_ EMIF_ ETM ETM ETM ETM ETM ETM ETM 15 15 RX1 TX1 ADDR[19] ADDR[18] DATA[06] DATA[05] DATA[04] DATA[03] DATA[02] DATA[16] DATA[17] NHET EMIF_ EMIF_ ETM 14 [26] ERROR ADDR[17] ADDR[16] DATA[07] VCCIO VCCIO VCCIO VCC VCC VCCIO 14 NHET NHET EMIF_ EMIF_ ETM 13 VCCIO 13 [17] [19] ADDR[15] BA[0] DATA[12] NHET EMIF_ EMIF_ ETM 12 ECLK VCCIO VSS VSS VCC VSS 12 [04] ADDR[14] OE DATA[13] NHET NHET EMIF_ EMIF_ ETM 11 VCCIO VSS VSS VSS VSS 11 [14] [30] ADDR[13] DQM[1] DATA[14] CAN1 CAN1 EMIF_ EMIF_ ETM 10 VCC VCC VSS VSS VSS 10 TX RX ADDR[12] DQM[0] DATA[15] A B C D E F G H J K L Figure2-5.ZWTPackagePinoutTopLeftQuadrant(337ball)[TopView] Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com K L M N P R T U V W NHET DMM CAN3 AD1 ADS AD2 AD1 ADS 19 VSSAD VSSAD 19 [28] DATA[0] RX EVT IN[15] IN[6] IN[6] IN[11] NHET DMM CAN3 ADS ADS ADS AD1 AD1 18 NC VSSAD 18 [0] DATA[1] TX IN[8] IN[14] IN[13] IN[4] IN[2] EMIF_ EMIF_ EMIF_ EMIF_ AD1 AD1 ADS AD1 ADS 17 NC 17 CS[1] CS[0] CS[2] CS[3] IN[5] IN[3] IN[10] IN[1] IN[9] EMIF_ EMIF_ EMIF_ EMIF_ AD2 ADS AD2 ADREF 16 DATA[0] DATA[1] DATA[2] DATA[3] NC IN[7] IN[12] IN[3] LO VSSAD 16 ETM ETM ETM ETM AD2 AD2 ADREF 15 DATA[16] DATA[17] DATA[18] DATA[19] NC NC IN[5] IN[4] HI VCCAD 15 AD2 AD1 AD1 14 VCC VCCIO VCCIO VCCIO VCCIO NC NC 14 IN[2] IN[7] IN[0] ETM AD2 AD2 AD2 13 VCCIO NC 13 DATA[1] IN[1] IN[0] EVT ETM MIBSPI5 RTP LIN1 LIN1 12 VCC VSS VSS VCCIO DATA[0] CS[3] ENA TX RX 12 ETM RTP RTP RTP RTP 11 VSS VSS VSS VCC TRACE 11 SYNC DATA[1] DATA[0] CLK CTL ETM RTP RTP MIBSPI3 10 VSS VSS VCC VCC TRACE GIOB[3] 10 DATA[2] DATA[3] CS[0] CLKOUT K L M N P R T U V W Figure2-6.ZWTPackagePinoutTopRightQuadrant(337ball)[TopView] 20 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 A B C D E F G H J K L EMIF_ EMIF_ ETM_ 10 CAN1TX CAN1RX ADDR[12] DQM[0] DATA[15] VCC VCC VSS VSS VSS 10 9 N[H2E7]T TFXREANY2 ADEMDRIF[_11] AEDMDIRF[_5] DAETTAM[8] VCC VSS VSS VSS VSS 9 8 FRAY FRAY EMIF_ EMIF_ ETM VCCP VSS VSS VCC VSS 8 RX2 TX2 ADDR[10] ADDR[4] DATA[9] 7 LIN2 LIN2 EMIF_ EMIF_ ETM VCCIO 7 RX TX ADDR[9] ADDR[3] DATA[10] GIOA 6 MIBSPI5 EMIF_ EMIF_ ETM VCCIO VCCIO VCCIO VCCIO VCC VCC 6 [4] CS[1] ADDR[8] ADDR[2] DATA[11] GIOA GIOA EMIF_ EMIF_ ETM ETM ETM ETM ETM 5 FLTP2 FLTP1 5 [0] [5] ADDR[7] ADDR[1] DATA[20] DATA[21] DATA[22] DATA[23] DATA[24] 4 NHET NHET EMIF_ EMIF_ EMIF_ EMIF_ EMIF_ NHET NHET EMIF_ EMIF_ 4 [16] [12] ADDR[6] ADDR[0] DATA[4] DATA[5] DATA[6] [21] [23] DATA[7] DATA[8] 3 NHET NHET MIBSPI3 NC NHET MIBSPI1 MIBSPI1 GIOA MIBSPI1 NC NC 3 [29] [22] CS[3] [11] CS[1] CS[2] [6] CS[3] 2 VSS MCIBSS[P2]I3 GI[O1]A NC NC GI[O2]B GI[O5]B CATXN2 GI[O6]B GI[O1]B KEGLNVDIN 2 1 VSS VSS GIOA NC GIOA GIOB GIOB CAN2 NHET OSCIN OSCOUT 1 [2] [3] [7] [4] RX [18] A B C D E F G H J K L Figure2-7.ZWTPackagePinoutBottomLeftQuadrant(337ball)[TopView] Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com K L M N P R T U V W ETM RTP RTP MIBSPI3 10 VSS VSS VCC VCC TRACE GIOB[3] 10 DATA[2] DATA[3] CS[0] CLKOUT ETM RTP RTP MIBSPI3 MIBSPI3 9 VSS VSS VSS VCCIO 9 TRACE DATA[4] DATA[5] CLK ENA CLKIN ETM EMIF_ RTP MIBSPI3 MIBSPI3 8 VCC VSS VSS VCCIO 8 DATA[31] DATA[15] DATA[6] SOMI SIMO ETM EMIF_ RTP NHET 7 VCCIO DATA[30] DATA[14] DATA[7] [9] PORRST 7 ETM EMIF_ RTP NHET MIBSPI5 6 VCC VCC VCCIO VCCIO VCCIO 6 DATA[29] DATA[13] DATA[8] [5] CS[2] ETM ETM ETM ETM ETM ETM EMIF_ RTP MIBSPI3 NHET 5 5 DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28] DATA[12] DATA[9] CS[1] [2] EMIF_ EMIF_ EMIF_ EMIF_ EMIF_ RTP RTP 4 NC VSS NC 4 DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[11] DATA[10] NHET RTP RTP RTP NHET 3 NC NC NC NC NC 3 [25] DATA[14] DATA[13] DATA[12] [6] GIOB KELVIN GIOB NHET NHET MIBSPI1 RTP NHET 2 TEST VSS 2 [1] GND [0] [13] [20] CS[0] DATA[15] [1] GIOA NHET NHET NHET NHET 1 OSCIN OSCOUT NC VSS VSS 1 [7] [15] [24] [7] [3] K L M N P R T U V W Figure2-8.ZWTPackagePinoutBottomRightQuadrant(337ball)[TopView] 22 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 2.5 Terminal Functions Thisfollowingtabledescribesthepinsonthedevice. NOTE Table Abbreviations: PWR = power, GND = ground, REF = reference voltage, NC = no connect, IPD = Internal Pull Down, IPU = Internal Pull Up, I/O = Input/Output, I = Input, O = Output Table2-9. TerminalFunctions Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 HIGH-ENDTIMER(NHET) NHET[0] K18 105 K18 105 Timerinputcaptureoroutputcompare. TheapplicableNHETpinscanbe NHET[1] V2 42 V2 42 programmedasgeneral-purpose NHET[2] W5 56 W5 56 input/output(GIO)pins.NHETpinsare high-resolution. NHET[3] U1 41 U1 41 Thehigh-resolution(HR)SHAREfeature NHET[4] B12 121 B12 121 allowsevenHRpinstosharethenext NHET[5] V6 44 V6 44 higheroddHRpinstructures.Thenext higheroddHRpinstructureisalways NHET[6] W3 48 W3 48 implemented,evenifthenexthigherodd NHET[7] T1 109 T1 109 HRpadand/orpinitselfisnot.TheHR sharingisindependentofwhetherornot NHET[8] E18 112 E18 112 theoddpinisavailableexternally.Ifan NHET[9] V7 57 V7 57 oddpinisavailableexternallyand shared,thentheoddpincanonlybe NHET[10] D19 116 D19 116 usedasageneral-purposeI/O. NHET[11] E3 117 E3 117 NHET[0]providesSPIclockwhenused forSPIemulation. NHET[12] B4 8 B4 8 EachNHETpinisequippedwithaninput NHET[13] N2 26 N2 26 suppressionfilterthatcanbeusedto eliminatethesamplingofpulsesthatare NHET[14] A11 138 A11 138 program smallerthanaprogrammableduration NHET[15] N1 113 N1 113 mable GIOA[0]/INT[0]isalsoconnectedtothe NHET[16] A4 142 A4 142 3.3VI/O 2mA-z IPD NHETPinDisableinputoftheNHET (20uA) module. NHET[17] A13 A13 NHETpinscanbeprogrammedasa GIOpinswhennotusedasNHET NHET[18] J1 10 J1 10 functionalpins. NHET[19] B13 B13 NHET[20] P2 45 P2 45 NHET[21] H4 11 H4 11 NHET[22] B3 9 B3 9 NHET[23] J4 12 J4 12 NHET[24] P1 43 P1 43 NHET[25] M3 M3 NHET[26] A14 A14 NHET[27] A9 A9 NHET[28] K19 106 K19 106 NHET[29] A3 A3 NHET[30] B11 137 B11 137 NHET[31] J17 J17 Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 GENERAL-PURPOSEI/O(GIO) General-purposeinput/outputpin. GIOA[0]/INT[0]isaninterrupt-capable GIOA[0]/INT0 A5 118 A5 118 pin.GIOA[0]/INT[0]isalsoconnectedto theNHETPinDisableinputoftheNHET module. GIOA[1]/INT1 C2 134 C2 134 GIOA[2]/INT2 C1 141 C1 141 GIOA[3]/INT3 E1 144 E1 144 General-purposeinput/output GIOA[4]/INT4 A6 110 A6 110 pins.GIOA[7:1]/INT[7:1]areinterrupt- capablepins. GIOA[5]/INT5 B5 111 B5 111 Program GIOA[6]/INT6 H3 27 H3 27 3.3VI/O 2mA-z mable IPD GIOA[7]/INT7 M1 51 M1 51 (20uA) GIOB[0] M2 M2 GIOB[1] K2 K2 GIOB[2] F2 F2 GIOB[3] W10 W10 General-purposeinput/outputpins. GIOB[4] G1 G1 GIOB[5] G2 G2 GIOB[6] J2 J2 GIOB[7] F1 F1 FlexRayController(FLEXRAY) NOTE:DeviceswithouttheFlexRayoptionshouldleaveallFlexRaypinsunconnected(NC) Program mable FRAYRX1 A15 126 3.3VI FlexRaydatareceive(channel1)pin IPD (20uA) FRAYTX1 B15 124 8mA FlexRaydatatransmit(channel1)pin 3.3VO FRAYTXEN1 B16 125 8mA FlexRaytransmitenable(channel1)pin Program mable FRAYRX2 A8 131 3.3VI FlexRaydatareceive(channel2)pin IPD(20u A) FRAYTX2 B8 129 8mA FlexRaydatatransmit(channel2)pin 3.3VO FRAYTXEN2 B9 130 8mA FlexRaytransmitenable(channel2)pin CANController(DCAN1) CAN1TX A10 50 A10 50 Program CAN1transmitpinorGIOpin mable 3.3VI/O 2mA-z CAN1RX B10 49 B10 49 IPU CAN1receivepinorGIOpin (20uA) CANController(DCAN2) CAN2TX H2 54 H2 54 Program CAN2transmitpinorGIOpin mable 3.3VI/O 2mA-z CAN2RX H1 55 H1 55 IPU CAN2receivepinorGIOpin (20uA) CANController(DCAN3) CAN3TX M18 M18 program CAN3transmitpinorGIOpin mable 3.3VI/O 2mA-z CAN3RX M19 M19 IPU CAN3receivepinorGIOpin (20uA) 24 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 SerialCommunicationsInterface(SCI)/LocalInterconnectNetwork(LIN1) LIN1RX W12 53 W12 53 Program LIN1datareceivepinorGIOpin mable 3.3VI/O 2mA-z LIN1TX V12 52 V12 52 IPU LIN1datatransmitpinorGIOpin (20uA) SerialCommunicationsInterface(SCI)/LocalInterconnectNetwork(LIN2) LIN2RX A7 140 A7 140 Program LIN2datareceivepinorGIOpin mable 3.3VI/O 2mA-z LIN2TX B7 139 B7 139 IPU LIN2datatransmitpinorGIOpin (20uA) MultibufferedSerialPeripheralInterface(MIBSPI1) MIBSPI1CLK F18 17 F18 17 4mA MIBSPI1clockpinorGIOpin MIBSPI1CS[0] R2 23 R2 23 MIBSPI1CS[1] F3 24 F3 24 MIBSPI1slavechipselectpinsorGIO 2mA-z MIBSPI1CS[2] G3 25 G3 25 Program pins MIBSPI1CS[3] J3 J3 3.3VI/O mable IPU MIBSPI1ENA G19 18 G19 18 2mA-z (20uA) MIBSPI1enablepinorGIOpin MIBSPI1datastream-Slavein/master MIBSPI1SIMO F19 14 F19 14 outpinorGIOpin 4mA MIBSPI1datastream-Slaveout/master MIBSPI1SOMI G18 13 G18 13 inpinorGIOpin MultibufferedSerialPeripheralInterface(MIBSPI3) MIBSPI3CLK V9 3 V9 3 4mA MIBSPI3clockpinorGIOpin MIBSPI3CS[0] V10 7 V10 7 MIBSPI3CS[1] V5 V5 MIBSPI3slavechipselectpinsorGIO 2mA-z MIBSPI3CS[2] B2 B2 Program pins MIBSPI3CS[3] C3 C3 3.3VI/O mable IPU MIBSPI3ENA W9 6 W9 6 2mA-z (20uA) MIBSPI3enablepinorGIOpin MIBSPI3datastream-Slavein/master MIBSPI3SIMO W8 4 W8 4 outpinorGIOpin 4mA MIBSPI3datastream-Slaveout/master MIBSPI3SOMI V8 5 V8 5 inpinorGIOpin Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 MultibufferedSerialPeripheralInterface-Parallel(MIBSPIP5) MIBSPI5CLK/DM MIBSPI5clockpinorGIOpin; H19 91 H19 91 4mA MDATA[4] multiplexedwithDMMDATA[4]pin MIBSPI5CS[0]/DM E19 92 E19 92 MDATA[5] MIBSPI5CS[1]/DM B6 93 B6 93 MDATA[6] MIBSPI5slavechipselectpinsorGIO MIBSPI5CS[2]/DM pins;multiplexedwithDMMDATApins W6 W6 2mA-z MDATA[2] MIBSPI5CS[3]/DM T12 T12 MDATA[3] MIBSPI5ENA/DM MIBSPI5enablepinorGIOpin; H18 94 H18 94 MDATA[7] multiplexedwithDMMDATA[7]pin MIBSPI5SIMO[0]/ J19 95 J19 95 Program DMMDATA[8] mable 3.3VI/O DMMDATA[9]/MIB IPU SPI5SIMO[1] E16 96 E16 96 (20uA) MIBSPI5datastream-Slavein/master outpinsorGIOpins;multiplexedwith MIBSPI5SIMO[2]/ H17 97 H17 97 DMMDATApins DMMDATA[10] MIBSPI5SIMO[3]/ G17 98 G17 98 DMMDATA[11] 4mA MIBSPI5SOMI[0]/ J18 99 J18 99 DMMDATA[12] MIBSPI5SOMI[1]/ DMMDATA[13] E17 100 E17 100 MIBSPI5datastream-Slaveout/master inpinsorGIOpins;multiplexedwith MIBSPI5SOMI[2]/ H16 101 H16 101 DMMDATApins DMMDATA[14] MIBSPI5SOMI[3]/ G16 102 G16 102 DMMDATA[15]/ MultibufferedAnalog-To-DigitalConverter(MIBADC1) Program mable AD1EVT N19 84 N19 84 3.3VI/O 2mA-z MibADC1eventinputpinorGIOpin IPD (20uA) AD1IN[0] W14 83 W14 83 AD1IN[1] V17 82 V17 82 AD1IN[2] V18 81 V18 81 AD1IN[3] T17 80 T17 80 3.3VI MibADC1analoginputpins AD1IN[4] U18 79 U18 79 AD1IN[5] R17 78 R17 78 AD1IN[6] T19 77 T19 77 AD1IN[7] V14 76 V14 76 26 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 MultibufferedAnalog-To-DigitalConverter(MIBADC2) Program mable AD2EVT W13 59 W13 59 3.3VI/O 2mA-z MibADC2eventinputpinorGIOpin IPD (20uA) AD2IN[0] V13 60 V13 60 AD2IN[1] U13 61 U13 61 AD2IN[2] U14 62 U14 62 AD2IN[3] U16 63 U16 63 3.3VI MibADC2analoginputpins AD2IN[4] U15 U15 AD2IN[5] T15 T15 AD2IN[6] R19 R19 AD2IN[7] R16 R16 MultibufferedAnalog-To-DigitalConverter-sharedsignals(MIBADC1,MIBADC2) ADSIN[8] P18 75 P18 75 ADSIN[9] W17 74 W17 74 ADSIN[10] U17 73 U17 73 ADSIN[11] U19 72 U19 72 MibADC1,MibADC2sharedanaloginput 3.3VI ADSIN[12] T16 71 T16 71 pins ADSIN[13] T18 70 T18 70 ADSIN[14] R18 69 R18 69 ADSIN[15] P19 68 P19 68 3.3-V MibADC1,MibADC2modulehigh- ADREFHI V15 66 V15 66 REF voltagereferenceinput GND MibADC1,MibADC2modulelow-voltage ADREFLO V16 65 V16 65 REF referenceinput 3.3-V MibADC1,MibADC2analogsupply VCCAD W15 67 W15 67 PWR voltage VSSAD V19 64 V19 64 VSSAD W16 W16 MibADC1,MibADC2analogground GND VSSAD W18 W18 reference VSSAD W19 W19 Oscillator(OSC) Oscillatorinputconnectionpinor OSCIN K1 20 K1 20 1.5VI externalclockinputpin OSCOUT L1 21 L1 21 1.5VO Oscillatorouptutconnectionpin Kelvin_GND L2 L2 GND Kelvin_GNDforoscillator Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 SystemModule(SYS) PoweronResetPin.Externalpower IPD PORRST W7 28 W7 28 3.3VI supplymonitorcircuitrymustasserta (100µA) power-onresetonthispin. ActiveLowBidirectionalResetpin.An externaldevicecanassertadevicereset onthispin. Theoutputbufferonthispinis IPU implementedasanopendrain(drives RST B17 85 B17 85 4mA (100µA) lowonly). 3.3VI/O Toensureanexternalresetisnot arbitrarilygenerated,TIrecommends thatanexternalpullupresistoris connectedtothispin. IPD ExternalClockPrescalermoduleoutput ECLK A12 88 A12 88 8mA (20µA) pinorGIOpin Tset/Debug(T/D) IPD JTAGtestclockpin.ClockstheJTAG TCK B18 30 B18 30 3.3VI (100uA) debuglogic. RTCK A16 35 A16 35 3.3VO JTAGreturntestclockpin.(JTAG) IPU TDI A17 34 A17 34 JTAGtestdatainpin. (100uA) TDO C18 33 C18 33 8mA IPD JTAGtestdataoutpin. 3.3VI/O (100uA) JTAGserialinputpinforcontrollingthe IPU TMS C19 36 C19 36 stateoftheCPUtestaccessport(TAP) (100uA) controller. JTAGtesthardwareresettoTAP.IEEE IPD TRST D18 29 D18 29 Standard1149-1(JTAG)Boundary-Scan (100uA) Logic 3.3VI Testenablepin.ReservedforinternalTI IPD useonly.Forproperoperation,thispin TEST U2 58 U2 58 (100uA) mustbeconnectedtoground,e.g.using aexternalresistor. ErrorSignalingModule(ESM) IPD ERROR B14 143 B14 143 3.3VI/O 8mA ErrorSignalingpin (20uA) Flash FlashTestPad1pin.Forproper operationthispinmustconnectonlytoa testpadornotbeconnectedatall[no FLTP1 J5 122 J5 122 connect(NC)].Thetestpadmustnotbe exposedinthefinalproductwhereit mightbesubjectedtoanESDevent. FlashTestPad2pin.Forproper operationthispinmustconnectonlytoa testpadornotbeconnectedatall[no FLTP2 H5 123 H5 123 connect(NC)].Thetestpadmustnotbe exposedinthefinalproductwhereit mightbesubjectedtoanESDevent. Flashpumpvoltagesupply(3.3V).This 3.3V V F8 128 F8 128 pinisrequiredforFlashread,program CCP PWR anderaseoperations. 28 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 RAMTracePortModule(RTP) RTPDATA[0] V11 V11 RTPDATA[1] U11 U11 RTPDATA[2] T10 T10 RTPDATA[3] U10 U10 RTPDATA[4] T9 T9 RTPDATA[5] U9 U9 RTPDATA[6] U8 U8 RTPDATA[7] U7 U7 RAMTracePortOutputDataSignalpins 8mA RTPDATA[8] U6 U6 orGIOpins Program RTPDATA[9] U5 U5 mable 3.3VI/O IPU RTPDATA[10] U4 U4 (20uA) RTPDATA[11] T4 T4 RTPDATA[12] V3 V3 RTPDATA[13] U3 U3 RTPDATA[14] T3 T3 RTPDATA[15] T2 T2 RTPENA U12 U12 2mA-z PacketHandshakeSignalpinorGIOpin PacketSynchronizationSignalpinor RTPSYNC T11 T11 8mA GIOpin RTPCLK W11 W11 PacketClockSignalpinorGIOpin Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 DataModificationModule(DMM) DMMDATA[0] L19 L19 DMMDatapinsorGIOpins DMMDATA[1] L18 L18 DMMDATA[2]/MIB W6 W6 2mA-z SPI5CS[2] DMMDATA[3]/MIB T12 T12 SPI5CS[3] DMMDATA[4]/MIB H19 H19 4mA SPI5CLK DMMDATA[5]/MIB E19 E19 SPI5CS[0] DMMDATA[6]/MIB B6 B6 2mA-z SPI5CS[1] DMMDATA[7]/MIB H18 H18 SPI5ENA DMMDATA[8]/MIB J19 J19 SPI5SIMO[0] Program DMMDatapinsorGIOpins;multiplexed DMMDATA[9]/MIB 3.3VI/O mable withMIBSPI5pins E16 E16 IPU SPI5SIMO[1] (20uA) DMMDATA[10]/MI H17 H17 BSPI5SIMO[2] DMMDATA[11]/MI G17 G17 BSPI5SIMO[3] 4mA DMMDATA[12]/MI J18 J18 BSPI5SOMI[0] DMMDATA[13]/MI E17 E17 BSPI5SOMI[1] DMMDATA[14]/MI H16 H16 BSPI5SOMI[2] DMMDATA[15]/MI G16 G16 BSPI5SOMI[3] DMMENA F16 F16 8mA DMMHandshakepinorGIOpin DMMSYNC J16 J16 DMMSynchronizationpinorGIOpin 2mA-z DMMCLK F17 F17 DMMClockinputpinorGIOpin 30 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 ExternalMemoryInterfaceModule(EMIF) EMIFBADD[0] D13 D13 3.3VI/O 8mA EMIFByteAddresspins EMIFBADD[1] D16 D16 EMIFDATA[0] K16 K16 EMIFDATA[1] L16 L16 EMIFDATA[2] M16 M16 EMIFDATA[3] N16 N16 EMIFDATA[4] E4 E4 EMIFDATA[5] F4 F4 EMIFDATA[6] G4 G4 Program EMIFDATA[7] K4 K4 mable 3.3VI/O 8mA EMIFDatapins EMIFDATA[8] L4 L4 IPU (20uA) EMIFDATA[9] M4 M4 EMIFDATA[10] N4 N4 EMIFDATA[11] P4 P4 EMIFDATA[12] T5 T5 EMIFDATA[13] T6 T6 EMIFDATA[14] T7 T7 EMIFDATA[15] T8 T8 EMIFADD[0] D4 D4 EMIFADD[1] D5 D5 EMIFADD[2] D6 D6 EMIFADD[3] D7 D7 EMIFADD[4] D8 D8 EMIFADD[5] D9 D9 EMIFADD[6] C4 C4 EMIFADD[7] C5 C5 EMIFADD[8] C6 C6 EMIFADD[9] C7 C7 EMIFADD[10] C8 C8 3.3VI/O 8mA EMIFAddresspins EMIFADD[11] C9 C9 EMIFADD[12] C10 C10 EMIFADD[13] C11 C11 EMIFADD[14] C12 C12 EMIFADD[15] C13 C13 EMIFADD[16] D14 D14 EMIFADD[17] C14 C14 EMIFADD[18] D15 D15 EMIFADD[19] C15 C15 EMIFADD[20] C16 C16 EMIFADD[21] C17 C17 EMIFCS[0] L17 L17 EMIFCS[1] K17 K17 3.3VI/O 8mA EMIFChipSelectpins EMIFCS[2] M17 M17 EMIFCS[3] N17 N17 Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 EMIFWE D17 D17 3.3VI/O 8mA EMIFWriteEnablepin EMIFOE D12 D12 3.3VI/O 8mA EMIFOutputEnablepin EMIFDQM[0] D10 D10 3.3VI/O 8mA EMIFByteEnablepins EMIFDQM[1] D11 D11 32 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 EmbeddedTraceModule(ETM) ETMDATA[0] R12 R12 ETMDATA[1] R13 R13 ETMDATA[2] J15 J15 ETMDATA[3] H15 H15 ETMDATA[4] G15 G15 ETMDATA[5] F15 F15 ETMDATA[6] E15 E15 ETMDATA[7] E14 E14 ETMDATA[8] E9 E9 ETMDATA[9] E8 E8 ETMDATA[10] E7 E7 ETMDATA[11] E6 E6 ETMDATA[12] E13 E13 ETMDATA[13] E12 E12 ETMDATA[14] E11 E11 ETMDATA[15] E10 E10 3.3VO 8mA ETMTraceDataoutputpins ETMDATA[16] K15 K15 ETMDATA[17] L15 L15 ETMDATA[18] M15 M15 ETMDATA[19] N15 N15 ETMDATA[20] E5 E5 ETMDATA[21] F5 F5 ETMDATA[22] G5 G5 ETMDATA[23] K5 K5 ETMDATA[24] L5 L5 ETMDATA[25] M5 M5 ETMDATA[26] N5 N5 ETMDATA[27] P5 P5 ETMDATA[28] R5 R5 ETMDATA[29] R6 R6 ETMDATA[30] R7 R7 ETMDATA[31] R8 R8 ETMTRACECTL R11 R11 ETMControlpin ETMTRACECLKO 3.3VO 8mA R10 R10 ETMClockoutputpin UT IPU ETMTRACECLKIN R9 R9 3.3VI ETMClockinputpin (20uA) Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 SupplyVoltageDigitalI/O(3.3V)andCore(1.5V) V F6 1 F6 1 CCIO V F7 15 F7 15 CCIO V F11 40 F11 40 CCIO V F12 90 F12 90 CCIO V F13 108 F13 108 CCIO V F14 119 F14 119 CCIO V G6 132 G6 132 CCIO V G14 G14 CCIO V H6 H6 CCIO V H14 H14 CCIO VCCIO J6 J6 DigitalI/Osupplypins VCCIO L14 L14 3.3V Note:AllVccIOpadsareconnectedto theBGApackagesthroughthepackage VCCIO M6 M6 PWR substrate.Thereisnotadirectballto V M14 M14 bondpadconnectionforthissupply. CCIO V N6 N6 CCIO V N14 N14 CCIO V P6 P6 CCIO V P7 P7 CCIO V P8 P8 CCIO V P9 P9 CCIO V P12 P12 CCIO V P13 P13 CCIO V P14 P14 CCIO V CCIO V F9 19 F9 19 CC V F10 31 F10 31 CC V H10 37 H10 37 CC V J14 47 J14 47 CC V K6 87 K6 87 CC DigitalCoresupplypins V K8 104 K8 104 CC Note:AllVccpadsareconnectedtothe 1.5V V K12 114 K12 114 BGApackagesthroughthepackage CC PWR substrate.Thereisnotadirectballto V K14 135 K14 135 CC bondpadconnectionforthissupply. V L6 L6 CC V M10 M10 CC V P10 P10 CC V P11 P11 CC V CC 34 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table2-9. TerminalFunctions(continued) Terminal Internal TMS570LSXXX16 TMS570LSXXX06 Type pullup/p Description Name ulldown 337 144 337 144 SupplyGround V A1 2 A1 2 SS V A2 16 A2 16 SS V A18 22 A18 22 SS V A19 32 A19 32 SS V B1 38 B1 38 SS V B19 39 B19 39 SS V H8 46 H8 46 SS V H9 86 H9 86 SS V H11 89 H11 89 SS V H12 103 H12 103 SS V J8 107 J8 107 SS V J9 115 J9 115 SS V J10 120 J10 120 SS V J11 127 J11 127 SS V J12 133 J12 133 SS V K9 136 K9 136 SS V K10 K10 SS Digitalsupplygroundreferencepins VSS K11 K11 Note:AllVsspadsareconnectedtothe GND V L8 L8 BGApackagesthroughthepackage SS substrate. V L9 L9 SS V L10 L10 SS V L11 L11 SS V L12 L12 SS V M8 M8 SS V M9 M9 SS V M11 M11 SS V M12 M12 SS V V1 V1 SS V W1 W1 SS V W2 W2 SS V V4 V4 SS V SS V SS V SS V SS V SS Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 2.6 Device Support 2.6.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,TMS570LS20216ASPGEQQ1). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed qualityandreliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production systembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PGE), the temperature range (for example, "Blank" is the commercial temperaturerange),andthedevicespeedrangeinMegaHertz. 36 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Full Part # TMS 570 LS 20 2 16 A S PGE Q Q1 R Orderable Part # S 5 LS 20 2 16 A S PGE Q Q1 R Prefix:TM S = FullyTMS Qualified P=TMPPrototype X =TMX Samples CoreTechnology: 5 = 570 Cortex R4 Architecture: LS = Lockstep CPUs Flash Memory Size: 20 = 2MB 10 = 1MB RAM Memory Size: 2 = 160kB 1 = 128kB Peripheral Set: 16 = FlexRay 06 = No FlexRay Die Revision: Blank = Initial Die A= 1st Die Revision B = 2nd Die Revision Technology/Core Voltage: S = F035 (130nm), 1.5 V nominal core voltage PackageType: PGE = 144p QFPPackage [Green] ZWT= 337p BGAPackage [Green] Temperature Range: Q = -40...+125oC Quality Designator: Q1 =Automotive Shipping Options: R =Tape and Reel A. Foractualdevicepartnumbers(P/Ns)andorderinginformation,seetheTIwebsite(http://www.ti.com). Figure2-9.DeviceNumberingConventions(A) Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 3 Reset / Abort Sources 3.1 Reset / Abort Sources The device Resets and Aborts are handled as shown in the following table. The table shows the source of the error, the system mode, the type of error response and the corresponding Error Signaling Module (ESM)channel.OnlystandardARMexceptionhandlersandESMerrorsareused. Table3-1.Reset/AbortSources ErrorSource SystemMode ErrorResponse ESMHookupgroupchannel 1)CPUtransactions Precisewriteerror(Strongly User/Privilege PreciseAbort(CPU) n/a Ordered) Precisereaderror(Deviceor User/Privilege PreciseAbort(CPU) n/a Normal) Imprecisewriteerror(Deviceor User/Privilege ImpreciseAbort(CPU) n/a Normal) Illegalinstruction User/Privilege UndefinedInstructionTrap n/a (CPU)(1) MPUaccessviolation User/Privilege Abort(CPU) n/a 2)SRAM B0TightlyCoupledMemory User/Privilege ESM 1.26 (TCM)(even)ECCsingleerror (correctable) B0TCM(even)ECCdoubleerror User/Privilege Abort(CPU),ESM=>nERROR 3.3 (non-correctable) B0TCM(even)uncorrectable User/Privilege ESM=>NMI 2.6 error(i.e.redundantaddress decode) B0TCM(even)addressbus User/Privilege ESM=>NMI 2.10 parityerror B1TCM(odd)ECCsingleerror User/Privilege ESM 1.28 (correctable) B1TCM(odd)ECCdoubleerror User/Privilege Abort(CPU),ESM=>nERROR 3.5 (non-correctable) B1TCM(odd)uncorrectable User/Privilege ESM=>NMI 2.8 error(i.e.redundantaddress decode) B1TCM(odd)addressbusparity User/Privilege ESM=>NMI 2.12 error 3)FlashwithECCINTEGRATEDINTOCPU ECCsingleerror(correctable) User/Privilege ESM 1.6 ECCdoubleerror(non- User/Privilege Abort(CPU),ESM=>nERROR 3.7 correctable) Uncorrectableerror(i.e. User/Privilege ESM=>NMI 2.4 redundantaddresstag, redundantsyndromecompare, addressbusparity,etc.) 4)DMAtransactions Externalimpreciseerroronread User/Privilege ESM 1.5 (Illegaltransactionwithok response) Externalimpreciseerroronwrite User/Privilege ESM 1.13 (Illegaltransactionwithok response) (1) TheUndefinedInstructionTRAPisNOTdetectableoutsidetheCPU.ThetrapistakenonlyiftheCodereachestheexecutestageof theCPU. 38 Reset/AbortSources Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table3-1.Reset/AbortSources(continued) ErrorSource SystemMode ErrorResponse ESMHookupgroupchannel Memoryaccesspermission User/Privilege ESM 1.2 violation Memoryparityerror User/Privilege ESM 1.3 5)DMMtransactions Externalimpreciseerroronread User/Privilege ESM 1.5 (Illegaltransactionwithok response) Externalimpreciseerroronwrite User/Privilege ESM 1.13 (Illegaltransactionwithok response) 6)AHB-APtransactions Externalimpreciseerroronread User/Privilege ESM 1.5 (Illegaltransactionwithok response) Externalimpreciseerroronwrite User/Privilege ESM 1.13 (Illegaltransactionwithok response) 7)HETTU NCNB(StronglyOrdered) User/Privilege Interrupt=>VIM n/a transactionwithslaveerror response Externalimpreciseerror(Illegal User/Privilege Interrupt=>VIM n/a transactionwithokresponse) Memoryaccesspermission User/Privilege ESM 1.9 violation Memoryparityerror User/Privilege ESM 1.8 8)NHET Memoryparityerror User/Privilege ESM 1.7 9)MibSPI MibSPI1memoryparityerror User/Privilege ESM 1.17 MibSPI3memoryparityerror User/Privilege ESM 1.18 MibSPIP5memoryparityerror User/Privilege ESM 1.24 10)MibADC MibADC1memoryparityerror User/Privilege ESM 1.19 MibADC2memoryparityerror User/Privilege ESM 1.1 11)DCAN DCAN1memoryparityerror User/Privilege ESM 1.21 DCAN2memoryparityerror User/Privilege ESM 1.23 DCAN3memoryparityerror User/Privilege ESM 1.22 12)PLL PLLsliperror User/Privilege ESM 1.10 13)Clockmonitor Clockmonitorinterrupt User/Privilege ESM 1.11 14)CCM Selftestfailure User/Privilege ESM 1.31 Comparefailure User/Privilege ESM=>NMI 2.2 15)FlexRay Memoryparityerror User/Privilege ESM 1.12 16)FlexRayTU NCNB(StronglyOrdered) User/Privilege Interrupt=>VIM n/a transactionwithslaveerror response Copyright©2010–2018,TexasInstrumentsIncorporated Reset/AbortSources 39 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table3-1.Reset/AbortSources(continued) ErrorSource SystemMode ErrorResponse ESMHookupgroupchannel Externalimpreciseerror(Illegal User/Privilege Interrupt=>VIM n/a transactionwithokresponse) Memoryaccesspermission User/Privilege ESM 1.16 violation Memoryparityerror User/Privilege ESM 1.14 17)VIM Memoryparityerror User/Privilege ESM 1.15 18)voltagemonitor VMONoutofvoltagerange n/a Reset n/a 19)CPUSelftest(LBIST) CPUSelftest(LBIST)error User/Privilege ESM 1.27 20)errorsreflectedintheSYSESRregister Power-UpReset;VCCoutof n/a Reset n/a voltagerange Oscillatorfail/PLLslip(2) n/a Reset n/a Watchdogtimelimitexceeded n/a Reset n/a CPUReset n/a Reset n/a SoftwareReset n/a Reset n/a ExternalReset n/a Reset n/a (2) Oscillatorfail/PLLslipcanbeconfiguredinthesystemregisterPLLCTL1togenerateareset. 40 Reset/AbortSources Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 4 Peripherals 4.1 Error Signaling Module (ESM) The Error Signaling Module (ESM) is used to indicate a severe device failure via interrupts and the external ERROR pin. The error pin is normally used by an external device to either reset the controller and/orkeepthesysteminafailsafestate. The ESM module consists of three error groups with 32 inputs each. The generation of the interrupts and the activation of the ERROR Pin is shown in the following table. The next table shows the ESM error sourcesandtheircorrespondinggroupandchannelnumbers. Table4-1.ESMGroups ErrorGroup Interrupt,Level InfluenceonERRORpin Group1 maskable,low/high configurable Group2 non-maskable,high fixed Group3 none,none fixed Table4-2.ESMAssignments ERRORSources Group Channels Reserved Group1 0 MibADC2-parity Group1 1 DMA-MPU Group1 2 DMA-parity Group1 3 Reserved Group1 4 DMA/DMM/AHB-AP-imprecisereaderror Group1 5 Flash(ATCM)-correctableerror Group1 6 NHET-parity Group1 7 HETTU-parity Group1 8 HETTU-MPU Group1 9 PLL-slip Group1 10 ClockMonitor-interrupt Group1 11 FlexRay-parity Group1 12 DMA/DMM/AHB-AP-imprecisewriteerror Group1 13 FlexRayTU-parity Group1 14 VIMRAM-parity Group1 15 FlexRayTU-MPU Group1 16 MibSPI1-parity Group1 17 MibSPI3-parity Group1 18 MibADC1-parity Group1 19 Reserved Group1 20 DCAN1-parity Group1 21 DCAN3-parity Group1 22 DCAN2-parity Group1 23 MibSPIP5-parity Group1 24 Reserved Group1 25 RAMevenbank(B0TCM)-correctableerror Group1 26 CPU-selftest Group1 27 RAModdbank(B1TCM)-correctableerror Group1 28 Reserved Group1 29 Reserved Group1 30 Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 41 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table4-2.ESMAssignments(continued) ERRORSources Group Channels CCM-R4-selftest Group1 31 Reserved Group2 0 Reserved Group2 1 CCM-R4-compare Group2 2 Reserved Group2 3 Flash(ATCM)-uncorrectableerror Group2 4 Reserved Group2 5 RAMevenbank(B0TCM)-uncorrectableerror Group2 6 Reserved Group2 7 RAModdbank(B1TCM)-uncorrectableerror Group2 8 Reserved Group2 9 RAMevenbank(B0TCM)-addressbusparityerror Group2 10 Reserved Group2 11 RAModdbank(B1TCM)-addressbusparityerror Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 Flash(ATCM)-ECClivelockdetect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 Reserved Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 Reserved Group3 0 Reserved Group3 1 Reserved Group3 2 RAMevenbank(B0TCM)-ECCuncorrectableerror Group3 3 Reserved Group3 4 RAModdbank(B1TCM)-ECCuncorrectableerror Group3 5 Reserved Group3 6 Flash(ATCM)-ECCuncorrectableerror Group3 7 Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11 Reserved Group3 12 Reserved Group3 13 42 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table4-2.ESMAssignments(continued) ERRORSources Group Channels Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31 Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 43 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 4.2 Direct Memory Access (DMA) The direct-memory access (DMA) controller transfers data to and from any specified location in the device memorymap.TheDMAsupportsdatatransferforbothon-chipmemoriesandperipherals. The DMA controller on this device supports 16 channels and 32 request lines. Each of the 32 DMA requests are assigned by default to one of the 16 available channels. For DMA requests multiplexed between multiple sources, the DMA controller cannot differentiate between the multiple sources and the user has to ensure that multiple sources are not enabled at the same time. Please refer to the DMA SpecificationintheTRMformoredetails. TheDMArequestconfigurationisshowninthefollowingtable. Table4-3.DMARequestLineConnection Modules DMARequestSources DMARequest MIBSPI1 MIBSPI1[1](1) DMAREQ[0] MIBSPI1 MIBSPI1[0](2) DMAREQ[1] Reserved Reserved DMAREQ[2] Reserved Reserved DMAREQ[3] MIBSPI1/MIBSPI3/DCAN2 MIBSPI1[2]/MIBSPI3[2]/DCAN2IF3 DMAREQ[4] MIBSPI1/MIBSPI3/DCAN2 MIBSPI1[3]/MIBSPI3[3]/DCAN2IF2 DMAREQ[5] MIBSPIP5/DCAN1 MIBSPIP5[2]/DCAN1IF2 DMAREQ[6] MIBADC1/MIBSPIP5 MIBADC1event/MIBSPIP5[3] DMAREQ[7] MIBSPI1/MIBSPI3/DCAN1 MIBSPI1[4]/MIBSPI3[4]/DCAN1IF1 DMAREQ[8] MIBSPI1/MIBSPI3/DCAN2 MIBSPI1[5]/MIBSPI3[5]/DCAN2IF1 DMAREQ[9] MIBADC1/MIBSPIP5 MIBADC1G1/MIBSPIP5[4] DMAREQ[10] MIBADC1/MIBSPIP5 MIBADC1G2/MIBSPIP5[5] DMAREQ[11] RTI/MIBSPI1/MIBSPI3 RTIDMAREQ0/MIBSPI1[6]/MIBSPI3[6] DMAREQ[12] RTI/MIBSPI1/MIBSPI3 RTIDMAREQ1/MIBSPI1[7]/MIBSPI3[7] DMAREQ[13] MIBADC2/MIBSPI3/MIBSPIP5 MIBADC2event/MIBSPI3[1](1)/MIBSPIP5[6] DMAREQ[14] MIBSPI3/MIBSPIP5 MIBSPI3[0]†/MIBSPIP5[7] DMAREQ[15] MIBADC2/MIBSPI1/MIBSPI3/DCAN1 MIBADC2G1/MIBSPI1[8]/MIBSPI3[8]/DCAN1 DMAREQ[16] IF3 MIBADC2/MIBSPI1/MIBSPI3/DCAN3 MIBADC2G2/MIBSPI1[9]/MIBSPI3[9]/DCAN3 DMAREQ[17] IF1 RTI/MIBSPIP5 RTIDMAREQ2/MIBSPIP5[8] DMAREQ[18] RTI/MIBSPIP5 RTIDMAREQ3/MIBSPIP5[9] DMAREQ[19] LIN2/NHET/DCAN3 LIN2receive/NHETDMAREQ[4]/DCAN3IF2 DMAREQ[20] LIN2/NHET/DCAN3 LIN2transmit/NHETDMAREQ[5]/DCAN3IF3 DMAREQ[21] MIBSPI1/MIBSPI3/MIBSPIP5 MIBSPI1[10]/MIBSPI3[10]/MIBSPIP5[10] DMAREQ[22] MIBSPI1/MIBSPI3/MIBSPIP5 MIBSPI1[11]/MIBSPI3[11]/MIBSPIP5[11] DMAREQ[23] NHET/MIBSPIP5 NHETDMAREQ[6]/MIBSPIP5[12] DMAREQ[24] NHET/MIBSPIP5 NHETDMAREQ[7]/MIBSPIP5[13] DMAREQ[25] CRC/MIBSPI1/MIBSPI3 CRCDMAREQ[0]/MIBSPI1[12]/MIBSPI3[12] DMAREQ[26] CRC/MIBSPI1/MIBSPI3 CRCDMAREQ[1]/MIBSPI1[13]/MIBSPI3[13] DMAREQ[27] LIN1/MIBSPIP5 LIN1receive/MIBSPIP5[14] DMAREQ[28] LIN1/MIBSPIP5 LIN1transmit/MIBSPIP5[15] DMAREQ[29] MIBSPI1/MIBSPI3/MIBSPIP5 MIBSPI1[14]/MIBSPI3[14]/MIBSPIP5[1](1) DMAREQ[30] MIBSPI1/MIBSPI3/MIBSPIP5 MIBSPI1[15]/MIBSPI3[15]/MIBSPIP5[0](2) DMAREQ[31] (1) SPI1,SPI3,SPI5receiveinstandardSPI/compatibilitymode (2) SPI1,SPI3,SPI5transmitinstandardSPI/compatibilitymode 44 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 4.3 High End Timer Transfer Unit (HET-TU) The High End Timer Transfer Unit (HET-TU) is a local Direct Memory Access (DMA) module. It is specifically designed to transfer High End Timer (NHET) data to (or from) the CPU data SRAM . The HET software controls which HET instructions generate transfer requests to the transfer unit. More information about the NHET and the HET-TU can be found in the technical reference manual (TRM). The HET-TU supports8channels. TheHET-TUrequestassignmentisshowninthefollowingtable. Table4-4.NHETRequestLineConnection Modules RequestSource HETTRANSFERUNITRequest NHET HTUREQ[0] HETTUDCP[0] NHET HTUREQ[1] HETTUDCP[1] NHET HTUREQ[2] HETTUDCP[2] NHET HTUREQ[3] HETTUDCP[3] NHET HTUREQ[4] HETTUDCP[4] NHET HTUREQ[5] HETTUDCP[5] NHET HTUREQ[6] HETTUDCP[6] NHET HTUREQ[7] HETTUDCP[7] Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 45 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 4.4 Vectored Interrupt Manager (VIM) The Vectored Interrupt Manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on the device. Interrupt requests originating from the device modules (i.e., SPI, LIN, SCI, etc.) are assigned to channels within the 64-channel VIM. Programming multiple interrupt sources to the same VIM channel effectively shares the VIM channel between sources. The VIM request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can beprogrammedintheVIMtobeofeithertype: • Fast interrupt request (FIQ)- The FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts (NMFI). • Normalinterruptrequest(IRQ) The VIM prioritizes interrupts, whose precedence of request channels decrease with ascending channel order in the VIM (0 [highest] and 64[lowest] priority). For VIM default mapping, channel priorities, and their associated modules see the table below. More information on the VIM can be found in the technical referencemanual(TRM). Table4-5.InterruptRequestAssignments Modules InterruptSources DefaultVIMInterruptRequest ESM ESMHighlevelinterrupt(NMI) 0 Reserved (NMI) 1 RTI RTIcompareinterrupt0 2 RTI RTIcompareinterrupt1 3 RTI RTIcompareinterrupt2 4 RTI RTIcompareinterrupt3 5 RTI RTIoverflowinterrupt0 6 RTI RTIoverflowinterrupt1 7 RTI RTItimebase 8 GIO GIOinterruptA 9 NHET NHETlevel1interrupt 10 HETTU HETTUlevel1interrupt 11 MIBSPI1 MIBSPI1level0interrupt 12 LIN1(incl.SCI) LIN1level0interrupt 13 MIBADC1 MIBADC1eventgroupinterrupt 14 MIBADC1 MIBADC1swgroup1interrupt 15 DCAN1 DCAN1level0interrupt 16 Reserved Reserved 17 FlexRay FlexRaylevel0interrupt 18 CRC CRCInterrupt 19 ESM ESMLowlevelinterrupt 20 SYSTEM Softwareinterrupt(SSI) 21 CPU PMUInterrupt 22 GIO GIOinterruptB 23 NHET NHETlevel2interrupt 24 HETTU HETTUlevel2interrupt 25 MIBSPI1 MIBSPI1level1interrupt 26 LIN1(incl.SCI) LIN1level1interrupt 27 MIBADC1 MIBADC1swgroup2interrupt 28 DCAN1 DCAN1level1interrupt 29 Reserved Reserved 30 MIBADC1 MIBADC1magnitudeinterrupt 31 46 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table4-5.InterruptRequestAssignments(continued) Modules InterruptSources DefaultVIMInterruptRequest FlexRay FlexRaylevel1interrupt 32 DMA FTCAinterrupt 33 DMA LFSAinterrupt 34 DCAN2 DCAN2level0interrupt 35 DMM DMMlevel0interrupt 36 MIBSPI3 MIBSPI3level0interrupt 37 MIBSPI3 MIBSPI3level1interrupt 38 DMA HBCAinterrupt 39 DMA BTCAinterrupt 40 Reserved Reserved 41 DCAN2 DCAN2level1interrupt 42 DMM DMMlevel1interrupt 43 DCAN1 DCAN1IF3interrupt 44 DCAN3 DCAN3level0interrupt 45 DCAN2 DCAN2IF3interrupt 46 FPU FPUinterrupt 47 FlexRayTU FlexRayTUTransferStatusinterrupt 48 LIN2(incl.SCI) LIN2level0interrupt 49 MIBADC2 MIBADC2eventgroupinterrupt 50 MIBADC2 MIBADC2swgroup1interrupt 51 FlexRay FlexRayT0Cinterrupt 52 MIBSPIP5 MIBSPIP5level0interrupt 53 LIN2(incl.SCI) LIN2level1interrupt 54 DCAN3 DCAN3level1interrupt 55 MIBSPIP5 MIBSPIP5level1interrupt 56 MIBADC2 MIBADC2swgroup2interrupt 57 FlexRayTU FlexRayTUErrorinterrupt 58 MIBADC2 MIBADC2magnitudeinterrupt 59 DCAN3 DCAN3IF3interrupt 60 Reserved Reserved 61 FlexRay FlexRayT1Cinterrupt 62 Reserved Reserved 63 Note:Addresslocation0x00000000intheVIMRAMisreservedforthephantominterruptISRentry. Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 47 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 4.5 MIBADC Event Trigger Sources All three conversion groups can be configured for event-triggered operation, providing up to three event triggeredgroups. The trigger source and polarity can be selected individually for group 1, group 2 and the event group from the options identified in the first table following for MibADC1 and in the second table following for MibADC2. Table4-6.MIBADC1EventTriggerSources Event# SOURCESELECTBITSforG1,G2or Hookup EVENT(G1SRC[2:0],G2SRC[2:0]or EVSRC[2:0]) 1 000 AD1EVT 2 001 NHET[8] 3 010 NHET[10] 4 011 RTIcompare0 5 100 NHET[17] 6 101 NHET[19] 7 110 GIOB[0] 8 111 GIOB[1] NOTE TheTriggerispresent,evenifthepinisnotavailable. Table4-7.MIBADC2EventTriggerSources Event# SOURCESELECTBITSforG1,G2or Hookup EVENT(G1SRC[2:0],G2SRC[2:0]or EVSRC[2:0]) 1 000 AD2EVT 2 001 NHET[8] 3 010 NHET[10] 4 011 RTIcompare0 5 100 NHET[17] 6 101 NHET[19] 7 110 GIOB[0] 8 111 GIOB[1] NOTE TheTriggerispresent,evenifthepinisnotavailable. The application can generate the trigger condition using these signals by configuring the corresponding device pins as input pins and driving them from an external source, or by configuring them as output pins anddrivingthembysoftware.Thepindoesn'thavetobepresentonthepackagetobeabletobeusedas atrigger. The interrupt request signals (RTI compare 0) are driven HIGH when the interrupt condition occurs. So if the ADC is required to be triggered on the interrupt being asserted, select the rising edge for this trigger source. The ADC can be still triggered using the falling edge on the interrupt line. In this case, the falling edgeoccurswhentheinterruptlineisdeasserted. 48 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 4.6 MIBSPI 4.6.1 MIBSPI Event Trigger Sources The Multi-buffered Serial Peripheral Interfaces (MIBSPIs) have a programmable buffer memory that enables data transmission to be completed without CPU intervention. The buffers are combined in different Transfer Groups (TGs) that can be triggered by external events such as I/O activity, timers or by theinternaltickcounter.Theinternaltickcountersupportstheperiodictriggerofevents.Eachbufferofthe MibSPI can be associated with different DMA channels in different TGs, allowing the user to move data betweeninternalmemoryandanexternalslavewithminimalCPUinteraction. Table4-8.MIBSPI1EventTriggerSources Event TGxCTRLTRIGSRC[3:0] Hookup Disabled 0000 Notriggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 InternalTickcounter Table4-9.MIBSPI3EventTriggerSources Event TGxCTRLTRIGSRC[3:0] Hookup Disabled 0000 Notriggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 InternalTickcounter Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 49 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table4-10.MIBSPI5EventTriggerSources Event TGxCTRLTRIGSRC[3:0] Hookup Disabled 0000 Notriggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 InternalTickcounter 4.6.2 MIBSPIP5/DMM Pin Multiplexing The multiplexing of MIBSPIP5 and DMM pins are controlled by the status of the MIBSPIP5 module and the DMM module. The pins will have DMM functionality if the DMM module is enabled and the MIBSPIP5 module is disabled; if the MIBSPIP5 is enabled the pins will have MIBSPI functionality, regardless of the DMM module status. DMMCLK, DMMSYNC, DMMENA and DMMDATA[1:0] are always functional independent of the MIBSPIP5 configuration because they are not multiplexed. The related pin numbers can be found in the MIBSPI5 and the DMM section of the Terminal Functions chapter. The following table showstheMIBSPI5andDMMDatapinmultiplexing. Table4-11.MIBSPIP5PinMultiplexing MIBSPIP5enabled DMMenabled&MIBSPIP5disabled MIBSPI5CLK DMMDATA[4] MIBSPI5CS[0] DMMDATA[5] MIBSPI5CS[1] DMMDATA[6] MIBSPI5CS[2] DMMDATA[2] MIBSPI5CS[3] DMMDATA[3] MIBSPI5ENA DMMDATA[7] MIBSPI5SIMO[0] DMMDATA[8] MIBSPI5SIMO[1] DMMDATA[9] MIBSPI5SIMO[2] DMMDATA[10] MIBSPI5SIMO[3] DMMDATA[11] MIBSPI5SOMI[0] DMMDATA[12] MIBSPI5SOMI[1] DMMDATA[13] MIBSPI5SOMI[2] DMMDATA[14] MIBSPI5SOMI[3] DMMDATA[15] 50 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 4.7 ETM ThedevicecontainsanARMCortex™-R4FExternalTraceMacrocell(ETM-R4)witha32bitdataport.The ETM-R4 module is connected to a Test Port Interface Unit (TPIU) with a 32bit data bus. The ETM-R4 is CoreSight compliant and follows the ARM ETM v3 specification; for more details see ARM CoreSight™ ETM-R4TRMspecificationRevr0p0.TheETM-R4supports"halfrateclocking"only. The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The selectionisdonebytheEXTCTRLOUT[1:0]controlbitsoftheTPIU;thedefaultis'00'. Table4-12.ETMTRACECLKINSelection EXTCTRLOUT[1:0] TPIU/TRACECLKIN 00 tied-zero 01 VCLK 10 ETMTRACECLKIN 11 tied-zero Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 51 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 4.8 Debug Scan Chains The device contains an ICEPICK module to access the debug scan chains. Debug scan chain #0 handles the access to the CPU, to the ETM-R4 (External Trace Macrocell), to the POM (Parameter Overlay Module) and to the TPIU (Test Port Interface Unit). Debug scan chain #1 handles the access to the Ram Trace Port (RTP) and the Data Modification Module (DMM) which each incorporate a dedicated TAP (Test Access Port) controller. Each module is selected via its scan chain number. The IcePick scan ID is 0x80206D05,whichisthesamenumberasthedeviceID. DAP CPU ETM POM TPIU debugscanchain#0 CoreSight K C PI E C I TDI RTP TAP RTP 0 TDO DMM TAP DMM 1 debug scan chain #1 Boundary Scan boundaryscaninterface Figure4-1.DebugScanChains 4.8.1 JTAG The32bitJTAGIDcodeforthisdeviceis0x0B7B302F. 52 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 4.9 CCM 4.9.1 Dual Core Implementation The microcontroller has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-R4 (Core Compare Module). To avoid common mode impacts the signals of the CPUs to be comparedaredelayedinadifferentwayasshowninthefollowingfigure. CCM-R4 1.5cycledelay CCM-R4 Compare CPU1CLK Compare Error CPU1 CPU2 1.5cycledelay CPU2CLK Figure4-2.DualCoreImplementation 4.9.2 CCM-R4 To avoid an erroneous CCM-R4 compare error, the application software must ensure that the CPU registers of both CPUs are initialized with the same values before the 1st function call or other operation that pushes the CPU registers onto the stack. All CCM-R4 error forcing test modes are limited to 100MHz HCLKspeed. Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 53 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 4.10 LPM TMS570 Platform devices support multiple low power modes. These different modes allow the user to trade-off the amount of current consumption during low power mode versus functionality and wake-up time. Supported Low Power modes on this devices are Doze, Snooze and Sleep; for detailed description please refertotheArchitecturesectionoftheTechnicalReferenceManual. 4.11 Voltage Monitor A voltage monitor has been implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. It also reduces the risk of corrupting memory or glitches on I/O pins during power-up, power-down or brown outs. The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the device is held in reset when the voltage supplies are out of range. The voltage monitor thresholds can be foundintheVmonsectionofthedeviceelectricalspecifications. When the voltage monitor detects a low voltage on the I/O supply, it will assert a reset. When the voltage monitordetectsalowvoltageonthecoresupply,itasynchronouslymakesalloutputpinshighimpedance, andassertsareset.Thevoltagemonitorisdisabledwhenthedeviceisinhaltmode. Thevoltagemonitorhasthreefilterfunctions: • Itrejectsshortlow-goingglitchesonthe PORRSTpin • ItrejectsnoiseontheVCCIOsupply • ItrejectsnoiseontheVCCsupply Please note that such glitches on VCC and VCCIO could still corrupt the system depending on many factors. The width of noise that can be filtered by the voltage monitor on the VCC and VCCIO supplies is shown in the table below. Glitches less than MIN will be filtered out, glitches greater than MAX are guaranteed to generate a reset. The duration of glitches that will be filtered on the PORRST pin can be foundinTable7-6,TimingRequirementsfor PORRST. Table4-13.VMONSupplyGlitchFilterCapability Parameter Min Max WidthofglitchonVCCthatcanbefilteredout 300ns 1us WidthofglitchonVCCIOthatcanbefilteredout 300ns 1us 4.12 CRC MCRC Controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the integrity of memory system. A signature representing the contents of the memory is obtained when the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a pre- determined good signature value. MCRC controller provides up to four channels to perform CRC calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into data trace mode. In data trace mode, MCRC controller compresses each data being read throughtheCPUreaddatabus. When using the MCRC module in PSA mode while ECC is enabled, bus masters (e.g. FTU, HTU, DMA or CPU)shouldnotwritetothedataRAM(TCRAM)toavoidcorruptingthePSAvalue. 4.13 System Module Access Thesystemmoduleaccessmodesandaccessrightsareshowninthefollowingtable. 54 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table4-14.SystemModuleAccess Domain Module AccessModeUsedbyModule AccessRightsRequiredto AccesstheModuleRAMS System VIM n/a privilegemode(RWP) System RTP n/a privilegemode(RWP) System DMA usermode privilegemode(RWP) Peripheral HTU privilegemode privilegemode(RWP) Peripheral FTU user&privilegemode user&privilegemode(RW) 4.14 Debug ROM TheDebugROMstoresthelocationofthecomponentsontheDebugAPBbus. Table4-15.DebugROMTable Address Description Value ComponentsTable 0x000 pointertoCortex-R4 0x00001003 0x000 ETM 0x00002003 0x000 TPIU 0x00003003 0x000 POM 0x00004003 0x001 endoftable 0x00000000 Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 55 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 4.15 CPU Self Test Controller: STC / LBIST The CPU Self Test Controller (STC) is used to test the ARM CPU core using a Deterministic Logic BIST (LBIST) Controller as the test engine. The STC has the capability of dividing the complete test run into smaller independent test sets (intervals). The test coverage and number of test execution cycles for each testintervalisshowninthetablebelow. ThemaximumclockratefortheSTC/LBISTis: • 53.333MHzwhenHCLK=160MHz/VCLK=80MHzonBGApackage • 50MHzwhenHCLK=100MHz/VCLK=100MHzonQFPandBGApackages • 46.666MHzwhenHCLK=140MHz/VCLK=70MHzonQFPandBGApackages In order to achieve the proper clock rate during CPU self test a STC clock divider has been implemented. The clock divider is set by the CLKDIV bits in STCCLKDIV register in the secondary system module frame atlocation0xFFFFE108.ThedefaultvalueoftheCPUSelfTestLBISTclockdividerissetto'divide-by-1’. NOTE The supply current while performing CPU self test is different than the device operating modecurrent.ThesevaluescanbefoundintheI sectionofSection6.4. cc Table4-16.STC/LBISTTestCoverageandDuration Intervals TestCoverage TestCycles(STCClockCycles) 0 0% 0 1 57.14% 1,555 2 65.82% 3,108 3 70.56% 4,661 4 73.56% 6,214 5 76.06% 7,767 6 78.07% 9,320 7 79.62% 10,873 8 80.92% 12,426 9 82.1% 13,979 10 82.94% 15,532 11 83.76% 17,085 12 84.51% 18,638 13 85.12% 20,191 14 85.62% 21,744 15 86.19% 23,297 16 86.56% 24,850 17 86.97% 26,403 18 87.33% 27,956 19 87.67% 29,509 20 88.01% 31,062 21 88.31% 32,615 22 88.58% 34,168 23 88.87% 35,721 24 89.11% 37,274 25 89.34% 38,827 26 89.59% 40,380 27 89.82% 41,933 28 90.05% 43,486 56 Peripherals Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table4-16.STC/LBISTTestCoverageandDuration(continued) Intervals TestCoverage TestCycles(STCClockCycles) 29 90.26% 45,039 30 90.46% 46,592 31 90.64% 48,145 32 90.84% 49,698 Copyright©2010–2018,TexasInstrumentsIncorporated Peripherals 57 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 5 Device Registers 5.1 Device Identification Code Register The device identification code register identifies several aspects of the device including the silicon version. The details of the device identification code register are shown in Figure 5-1. The device identification coderegistervalueforthisdeviceis: • Rev0=0x80206D05 • RevA=0x80206D0D Figure5-1.DeviceIDBitAllocationRegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUEID 16 R-1 R-00000000010000 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TECH I/O PERIP FLASHECC RAM VERSION 1 0 1 VOLT HERA ECC AGE L PARIT Y R-011 R-0 R-1 R-10 R-1 R-1 R-1 R-0 R-1 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicedependent Table5-1.DeviceIDBitAllocationRegisterFieldDescriptions Bit Field Value Description 31 CP15 Indicatesthepresenceofcoprocessor15 0 CP15notpresent 1 CP15present 30-17 UNIQUEID 1 Siliconversion(revision)bitsThisbitfieldholdsauniquenumberforadedicateddeviceconfiguration (die). 16-13 TECH Processtechnologyonwhichthedeviceismanufactured. 0000 C05 0001 F05 0010 C035 0011 F035 Others Reserved 12 I/O I/Ovoltageofthedevice. VOLTAGE 0 I/Oare3.3v 1 I/Oare5v 11 PERIPHERA PeripheralParity LPARITY 0 Noparityonperipherals 1 Parityonperipherals 10-9 FLASHECC FlashECC 00 Noerrordetection/correction 01 Programmemorywithparity 10 ProgrammemorywithECC 11 Reserved 8 RAMECC IndicatesifRAMmemoryECCispresent. 0 NoECCimplemented 1 ECCimplemented 7-3 REVISION RevisionoftheDevice. 58 DeviceRegisters Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table5-1.DeviceIDBitAllocationRegisterFieldDescriptions(continued) Bit Field Value Description 2-0 101 TheplatformfamilyIDisalways0b101 Copyright©2010–2018,TexasInstrumentsIncorporated DeviceRegisters 59 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 5.2 Die-ID Registers The two registers (DIEIDL and DIEIDH) form a 64-bit number that contains information about the device’s die lot number, wafer number and X, Y wafer coordinates. The die identification information will vary from unit to unit. This information is programmed by TI as part of the initial device test procedure. The data formatoftheDie-IDregistersisshownhere. Figure5-2.DIEIDLRegister(Location:0xFFFFFF7C) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOT(LOWER10BITS) WAFER# R-D R-D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 YWAFERCOORDINATES XWAFERCOORDINATES R-D R-D LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicedependent Figure5-3.DIEIDHRegister(Location:0xFFFFFF80) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LOT#(UPPER14BITS) R-D LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicedependent 60 DeviceRegisters Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 5.3 PLL Registers The default values for the PLL (Phase Locked Loop) control registers are shown in this section. PLLCTL1 and PLLCTL2 are used to configure PLL1 (F035 FMzPLL) and PLLCTL3 is used to configure PLL2 (F035 FPLL). Figure5-4.PLLCTL1Register(Location:0xFFFFFF70) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ROS BPOS[1:0] PLLDIV[4:0] ROF RESV REFCLKDIV[5:0] R/WP- R/WP-01 R/WP-01111 R/WP- R-0 R/WP-000010 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLLMUL[15:0] R/WP-0101111100000000 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicespecific PLLCTL1Default=0x2F025F00 Figure5-5.PLLCTL2Register(Location:0xFFFFFF74) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FMEN SPREADINGRATE[8:0] RESV EWADJ[8:4] A R/WP- R/WP-111111111 R-0 R/WP-00000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BWADJ[3:0] ODPLL SPR_AMOUNT[8:0] R/WP-0111 R/WP-001 R/WP-000000000 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicespecific PLLCTL2Default=0x7FC07200 NOTE There are several combinations of the modulation depth and modulation frequency that are notallowed.ValidsettingsforthisdeviceincludethelistinTable7-2. Figure5-6.PLLCTL3Register(Location:0xFFFFE100) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED OSC RESERVED DIV R/W-000000000 R/WP- R/W-000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PLL_MUL[3:0] RESERVED PLL_DIV[2:0] R/W-000000 R/WP-011 R/W-00000 R/WP111 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicespecific PLLCTL3Default=0x00000307 Copyright©2010–2018,TexasInstrumentsIncorporated DeviceRegisters 61 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 6 Device Electrical Specifications 6.1 Operating Conditions 6.2 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)(1) Supplyvoltageranges V (2) -0.3Vto2.1V CC V ,V ,V (Flashpump)(2) -0.3Vto4.1V CCIO CCAD CCP Inputvoltagerange Allinputpins -0.3Vto4.1V Inputclampcurrent I (V<0orV>V ) ±20mA IK I I CCIO AllpinsexceptAD1IN[7:0],AD2IN[7:0],ADSIN[15:8] I (V<0orV>V ) IK I I CCAD AD1IN[7:0],AD2IN[7:0],ADSIN[15:8] ±10mA total ±40mA Operatingfree-airtemperatureranges,T Qversion -40°Cto125°C A Operatingjunctiontemperaturerange,T -40°Cto150°C J Storagetemperaturerange,T -65°Cto150°C stg (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability (2) Allvoltagevaluesarewithrespecttotheirassociatedgrounds. 6.3 Device Recommended Operating Conditions(1) MIN NOM MAX Unit V Digitallogicsupplyvoltage(Core) 1.35 1.5 1.65 V CC V Digitallogicsupplyvoltage(I/O) 3 3.3 3.6 V CCIO V MibADCsupplyvoltage 3 3.3 3.6 V CCAD V Flashpumpsupplyvoltage 3 3.3 3.6 V CCP V Digitallogicsupplyground 0 V SS V MibADCsupplyground -0.1 0.1 V SSAD T Operatingfree-airtemperature Qversion -40 125 °C A T Operatingjunctiontemperature -40 150 °C J (1) AllvoltagesarewithrespecttoV exceptV iswithrespecttoV . SS CCAD SSAD 62 DeviceElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 6.4 Electrical Characteristics Over Operating Free-Air Temperature Range(1) Parameter TestConditions MIN TYP MAX Unit V Inputhysteresis 0.15 V hys V Low-levelinput Allinputs(2) -0.3 0.8 V IL voltage V High-levelinput Allinputs 2 V + V IH CCIO voltage 0.3 V Low-leveloutputvoltage I =I MAX 0.2 V OL OL OL V CCIO I =50µA 0.2 OL V High-leveloutputvoltage I =I MAX 0.8 V OH OH OH V CCIO I =50µA V - OH CCIO 0.2 V Low-levelinput OSCIN -0.3 0.2V V ILoscin CC voltage V High-levelinput OSCIN 0.8V V + V IHoscin CC CC voltage 0.3 V Voltage VCClow 1.0 1.2 1.35 V MON monitoring VCChigh 1.7 2 2.38 threshold VCCIOlow 2.0 2.4 3.0 I Inputclampcurrent V <V -0.3orV >V +0.3 -2 2 mA IC I SSIO I CCIO I Inputcurrent I Pulldown V =V -1 1 µA I IL I SS (I/Opins) I Pulldown20uA V =V 5 40 IH I CCIO I Pulldown100uA V =V 40 195 IH I CCIO I Pullup20uA V =V -40 -5 IL I SS I Pullup100uA V =V -195 -40 IL I SS I Pullup V =V -1 1 IH I CCIO Allotherpins Nopulluporpulldown -1 1 (1) Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive. (2) ThisdoesnotapplytoPORRSTpin. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceElectricalSpecifications 63 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Electrical Characteristics Over Operating Free-Air Temperature Range(1) (continued) Parameter TestConditions MIN TYP MAX Unit I Low-leveloutput TDO V =V MAX 8 mA OL OL OL current TDI TMS RTCK ECLK FRAYTX1 FRAYTXEN1 FRAYTX2 FRAYTXEN2 DMMENA ETMTRACECTL ETMTRACECLKOUT ETMDATA[31:0] RTPSYNC RTPCLK RTPDATA[15:0] EMIFWE EMIFOE EMIFCS[3:0] EMIFDATA[15:0] EMIFADD[21:0] EMIFBADD[1:0] EMIFDQM[1:0] ERROR I Low-leveloutput RST V =V MAX 4 mA OL OL OL current MIBSPI1CLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI MIBSPI5CLK MIBSPI5SIMO[3:0] MIBSPI5SOMI[3:0] DMMDATA[15:8] DMMDATA[4] Allotheroutputpins 2 64 DeviceElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Electrical Characteristics Over Operating Free-Air Temperature Range(1) (continued) Parameter TestConditions MIN TYP MAX Unit I High-level TDO V =V MIN -8 mA OH OH OH outputcurrent TDI TMS RTCK ECLK FRAYRX1 FRAYTX1 FRAYTXEN1 FRAYRX2 FRAYTX2 FRAYTXEN2 ETMTRACECTL ETMTRACECLKOUT ETMDATA[31:0] RTPSYNC RTPCLK RTPDATA[15:0] DMMENA EMIFWE EMIFOE EMIFCS[3:0] EMIFDATA[15:0] EMIFADD[21:0] EMIFBADD[1:0] EMIFDQM[1:0] ERROR I High-level RST V =V MIN -4 mA OH OH OH outputcurrent MIBSPI1CLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI MIBSPI5CLK MIBSPI5SIMO[3:0] MIBSPI5SOMI[3:0] DMMDATA[15:8] DMMDATA[4] Allotheroutputpins -2 Copyright©2010–2018,TexasInstrumentsIncorporated DeviceElectricalSpecifications 65 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Electrical Characteristics Over Operating Free-Air Temperature Range(1) (continued) Parameter TestConditions MIN TYP MAX Unit I (3) V Digital Allpackages HCLK=100MHz,VCLK=100MHz 350 mA CC CC supplycurrent HCLK=140MHz,VCLK=70MHz 390 mA (Operating mode) BGApackages HCLK=160MHz,VCLK=80MHz 430 mA V Digital Allpackages STCCLK=46.666MHz Peak 510 mA CC supplycurrent STCCLK=50.0MHz Peak 540 mA (CPUselftest mode: BGApackages STCCLK=53.333MHz Peak 580 mA LBIST)(4)(5) V Digital Allpackages HCLK=80MHz, Peak 340 mA CC supplycurrent VCLK=40MHz (Memselftest HCLK=100MHz, Peak 430 mA mode: VLCK=100MHz PBIST)(4)(6) V Digitalsupplycurrent(dozemode) OSCIN=6MHz,V =1.65V(7) 35 mA CC CC V Digitalsupplycurrent(snoozemode) Allfrequencies,V =1.65V(7) 30 mA CC CC V Digitalsupplycurrent(sleepmode) Allfrequencies,V =1.65V(7) 25 mA CC CC I V Digitalsupplycurrent(operating NoDCload,V =3.6V(8) 15 mA CCIO CCIO CCIO mode) V Digitalsupplycurrent(dozemode) NoDCload,V =3.6V(8) 700 µA CCIO CCIO V Digitalsupplycurrent(snooze NoDCload,V =3.6V(8) 100 µA CCIO CCIO mode) V Digitalsupplycurrent(sleepmode) NoDCload,V =3.6V(8) 100 µA CCIO CCIO I V supplycurrent(operatingmode) Allfrequencies,V =3.6V 30 mA CCAD CCAD CCAD V supplycurrent(dozemode) Allfrequencies,V =3.6V(7) 200 µA CCAD CCAD V supplycurrent(snoozemode) Allfrequencies,V =3.6V(7) 200 µA CCAD CCAD V supplycurrent(sleepmode) Allfrequencies,V =3.6V(7) 200 µA CCAD CCAD I V pumpsupplycurrent V =3.6Vreadoperation 25 mA CCP CCP CCP V =3.6Vprogram(9) 90 mA CCP V =3.6Verase 90 mA CCP V =3.6Vdozemode(7) 5 µA CCP V =3.6Vsnoozemode(7) 5 µA CCP V =3.6Vsleepmode(7) 5 µA CCP C Input 2 pF I capacitance(10) C Output 3 pF O capacitance (3) TypicalvaluesareatV =1.5VandmaximumvaluesareatV =1.65V cc cc (4) ThepeakcurrentismeasuredontheTIEVMboardwithtwo10µFandthirteen100nFcapacitorsonVCCdomain.Runningatalower frequencyconsumeslesscurrent. (5) LBISTcurrentsspecifiedareforexecutionofLBISTwithacertainSTCclock.Lowercurrentconsumptioncanbeachievedby configuringaslowerSTCClockfrequency.Thecurrentpeakdurationcanlastforthedurationof1LBISTtestinterval. (6) PBISTcurrentsspecifiedareforexecutionofPBISTonallRAMs(Group1-14)andallthealgrithms.Lowercurrentconsumptioncanbe achievedbyconfiguringaslowerHCLKfrequency.Differentalgorithmsconsumedifferentcurrent.Formoreinformation,pleasereferto BasicPBISTConfigurationandinfluenceoncurrentconsumption(SPNA128). (7) ForFlashbanks/pumpsinsleepmode. (8) I/Opinsconfiguredasinputsoroutputswithnoload.Allpulldowninputs≤0.2V.Allpullupinputs≥V -0.2V. CCIO (9) Thisassumesreadingfromonebankwhileprogrammingadifferentbank. (10) ThemaximuminputcapacitanceC oftheFlexRayRXpin(s)is10pF. I 66 DeviceElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7 Peripheral and Electrical Specifications 7.1 Clocks 7.1.1 PLL And Clock Specifications Table7-1.TimingRequirementsForPLLCircuitsEnabledOrDisabled MIN MAX Unit f Inputclockfrequency 5 20 MHz (OSC) t Cycletime,OSCIN 50 ns c(OSC) t Pulseduration,OSCINlow 15 ns w(OSCIL) t Pulseduration,OSCINhigh 15 ns w(OSCIH) f OSCFAILfrequency-upperlevel 20 50 MHz (OSCRST) f OSCFAILfrequency-lowerlevel 1.5 5 MHz (OSCRST) 7.1.2 External Reference Resonator/Crystal Oscillator Clock Option The oscillator is enabled by connecting the appropriate fundamental 5–20 MHz resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in section (a) of the figure below. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled duringleakagetestmeasurementandHALTmode. NOTE TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-upandoperationovertemperature/voltageextremes. An external oscillator source can be used by connecting a 1.5V clock signal to the OSCIN pin and leaving theOSCOUTpinunconnected(open)asshowninsection(b)ofthefigurebelow. (seeNoteB) OSCIN Kelvin_GND OSCOUT OSCIN OSCOUT C1 C2 External (seeNoteA) ClockSignal (toggling0-1.5V) Crystal (a) (b) Figure7-1.RecommendedCrystal/ClockConnection NOTE Infigure(a),ThevaluesofC1andC2shouldbeprovidedbytheresonator/crystalvendor. Infigure(b),Kelvin_GNDshouldnotbeconnectedtoanyotherGND. 7.1.3 Validated FMPLL Setting ThefollowingtableincludesthevalidatedFMPLLsettings. Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 67 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com Table7-2.ValidatedFMPLLSettings OSC_INFrequency FMPLLOutput Modulation PLLCTL1 PLLCTL2 ModulationDepth (MHz) Frequency(MHz) Bandwidth(KHz) 10 0x20049500 0x82409253 150 100 0.5% 10 0x20049500 0x8300B240 150 77 0.5% 10 0x20048600 0x8240925C 135 100 0.5% 10 0x20048600 0x8300B247 135 77 0.5% 10 0x20048600 0x824092B9 135 100 1.0% 10 0x20048D80 0x8300B443 95 77 0.5% 10 0x20048D80 0x824094AF 95 100 1.0% 16 0x20079500 0x82409253 150 100 0.5% 16 0x20079500 0x8300B240 150 77 0.5% 16 0x20078600 0x8240925C 135 100 0.5% 16 0x20078600 0x8300B247 135 77 0.5% 16 0x20078600 0x824092B9 135 100 1.0% 16 0x20078D80 0x8300B443 95 77 0.5% 16 0x20078D80 0x824094AF 95 100 1.0% 20 0x20099500 0x82409253 150 100 0.5% 20 0x20099500 0x8300B240 150 77 0.5% 20 0x20098600 0x8240925C 135 100 0.5% 20 0x20098600 0x8300B247 135 77 0.5% 20 0x20098600 0x824092B9 135 100 1.0% 20 0x20098D80 0x8300B443 95 77 0.5% 20 0x20098D80 0x824094AF 95 100 1.0% 68 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.1.4 LPO And Clock Detection The LPOCLKDET module consists of a clock monitor (CLKDET) and 2 low power oscillators (LPO) - a low frequency (LF) and a high frequency (HF) oscillator. The CLKDET is a supervisor circuit for an externally supplied clock signal. In case the externally supplied clock frequency falls out of a frequency window, the clock detector flags this condition and switches to the HF LPO clock (limp mode). The OSCFAIL flag and clock switch-over remain, regardless of the behavior of the oscillator clock signal. The only way OSCFAIL canbecleared(andre-enableOSCINastheclocksource)isapower-on-reset. Table7-3.LPOAndClockDetection Parameter MIN Type MAX Unit Invalidfrequency lowerthreshold 1.5 5 MHz upperthreshold 20 50 MHz Limpmodefrequency(HFosc) 7.9 10 14.4 MHz HFoscfrequency 7.9 10 14.4 MHz LFoscfrequency 62 80 113 kHz lower- upper- guaranteedfail guaranteedpass guaranteedfail threshold threshold f[MHz] 1.5 5.0 20.0 50.0 Figure7-2.LPOAndClockDetection Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks Table7-4.SwitchingCharacteristicsOverRecommendedOperatingConditionsForClocks Parameter TestConditions MIN MAX Unit f HCLK-Systemclockfrequency(337BGA Pipelinemodeenabled 160 MHz (HCLK) packages) Pipelinemodedisabled 36 MHz f HCLK-Systemclockfrequency(144pinQFP Pipelinemodeenabled 140 MHz (HCLK) package) Pipelinemodedisabled 36 MHz f GCLK-CPUclockfrequency(ratioGCLK: f MHz (GCLK) (HCLK) HCLK=1:1) f RCLK-FrequencyoutofPLLmacrointoR- 160 MHz (RCLK) divider f (1) RTICLK-clockfrequency f MHz (RTICLK) (VCLK) f VCLK-Primaryperipheralclockfrequency f MHz (VCLK) (VCLK2) f VCLK2-Secondaryperipheralclockfrequency 100 MHz (VCLK2) f AVCLK1-Primaryasynchronousperipheralclock f MHz (AVCLK1) (VCLK) frequency f AVCLK2-Secondaryasynchronousperipheral f MHz (AVCLK2) (VCLK) clockfrequency f (2) ECLK-ExternalclockoutputfrequencyforECP 80 MHz (ECLK) Module f Systemclockfrequency-Flash f MHz (PROG/ERASE) (HCLK) programming/erase (1) IftheRTIxclocksourceischosentobeanythingotherthanthedefaultVCLK,thentheRTIclockneedstobeatleastthreetimesslower thantheVCLK. (2) (ECLK)=f(VCLK)/N,whereN={1to65536}.NistheECPprescalevaluedefinedbytheECPCNTL.[15:0]registerbitsintheSystem module.PipelinemodeenabledordisabledisdeterminedbytheFRDCNTL[2:0]. 7.1.5.1 Timing-WaitStates RAM AddressWaitstates 0 0MHz f(HCLK) DataWaitstates 0 0MHz f(HCLK) Flash AddressWaitstates 0 1 0MHz 100MHz f(HCLK) DataWaitstates 0 1 2 3 0MHz 36MHz 72MHz 108MHz f(HCLK) Figure7-3.WaitStates NOTE If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not exceeded. The speed of the device clocks may need be derated to accommodate the modulationdepthwhenFMzPLLfrequencymodulationisenabled. 70 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.2 ECLK Specification 7.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks Table7-5.SwitchingCharacteristicsOverRecommendedOperatingConditionsForExternalClocks(1)(2) NO. Parameter TestConditions MIN MAX Unit 3 t Pulseduration,ECLKlow underallprescalefactor 0.5t –tf ns w(EOL) c(ECLK) combinations(XandN) 4 t Pulseduration,ECLKhigh underallprescalefactor 0.5t – ns w(EOH) c(ECLK) combinations(XandN) tr (1) X={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}.XistheVBUSinterfaceclockdividerratiodeterminedbytheCLKCNTL.[19:16]bitsinthe SYSmodule. (2) N={1to65536}.NistheECPprescalevaluedefinedbytheECPCNTL.[15:0]registerbitsintheSystemmodule. 4 ECLK 3 Figure7-4.ECLKTimingDiagram Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.3 RST And PORRST Timings 7.3.1 Timing Requirements For PORRST Table7-6.TimingRequirementsFor PORRST NO. MIN MAX Unit V V lowsupplylevelwhenPORRSTmustbeactiveduringpowerup 0.5 V CCPORL CC V V highsupplylevelwhenPORRSTmustremainactiveduringpowerup 1.35 V CCPORH CC andbecomeactiveduringpowerdown V V /V lowsupplylevelwhenPORRSTmustbeactiveduring 1.1 V CCIOPORL CCIO CCP powerup V V /V highsupplylevelwhenPORRSTmustremainactiveduring 3 V CCIOPORH CCIO CCP powerupandbecomeactiveduringpowerdown V Low-levelinputvoltageofPORRSTV >2.5V 0.2V V IL(PORRST) CCIO CCIO Low-levelinputvoltageofPORRSTV <2.5V 0.5 V CCIO 3 t Setuptime,PORRSTactivebeforeV andV >V during 0 ms su(PORRST) CCIO CCP CCIOPORL powerup 6 t Holdtime,PORRSTactiveafterV >V 1 ms h(PORRST) CC CCPORH 7 t Setuptime,PORRSTactivebeforeV <=V duringpowerdown 8 µs su(PORRST) CC CCPORH 8 t Holdtime,PORRSTactiveafterV andV >V 1 ms h(PORRST) CCIO CCP CCIOPORH 9 t Holdtime,PORRSTactiveafterV <V 0 ms h(PORRST) CC CCPORL t FiltertimePORRST,pulseslessthanMINwillbefilteredout,pulses 20 150 ns f(PORRST) greaterthanMAXareguaranteedtogenerateareset(1) t FiltertimeRST,pulseslessthanMINwillbefilteredout,pulsesgreater 20 150 ns f(RST) thanMAXareguaranteedtogenerateareset (1) AlowpulseonthenPORRSTpinwhichisjustbarelylongerthantheglitchfilterimplementedonthispinwillresultinaveryshort internalreset.Thismayresultinunpredictablebehaviorassomepartsofthedevicemayberesetwhileotherpartsofthedeviceare not. 3.3V VCCIOPORH VCCIO / VCCP VCCIOPORH 8 1.5V VCCPORH VCC VCCPORH 7 6 6 VCCIOPORL 7 VCCIOPORL VCCPORL VCCPORL VCC(1.5V) 3 9 PORRST VIL(PORRST) VIL VIL VIL VIL VIL(PORRST) Figure7-5.PORRSTTimingDiagram NOTE ThereisnotimingdependencybetweentherampoftheVCCIOandtheVCCsupplyvoltage; this is just an exemplary drawing. All requirements are to ensure PORRST is active when VCCIOorVCCisoutofthenormaloperatingrange. 72 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.3.2 Switching Characteristics Over Recommended Operating Conditions For RST Table7-7.SwitchingCharacteristicsOverRecommendedOperatingConditionsFor RST(1) Parameter MIN MAX Unit t Validtime,RSTactiveafterPORRSTinactive 1048 ns v(RST) c(OSC) Validtime,RSTactive(allothers) 8t c(VCLK) (1) SpecifiedvaluesdoNOTincluderise/falltimes.Forriseandfalltimings,seetheswitchingcharacteristicsforoutputtimingsversusload capacitancetable. 7.3.3 IO Status During PORRST IO buffer condition during power-on-reset (nPORRST is low): All I/O pins, except nRST, are configured as High-impedance while nPORRST is low and immediately after nPORRST goes high. The FlexRay FRAYTX1 and FRAYTX2 pins are high impedance (high-Z) while nPORRST is low, and are output high at latest 1024 oscillator cycles after nPORRST goes high; the FlexRay FRAYTXEN1 and FRAYTXEN2 pins are high impedance (high-Z) while nPORRST is low, and output high immediately after nPORRST goes high. IO pullup/pulldown condition during power-on-reset: all internal pullups and pulldowns on input pins are disabled when nPORRST is low, and become active immediately after nPORRST goes high. Pins that are listed with "programmable" have programmable pullups or pulldowns. The default value after reset is listed underneath "programmable" in Table 2-9. The exceptions are nPORRST, nRST, nTRST and TEST pins. Thepullsonthesepinswillbeactiveduringpower-on-reset. Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.4 TEST Pin Timing Table7-8.TESTPinTiming NO. Description MIN MAX Unit t FiltertimeTEST,pulseslessthanMINwillbefilteredout,pulses 10 80 ns f(TEST) greaterthanMAXareguaranteedtoenterTESTmode 74 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.5 DAP - JTAG Scan Interface Timing 7.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output Table7-9.JTAGScanInterfaceTiming NO. MIN MAX Unit f TCKfrequency(atHCLKmax) 12 MHz (TCK) f RTCKfrequency(atTCKmaxandHCLKmax) 10 MHz (RTCK) 1 t Delaytime,TCKtoRTCK 20 ns d(TCK-RTCK) 2 t Setuptime,TDI,TMSbeforeRTCKrise(RTCKr) 15 ns su(TDI/TMS-RTCKr) 3 t Holdtime,TDI,TMSafterRTCKr 0 ns h(RTCKr-TDI/TMS) 4 t Holdtime,TDOafterRTCKf 0 ns h(RTCKf-TDO) 5 t Delaytime,TDOvalidafterRTCKfall(RTCKf) 10 ns d(RTCKf-TDO) Note:Thetimingsinthistablearemeasuredwitha50pFand50µAload.Andtheyaremeasuredatthe50%point,not20%or80%point. TCK RTCK 1 1 TMS TDI 2 3 TDO 4 5 Figure7-6.JTAGtiming Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.6 Output Timings 7.6.1 Switching Characteristics For Output Timings Versus Load Capacitance (C ) L Table7-10.SwitchingCharacteristicsForOutputTimingsVersusLoadCapacitance(C ) L Parameter MIN MAX Unit t 8mApins C =15pF 2.5 ns r L C =50pF 5 L C =100pF 9 L C =150pF 12 L t 8mApins C =15pF 2.5 ns f L C =50pF 5 L C =100pF 9 L C =150pF 12 L t 4mApins C =15pF 7 ns r L C =50pF 13 L C =100pF 21 L C =150pF 29 L t 4mApins C =15pF 7 ns f L C =50pF 13 L C =100pF 21 L C =150pF 29 L t 2mA-zpins C =15pF 10 ns r L C =50pF 17 L C =100pF 25 L C =150pF 35 L t 2mA-zpins C =15pF 10 ns f L C =50pF 17 L C =100pF 25 L C =150pF 35 L t t r f V Output 80% 80% CCIO 20% 20% 0 Figure7-7.CMOS-LevelOutputs 76 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.7 Input Timings 7.7.1 Timing Requirements For Input Timings Table7-11.TimingRequirementsForInputTimings(1) MIN MAX Unit t Inputminimumpulsewidth t +10(2) ns pw c(VCLK) (1) t =peripheralVBUSclockcycletime=1/f c(VCLK) (VCLK) (2) ThetimingshownaboveisonlyvalidforpinusedinGIOmode t pw V Input 80% 80% CCIO 20% 20% 0 Figure7-8.CMOS-LevelInputs Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.8 Flash Timings Table7-12.TimingRequirementsForProgramFlash MIN NOM MAX Unit t Fullword(32-bit)programmingtime 33 300 µs prog(32-bit) t 2M-byteprogramming -40°Cto125°C 17 74 s prog(Total) time(1) 0°Cto60°C,forfirst25 17 25 s cycles t ECCprogrammingtime 33 300 µs progECC(16-bit) t TotalECCbit -40°Cto125°C 4.3 15 s progECC(total) programmingtime(256k- 0°Cto60°C,forfirst25 4.3 7 s byte) cycles t Sectorerasetime -40°Cto125°C 2 15 s erase(sector) (includingcompaction) 0°Cto60°C,forfirst25 1.5 10 s cycles t Bankerasetime(including Bank0 7.5 20 s erase(bank) compaction),0°Cto60°C, Bank1 5.5 12 s forfirst25cycles Bank2 5.5 12 s Bank3 5.5 12 s t Write/erasecyclesatT =-40to125°Cwith15year 1000 cycles wec A DataRetentionrequirement(2) (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoesnotincludedatatransfertime. (2) Flashwrite/erasecyclesanddataretentionspecificationsarebasedonavalidatedimplementationoftheTIflashAPI.Non-TIflashAPI implementationisnotsupported.FordetaileddescriptionseetheF035FlashValidationProcedure(SPNA127). 78 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.9 SPI Master Mode Timing Parameters 7.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) Table7-13.SPIMasterModeExternalTimingParameters(1)(2)(3) NO. MIN MAX Unit 1 t Cycletime,SPICLK (4) 50 256t ns c(SPC)M c(VCLK) 2(5) t Pulseduration,SPICLKhigh(clockpolarity=0) 0.5t –3–t 0.5t +5 ns w(SPCH)M c(SPC)M r c(SPC)M t Pulseduration,SPICLKlow(clockpolarity=1) 0.5t –3–t 0.5t +5 w(SPCL)M c(SPC)M f c(SPC)M 3(5) t Pulseduration,SPICLKlow(clockpolarity=0) 0.5t –3–t 0.5t +5 ns w(SPCL)M c(SPC)M f c(SPC)M t Pulseduration,SPICLKhigh(clockpolarity=1) 0.5t –3–t 0.5t +5 w(SPCH)M c(SPC)M r c(SPC)M 4(5) t Delaytime,SPISIMOvalidbeforeSPICLKlow 0.5t –10 ns d(SIMO-SPCL)M c(SPC)M (clockpolarity=0) t Delaytime,SPISIMOvalidbeforeSPICLKhigh 0.5t –10 d(SIMO-SPCH)M c(SPC)M (clockpolarity=1) 5(5) t Validtime,SPISIMOdatavalidafterSPICLKlow 0.5t –t -7 ns v(SPCL-SIMO)M c(SPC)M f(SPC) (clockpolarity=0) t Validtime,SPISIMOdatavalidafterSPICLKhigh 0.5t –t -7 v(SPCH-SIMO)M c(SPC)M r(SPC) (clockpolarity=1) 6(5) t Setuptime,SPISOMIbeforeSPICLKlow(clock t ns su(SOMI-SPCL)M f(SPC) polarity=0) t Setuptime,SPISOMIbeforeSPICLKhigh(clock t +4 su(SOMI-SPCH)M r(SPC) polarity=1) 7(5) t Holdtime,SPISOMIdatavalidafterSPICLKlow 10 ns h(SPCL-SOMI)M (clockpolarity=0) t Holdtime,SPISOMIdatavalidafterSPICLKhigh 10 h(SPCH-SOMI)M (clockpolarity=1) 8(6) t SetuptimeCSactiveuntilSPICLKhigh,assumes (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ ns C2TDELAY thatSPInENAislowatt (clockpolarity=0) 2)*t -t + 2)*t -t + SPIENA c(VCLK) f(SPICS) c(VCLK) f(SPICS) t -9 t +5 r(SPC) r(SPC) SetuptimeCSactiveuntilSPICLKlow,assumes (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ ns thatSPInENAislowatt (clockpolarity=1) 2)*t -t + 2)*t -t + SPIENA c(VCLK) f(SPICS) c(VCLK) f(SPICS) t -9 t +5 f(SPC) f(SPC) 9(6) t HoldtimeSPICLKlowuntilCSinactive(clock 0.5*t + 0.5*t + ns T2CDELAY c(SPC)M c(SPC)M polarity=0) T2CDELAY*t + T2CDELAY*t + c(VCLK) c(VCLK) t - t - c(VCLK) c(VCLK) t +t -5 t +t +10 f(SPC) r(SPICS) f(SPC) r(SPICS) HoldtimeSPICLKhighuntilCSinactive(clock 0.5*t + 0.5*t + ns c(SPC)M c(SPC)M polarity=1) T2CDELAY*t + T2CDELAY*t + c(VCLK) c(VCLK) t - t - c(VCLK) c(VCLK) t +t -5 t +t +10 r(SPC) r(SPICS) r(SPC) r(SPICS) 10 t SPIENAnSamplepoint C2TDELAY*t - C2TDELAY*t ns SPIENA c(VCLK) c(VCLK) t -20 f(SPICS) 11 t SPIENAnSamplepointfromwritetobuffer (C2TDELAY+2)*t ns SPIENAW c(VCLK) (1) TheMASTERbit(SPIGCR1.0)issetandtheCLOCKPHASEbit(SPIFMTx.16)isset. (2) t =interfaceclockcycletime=1/f(VCLK) c(VCLK) (3) Forriseandfalltimings,seethe"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (4) WhentheSPIisinMastermode,thefollowingmustbetrue: ForPSvaluesfrom1to255:t ≥(PS+1)t ≥50ns,wherePSistheprescalevaluesetintheSPIFMTx.[15:8]registerbits. c(SPC)M c(VCLK) ForPSvaluesof0:t =2t ≥50ns.TheexternalloadontheSPICLKpinmustbelessthan60pF. c(SPC)M c(VCLK) (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). (6) C2TDELAYandT2CDELAYareprogrammedintheSPIDELAYregister Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 1 SPICLK (clockpolarity=0) 2 3 SPICLK (clockpolarity=1) 4 5 SPISIMO MasterOutDataIsValid 6 7 SPISOMI MasterInData Must Be Valid Figure7-9.SPIMasterModeExternalTiming(CLOCKPHASE=0) Writetobuffer SPICLK (clockpolarity=0) SPICLK (clockpolarity=1) SPISIMO MasterOutDataIsValid 8 9 SPICSn 10 11 SPIENAn Figure7-10.SPIMasterModeChipSelecttiming(CLOCKPHASE=0) 80 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.9.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) Table7-14.SPIMasterModeExternalTimingParameters(1)(2)(3) NO. MIN MAX Unit 1 t Cycletime,SPICLK (4) 50 256t ns c(SPC)M c(VCLK) 2(5) t Pulseduration,SPICLKhigh(clockpolarity=0) 0.5t –3–t 0.5t +5 ns w(SPCH)M c(SPC)M r c(SPC)M t Pulseduration,SPICLKlow(clockpolarity=1) 0.5t –3–t 0.5t +5 w(SPCL)M c(SPC)M f c(SPC)M 3(5) t Pulseduration,SPICLKlow(clockpolarity=0) 0.5t –3–t 0.5t +5 ns w(SPCL)M c(SPC)M r c(SPC)M t Pulseduration,SPICLKhigh(clockpolarity=1) 0.5t –3–t 0.5t +5 w(SPCH)M c(SPC)M f c(SPC)M 4(5) t Delaytime,SPICLKhighafterSPISIMOdata 0.5t –10 ns d(SIMO-SPCH)M c(SPC)M valid(clockpolarity=0) t Delaytime,SPICLKlowafterSPISIMOdatavalid 0.5t –10 d(SIMO-SPCL)M c(SPC)M (clockpolarity=1) 5(5) t Validtime,SPISIMOdatavalidafterSPICLK 0.5t –t –7 ns v(SPCH-SIMO)M c(SPC)M r(SPC) high(clockpolarity=0) t Validtime,SPISIMOdatavalidafterSPICLK 0.5t –tf –7 v(SPCL-SIMO)M c(SPC)M (SPC) low(clockpolarity=1) 6(5) t Setuptime,SPISOMIbeforeSPICLKhigh(clock t +4 ns su(SOMI-SPCH)M r(SPC) polarity=0) t Setuptime,SPISOMIbeforeSPICLKlow(clock t su(SOMI-SPCL)M f(SPC) polarity=1) 7(5) t Validtime,SPISOMIdatavalidafterSPICLKhigh 10 ns v(SPCH-SOMI)M (clockpolarity=0) t Validtime,SPISOMIdatavalidafterSPICLKlow 10 v(SPCL-SOMI)M (clockpolarity=1) 8(6) t SetuptimeCSactiveuntilSPICLKhigh,assumes (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ ns C2TDELAY thatSPInENAislowatt (clockpolarity=0) 2)*t +0.5*t - 2)*t +0.5*t - SPIENA c(VCLK) c(SPC)M c(VCLK) c(SPC)M t +t -9 t +t +5 f(SPICS) r(SPC) f(SPICS) r(SPC) SetuptimeCSactiveuntilSPICLKlow,assumes (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ ns thatSPInENAislowatt (clockpolarity=1) 2)*t +0.5*t 2)*t +0.5*t SPIENA c(VCLK) c(SPC)M c(VCLK) c(SPC)M -t +t -9 -t +t +5 f(SPICS) f(SPC) f(SPICS) f(SPC) 9(6) t HoldtimeSPICLKlowuntilCSinactive(clock T2CDELAY*t + T2CDELAY*t + ns T2CDELAY c(VCLK) c(VCLK) polarity=0) t -t +t t -t +t c(VCLK) f(SPC) r(SPICS) c(VCLK) f(SPC) r(SPICS) -5 +10 HoldtimeSPICLKhighuntilCSinactive(clock T2CDELAY*t + T2CDELAY*t + ns c(VCLK) c(VCLK) polarity=1) t -t + t -t + c(VCLK) r(SPC) c(VCLK) r(SPC) t -5 t +10 r(SPICS) r(SPICS) 10 t SPIENAnSamplePoint C2TDELAY*t - C2TDELAY*t ns SPIENA c(VCLK) c(VCLK) t -20 f(SPICS) 11 t SPIENAnSamplepointfromwritetobuffer (C2TDELAY+2)*t ns SPIENAW c(VCLK) (1) TheMASTERbit(SPIGCR1.0)issetandtheCLOCKPHASEbit(SPIFMTx.16)isset. (2) t =interfaceclockcycletime=1/f(VCLK) c(VCLK) (3) Forriseandfalltimings,seethe"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (4) WhentheSPIisinMastermode,thefollowingmustbetrue: ForPSvaluesfrom1to255:t ≥(PS+1)t ≥50ns,wherePSistheprescalevaluesetintheSPIFMTx.[15:8]registerbits. c(SPC)M c(VCLK) ForPSvaluesof0:t =2t ≥50ns.TheexternalloadontheSPICLKpinmustbelessthan60pF. c(SPC)M c(VCLK) (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). (6) C2TDELAYandT2CDELAYareprogrammedintheSPIDELAYregister Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 1 SPICLK (clockpolarity=0) 2 3 SPICLK (clockpolarity=1) 4 5 SPISIMO MasterOutDataIsValid Data Valid 6 7 MasterInData SPISOMI MustBeValid Figure7-11.SPIMasterModeExternalTiming(CLOCKPHASE=1) Writetobuffer SPICLK (clockpolarity=0) SPICLK (clockpolarity=1) SPISIMO MasterOutDataIsValid 8 9 SPICS 10 11 SPIENA Figure7-12.SPIMasterModeChipSelecttiming(CLOCKPHASE=1) 82 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.10 SPI Slave Mode Timing Parameters 7.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output) Table7-15.SPISlaveModeExternalTimingParameters (1)(2)(3) NO. MIN MAX Unit 1 t Cycletime,SPICLK(4) 90 ns c(SPC)S 2(5) t Pulseduration,SPICLKhigh(clockpolarity=0) 30 ns w(SPCH)S t Pulseduration,SPICLKlow(clockpolarity=1) 30 w(SPCL)S 3(5) t Pulseduration,SPICLKlow(clockpolarity=0) 30 ns w(SPCL)S t Pulseduration,SPICLKhigh(clockpolarity=1) 30 w(SPCH)S 4(5) t Delaytime,SPISOMIvalidafterSPICLKhigh t +15 ns d(SPCH-SOMI)S rf(SOMI) (clockpolarity=0) t Delaytime,SPISOMIvalidafterSPICLKlow(clock t +15 d(SPCL-SOMI)S rf(SOMI) polarity=1) 5(5) t Validtime,SPISOMIdatavalidafterSPICLKhigh 0 ns V(SPCH-SOMI)S (clockpolarity=0) t Validtime,SPISOMIdatavalidafterSPICLKlow 0 V(SPCL-SOMI)S (clockpolarity=1) 6(5) t Setuptime,SPISIMObeforeSPICLKlow(clock 4 ns su(SIMO-SPCL)S polarity=0) t Setuptime,SPISIMObeforeSPICLKhigh(clock 4 su(SIMO-SPCH)S polarity=1) 7(5) t Holdtime,SPISIMOdatavalidafterSPICLKlow 6 ns h(SPCL-SIMO)S (clockpolarity=0) t Holdtime,SPISIMOdatavalidafterSPICLKhigh 6 h(SPCH-SIMO)S (clockpolarity=1) 8 t Delaytime,SPIENAnhighafterlastSPICLKlow 1.5t 2.5t +t +26 ns d(SPCL-SENAH)S c(VCLK) c(VCLK) r(ENAn) (clockpolarity=0) t Delaytime,SPIENAnhighafterlastSPICLKhigh 1.5t 2.5t +t +26 d(SPCH-SENAH)S c(VCLK) c(VCLK) r(ENAn) (clockpolarity=1) 9 t Delaytime,SPIENAnlowafterSPICSnlow(ifnew t t +t +18 ns d(SCSL-SENAL)S f(ENAn) c(VCLK) f(ENAn) datahasbeenwrittentotheSPIbuffer) (1) TheMASTERbit(SPIGCR1.0)issetandtheCLOCKPHASEbit(SPIFMTx.16)isset. (2) t =interfaceclockcycletime=1/f c(VCLK) (VCLK) (3) Forriseandfalltimings,seethe"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (4) WhentheSPIisinSlavemode,thefollowingmustbetrue: t >2t andt >=90ns. c(SPC)S c(VCLK) c(SPC)S t >t andt >t . w(SPCH)S c(VCLK) w(SPCL)S c(VCLK) (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 1 SPICLK (clockpolarity=0) 2 3 SPICLK (clockpolarity=1) 4 5 SPISOMI SPISOMIDataIsValid 6 7 SPISIMOData SPISIMO Must Be Valid Figure7-13.SPISlaveModeExternalTiming(CLOCKPHASE=0) SPICLK (clockpolarity=0) SPICLK (clockpolarity=1) 8 SPIENAn 9 SPICSn Figure7-14.SPISlaveModeEnableTiming(CLOCKPHASE=0) 84 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output) Table7-16.SPISlaveModeExternalTimingParameters(1)(2)(3) NO. MIN MAX Unit 1 t Cycletime,SPICLK(4) 90 ns c(SPC)S 2(5) t Pulseduration,SPICLKhigh(clockpolarity=0) 30 ns w(SPCH)S t Pulseduration,SPICLKlow(clockpolarity=1) 30 w(SPCL)S 3(5) t Pulseduration,SPICLKlow(clockpolarity=0) 30 ns w(SPCL)S t Pulseduration,SPICLKhigh(clockpolarity=1) 30 w(SPCH)S 4(5) t Delaytime,SPISOMIdatavalidafterSPICLKlow t +15 ns d(SOMI- rf(SOMI) (clockpolarity=0) SPCL)S t Delaytime,SPISOMIdatavalidafterSPICLKhigh t +15 d(SOMI- rf(SOMI) (clockpolarity=1) SPCH)S 5(5) t Validtime,SPISOMIdatavalidafterSPICLKhigh 0 ns V(SPCL- (clockpolarity=0) SOMI)S t Validtime,SPISOMIdatavalidafterSPICLKlow 0 V(SPCH- (clockpolarity=1) SOMI)S 6(5) t Setuptime,SPISIMObeforeSPICLKhigh(clock 4 ns su(SIMO- polarity=0) SPCH)S t Setuptime,SPISIMObeforeSPICLKlow(clock 4 su(SIMO- polarity=1) SPCL)S 7(5) t Holdtime,SPISIMOdatavalidafterSPICLKhigh 6 ns h(SPCH- (clockpolarity=0) SIMO)S t Holdtime,SPISIMOdatavalidafterSPICLKlow 6 h(SPCL- (clockpolarity=1) SIMO)S 8 t Delaytime,SPIENAnhighafterlastSPICLKhigh 1.5t 2.5t +t +26 ns d(SPCH- c(VCLK) c(VCLK) r(ENAn) (clockpolarity=0) SENAH)S t Delaytime,SPIENAnhighafterlastSPICLKlow 1.5t 2.5t +t +26 d(SPCL- c(VCLK) c(VCLK) r(ENAn) (clockpolarity=1) SENAH)S 9 t Delaytime,SPIENAnlowafterSPICSnlow(ifnew t t +t +18 ns d(SCSL- f(ENAn) c(VCLK) f(ENAn) datahasbeenwrittentotheSPIbuffer) SENAL)S 10 t Delaytime,SOMIvalidafterSPICSnlow(ifnewdata t 2t +t +20 ns d(SCSL- c(VCLK) c(VCLK) rf(SOMI) hasbeenwrittentotheSPIbuffer) SOMI)S (1) TheMASTERbit(SPIGCR1.0)issetandtheCLOCKPHASEbit(SPIFMTx.16)isset. (2) t =interfaceclockcycletime=1/f c(VCLK) (VCLK) (3) Forriseandfalltimings,seethe"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table. (4) WhentheSPIisinSlavemode,thefollowingmustbetrue: t >2t andt >=90ns. c(SPC)S c(VCLK) c(SPC)S t >t andt >t . w(SPCH)S c(VCLK) w(SPCL)S c(VCLK) (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 1 SPICLK (clockpolarity=0) 2 3 SPICLK (clockpolarity=1) 4 5 SPISOMI SPISOMIDataIsValid Data Valid 6 7 SPISIMOData SPISIMO Must Be Valid Figure7-15.SPISlaveModeExternalTiming(CLOCKPHASE=1) SPICLK (clockpolarity=0) SPICLK (clockpolarity=1) 8 SPIENAn 9 SPICSn 10 SPISOMI SlaveOutDataIsValid Figure7-16.SPISlaveModeEnableTiming(CLOCKPHASE=1) 86 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.11 CAN Controller Mode Timings 7.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins Table7-17.DynamicCharacteristicsForTheCANnTXAndCANnRXPins Parameter MIN MAX Unit t (CANnTX) Delaytime,transmitshiftregistertoCANnTXpin(1) 15 ns d t (CANnRX) Delaytime,CANnRXpintoreceiveshiftregister 5 ns d (1) Thesevaluesdonotincluderise/falltimesoftheoutputbuffer. 7.12 SCI/LIN Mode Timings At100MHzPeripheralClock,3.125Mbits/sistheMaxSCIBaudRateachievable. 7.13 FlexRay Controller Mode Timings 7.13.1 Jitter Timing Table7-18.JitterTiming Parameter MIN MAX Unit t clockjitterandsignalsymmetry 98 102 ns Tx1bit t FlexRayBSS(bytestartsequence)toBSS 999 1001 ns Tx10bit t averageover10000samples 999.5 1000.5 ns Tx10bitAvg t delaydifferencebetweenriseandfallfromRxpinto - 2.5 ns RxAsymDelay samplepointinFlexRaycore Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.14 EMIF Timings Table7-19.EMIFRead/WriteModeSwitchingCharacteristics(1)(2) NO Parameter Description MIN MAX Unit ReadsandWrites 1 t Turnaroundtime (TA+1)*E- (TA+1)*E- ns d(TURNAROUND) t -2 t +3 r(CS) r(CS) Reads 2 t EMIFreadcycletime (RS+RST+ (RS+RST+ ns c(EMRCYCLE) RH+TA+4)* RH+TA+4)* E-t -3 E-t +3 f(CS) f(CS) 3 t Outputsetuptime,EMIFCS[3:0]lowtoEMIFOE (RS+1)*E- (RS+1)*E- ns su(EMCSL-EMOEL) low(SS=0) t +t -5 t +t +5 f(CS) f(OE) f(CS) f(OE) Outputsetuptime,EMIFCS[3:0]lowtoEMIFOE -t +t - -t +t + ns f(CS) f(OE) f(CS) f(OE) low(SS=1) 5 5 4 t Outputholdtime,EMIFOEhightoEMIFCS[3:0] (RH+1)*E- (RH+1)*E- ns h(EMOEH-EMCSH) high(SS=0) t +t -4 t +t +6 r(OE) r(CS) r(OE) r(CS) Outputholdtime,EMIFOEhightoEMIFCS[3:0] -t +t - -t +t + ns r(OE) r(CS) r(OE) r(CS) high(SS=1) 4 6 5 t Outputsetuptime,EMIFBADD[1:0]validto (RS+1)*E- (RS+1)*E- ns su(EMBAV-EMOEL) EMIFOElow t +t -5 t +t + rf(AD) f(OE) rf(AD) f(OE) 5 6 t Outputholdtime,EMIFOEhighto (RH+1)*E- (RH+1)*E- ns h(EMOEH-EMBAIV) EMIFBADD[1:0]invalid t -5 t +5 r(OE) r(OE) 7 t Outputsetuptime,EMIFADD[21:0]validto (RS+1)*E- (RS+1)*E- ns su(EMAV-EMOEL) EMIFOElow t +t -6 t +t + rf(AD) f(OE) rf(AD) f(OE) 6 8 t Outputholdtime,EMIFOEhightoEMIFADD[21:0] (RH+1)*E- (RH+1)*E- ns h(EMOEH-EMAIV) invalid t -5 t +6 r(OE) r(OE) 9 t EMIFOEactivelowwidth (RST+1)*E- (RST+1)*E- ns w(EMOEL) t -1 t +0 f(OE) f(OE) 10 t Setuptime,EMIFD[15:0]validbeforeEMIFOE t +9 ns su(EMDV-EMOEH) r(OE) high 11 t Holdtime,EMIFD[15:0]validafterEMIFOEhigh -t -3 h(EMOEH-EMDV) r(OE) Writes 12 t EMIFwritecycletime (WS+WST+ (WS+WST+ ns c(EMWCYCLE) WH+TA+4)* WH+TA+4)* E-t -3 E-t +2 f(CS) f(CS) 13 t Outputsetuptime,EMIFCS[3:0]lowtoEMIFWE (WS+1)*E- (WS+1)*E- ns su(EMCSL-EMWEL) low(SS=0) t +t -5 t +t +5 f(CS) f(WE) f(CS) f(WE) Outputsetuptime,EMIFCS[3:0]lowtoEMIFWE -t +t - -t +t + ns f(CS) f(WE) f(CS) f(WE) low(SS=1) 5 5 14 t Outputholdtime,EMIFWEhightoEMIFCS[3:0] (WH+1)*E- (WH+1)*E- ns h(EMWEH-EMCSH) high(SS=0) t +t -4 t +t + r(WE) r(CS) r(WE) r(CS) 5 Outputholdtime,EMIFWEhightoEMIFCS[3:0] -t +t - -t +t + ns r(WE) r(CS) r(WE) r(CS) high(SS=1 4 5 15 t Outputsetuptime,EMIFBADD[1:0]validto (WS+1)*E- (WS+1)*E- ns su(EMBAV-EMWEL) EMIFWElow t +t -5 t +t + rf(AD) f(WE) rf(AD) f(WE) 5 16 t Outputholdtime,EMIFWEhightoEMBADD[1:0] (WH+1)*E- (WH+1)*E- ns h(EMWEH-EMBAIV) invalid t -5 t +5 r(WE) r(WE) 17 t Outputsetuptime,EMIFADD[21:0]validto (WS+1)*E- (WS+1)*E- ns su(EMAV-EMWEL) EMIFWElow t +t -6 t +t + rf(AD) f(WE) rf(AD) f(WE) 6 (1) RS=Readsetup,RST=ReadStrobe,RH=ReadHold,WS=WriteSetup,WST=WriteStrobe,WH=WriteHold,TA=TurnAround, SS=StrobeSelectMode (2) E=VCLKperiodinns. 88 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 Table7-19.EMIFRead/WriteModeSwitchingCharacteristics(1)(2) (continued) NO Parameter Description MIN MAX Unit 18 t Outputholdtime,EMIFWEhighto (WH+1)*E- (WH+1)*E- ns h(EMWEH-EMAIV) EMIFADD[21:0]invalid t -5 t +6 r(WE) r(WE) 19 t EMIFWEactivelowwidth (WST+1)*E- (WST+1)*E- w(EMWEL) t -1 t +1 f(WE) f(WE) 20 t Outputsetuptime,EMIFD[15:0]validtoEMIFWE (WS+1)*E- (WS+1)*E- ns su(EMDV-ENWEL) low t +t -6 t +t + rf(DA) f(WE) rf(DA) f(WE) 5 21 t Outputholdtime,EMIFD[15:0]validafter (WH+1)*E- (WH+1)*E- ns h(EMWEH-EMDIV) EMIFWEhigh t -5 t +5 r(WE) r(WE) 7.14.1 Read Timing (Asynchronous RAM) 2 1 EMIFCS[3:0] EMIFR/W EMIFBADD[1:0] EMIFADD[21:0] 3 8 5 6 7 4 9 EMIFOE 11 10 EMIFD[15:0] EMIFWE Figure7-17.AsynchronousMemoryReadTimingforEMIF Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.14.2 Write Timing (Asynchronous RAM) 12 1 EMIFCS[3:0] EMIFBADD[1:0] EMIFADD[21:0] 13 16 15 18 17 14 19 EMIFWE 20 21 EMIFD[15:0] EMIFOE Figure7-18.AsynchronousMemoryWriteTimingforEMIF 7.15 ETM Timings 7.15.1 ETMTRACECLK Timing t(ETM) l t(ETM)r t(ETM)h t(ETM)f t(ETM) cyc Figure7-19.ETMTRACECLKTiming Table7-20.ETMTRACECLKTiming Parameter Minimum Maximum Description f(ETM) 40MHz Clockfrequency cyc t(ETM) 25ns Clockperiod cyc t(ETM) 2ns Lowpulsewidth l t(ETM) 2ns Highpulsewidth h t(ETM) 3ns Clockanddatarisetime r t(ETM) 3ns Clockanddatafalltime f 90 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.15.2 ETMDATA Timing ETMTRACECLK ETMDATA t(ETM) t(ETM) t(ETM) t(ETM) su ho su ho Figure7-20.ETMDATATiming Table7-21.ETMDATATiming Parameter Typical Description t(ETM) 2.5ns Datasetuptime su t(ETM) 1.5ns Dataholdtime ho Note:Thetimingsinthistablearemeasuredwitha50pFand50µAload.Andtheyaremeasuredatthe50%point,not20%or80%point. 'Typical'means25°Candnominalvoltage. Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.16 RTP Timings 7.16.1 RTPCLK Timing t(RTP) l t t(RTP) t r h f t(RTP) cyc Figure7-21.RTPCLKTiming Table7-22.RTPCLKTiming Parameter Minimum Description t(RTP) 10ns Clockperiod(dependingonHCLKdivide cyc ratio) t(RTP) (t(RTP) /2)-((t+t)/2)-1.5 Highpulsewidth(dependingonHCLKdivide h cyc r f ratioandloadonpin) t(RTP) (t(RTP) /2)-((t+t)/2)-1.5 Lowpulsewidth(dependingonHCLKdivide l cyc r f ratioandloadonpin) 7.16.2 RTPDATA Timing t(RTP) t(RTP) ssu sho RTPSYNC RTPCLK RTPDATA t(RTP) t(RTP) dsu dho Figure7-22.RTPDATATiming Table7-23.RTPDATATiming Parameter Minimum Description t(RTP) 0.5t(RTP) -3ns Datasetuptime dsu cyc t(RTP) 0.5t(RTP) -2ns Dataholdtime dho cyc t(RTP) 0.5t(RTP) -3ns SYNCsetuptime ssu cyc t(RTP) 0.5t(RTP) -2ns SYNCholdtime sho cyc Note:Thetimingsinthistablearemeasuredwitha50pFand50µAload.Andtheyaremeasuredatthe50%point,not20%or80%point. 92 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.16.3 RTPENABLE Timing ttt(((RRRTTTPPP))dd)iidssiaasbballeeble t(Rtt((TRRPTTPP)e))eennnaaabbblellee 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HHHCCCLLLKKK RRRTTTPPPCCCLLLKKK RRRTTTPPPEEENNNAAA RRRTTTPPPSSSYYYNNNCCC RRRTTTPPPDDDAAATTTAAA d1 d2 d3 d4 d5 d6 d7 d8 Divide by 1 Figure7-23.RTPENABLETiming Table7-24.RTPENABLETiming Parameter Minimum Maximum Description t 1.5t +t +12ns TimethatRTPENAmustgohigh (RTP)disable c(HCLK) r(RTPSYNC) beforethenextscheduled RTPSYNCinordertosuspend transmissionforthepacket followingthescheduled RTPSYNC. t 4.5t +t 5.5t +t +12ns TimeafterRTPENAgoeslow (RTP)enable c(HCLK) r(RTPSYNC) c(HCLK) r(RTPSYNC) beforeapacketthathasbeen halted,resumes. Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.17 DMM Timings 7.17.1 DMMCLK Timing t(DMM) l tr t(DMM)h tf t(DMM) cyc Figure7-24.DMMCLKTiming Table7-25.DMMCLKTiming Parameter Minimum Description t(DMM) t *2 Clockperiod cyc c(HCLK) t(DMM) t(DMM) /2-(t+t)/2 Highpulsewidth h cyc r f t(DMM) t(DMM) /2-(t+t)/2 Lowpulsewidth l cyc r f 7.17.2 DMMDATA Timing t(DMM)ssu t(DMM)sho DMMSYNC DMMCLK DMMDATA t(DMM)dsu t(DMM)dho Figure7-25.DMMDATATiming Table7-26.DMMDATATiming Parameter Minimum Description t(DMM) 2ns SYNCactivetoclkfallingedgesetuptime ssu t(DMM) 3ns clkfallingedgetoSYNCdeactiveholdtime sho t(DMM) 2ns DATAtoclkfallingedgesetuptime dsu t(DMM) 3ns clkfallingedgetoDATAholdtime dho 94 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.17.3 DMMENA Timing HCLK DMMCLK DMMSYNC DMMDATA D00 D01 D10 D11 D20 D21 D30 D31 D40 D41 D50 DMMENA Figure7-26.DMMENATiming The above figure shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up of the internal buffers. The DMMENA signal is shown asserted, after the first two packets have been received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4, D5, D6, D7. Packet D8 would result in an overflow. Once DMMENA is asserted, the DMM expects to stop receiving packets after 4 HCLK cycles; once DMMENA is de-asserted, the DMM can handle packets immediately(after0HCLKcycles). 7.18 MibADC 7.18.1 MibADC The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are givenwithrespecttoADREFLOunlessotherwisenoted. Table7-27.MibADC Resolution 12bits(4096values) Monotonic Assured Outputconversionφcode 00htoFFFh[00forV ≤AD ;FFFforV ≥AD ] AI REFLO AI REFHI 7.18.2 MibADC Recommended Operating Conditions Table7-28.MibADCRecommendedOperatingConditions(1) MIN MAX UNIT AD A-to-Dhigh-voltagereferencesource 3 3.6 V REFHI AD A-to-Dlow-voltagereferencesource 0 0.3 V REFLO V Analoginputvoltage AD AD V AI REFLO REFHI I Analoginputclampcurrent(2) -2 2 mA AIC (V <V –0.3orV >V + AI SSAD AI CCAD 0.3) (1) ForV andV recommendedoperatingconditions,seethe"devicerecommendedoperatingconditions"table. CCAD SSAD (2) InputcurrentsintoanyADCinputchanneloutsidethespecifiedlimitscouldaffectconversionresultsofotherchannels. Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions Table7-29.OperatingCharacteristicsOverFullRangesOfRecommendedOperatingConditions(1) Parameter Description/Conditions Min TYP Max Unit R Analoginputmuxon- 250 Ω mux resistance R ADCsampleswitchon- 150 250 Ω samp resistance C Inputmuxcapacitance 16 pF mux C ADCsamplecapacitance 11 12 13 pF samp I Analoginputleakage InputleakageperADCinputpin –200 200 nA AIL current I AD inputcurrent AD =3.6V,AD =V 5 mA ADREFHI REFHI REFHI REFLO SSAD CR Conversionrangeover AD -AD 3 3.6 V REFHI REFLO whichspecifiedaccuracy ismaintained E Differentialnonlinearity Differencebetweentheactualstepwidthandtheidealvalue. ±2 LSB DNL error E Integralnonlinearityerror MaximumdeviationfromthebeststraightlinethroughtheMibADC. ±2 LSB INL MibADCtransfercharacteristics,excludingthequantizationerror. E Totalerror/Absolute Maximumvalueofthedifference Executingperiodic ±4(2) LSB TOT accuracy betweenananalogvalueandtheideal internalcalibration midstepvalue. Nocalibration ±8 LSB (1) 1LSB=(AD –AD )/212fortheMibADC REFHI REFLO (2) Anperiodicinternaloffsetcalibrationisrequiredtoachievetheabsoluteaccuracy.PleaserefertotheAnalogToDigitalConverter(ADC) ModulechapteroftheTMS570LSSeriesMicrocontrollerTechnicalReferenceManual(SPNU489)andInterfacingtheEmbedded12-bit ADC(SPNA129)formoreinformation. 96 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.18.4 MibADC Input Model Pin Smux Rmux Pin Smux Rmux I I AIL AIL Pin Smux Rmux Ssamp Rsamp I I Cmux Csamp AIL AIL Figure7-27.MibADCInputEquivalentCircuit Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 97 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.18.5 MibADC Timings Table7-30.MibADCTimings Min NOm MAX Unit t Cycletime,MibADCclock 33 ns c(ADCLK) t Delaytime,sampleandholdtime 200 ns d(SH) t Delaytime,conversiontime 400 ns d©) t (1) Delaytime,totalsample/holdandconversiontime 600 ns d(SHC) (1) Thisistheminimumsample/holdandconversiontimethatcanbeachieved.Theseparametersaredependentonmanyfactors,e.gthe prescalesettings. 98 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 7.18.6 MibADC Nonlinearity Error The differential nonlinearity error shown in the figure below (sometimes referred to as differential linearity) isthedifferencebetweenanactualstepwidthandtheidealvalueof1LSB. 00...... 111100 00......110011 e d 00......110000 o C ut utp 00......001111 O Differential al 11LLSSBB git 00......001100 LinearityError(1/2LSB) Di DifferentialLinearity 00......000011 11LLSSBB Error(–1/2LSB) 00......000000 00 11 22 33 44 55 AnalogInputValue(LSB) Figure7-28.DifferentialNonlinearity(DNL) The integral nonlinearity error shown in the figure below (sometimes referred to as linearity error) is the deviationofthevaluesontheactualtransferfunctionfromastraightline. 0...111 0...110 Ideal Transition e 0...101 d o Actual C Transition ut 0...100 p ut AtTransition O al 0...011 011/100 git (–1/2LSB) Di 0...010 End-PointLin.Error 0...001 AtTransition 001/010(–1/4LSB) 0...000 0 1 2 3 4 5 6 7 AnalogInputValue(LSB) Figure7-29.IntegralNonlinearity(INL)Error Copyright©2010–2018,TexasInstrumentsIncorporated PeripheralandElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 7.18.7 MibADC Total Error The absolute accuracy or total error of an MibADC as shown in the figure below is the maximum value of thedifferencebetweenananalogvalueandtheidealmidstepvalue. 0...111 0...110 0...101 e d o C ut 0...100 p ut TotalError O 0...011 AtStep0...101 gital (–11/4LSB) Di 0...010 TotalError 0...001 AtStep 0...001(1/2LSB) 0...000 0 1 2 3 4 5 6 7 AnalogInputValue(LSB) Figure7-30.AbsoluteAccuracy(Total)Error 100 PeripheralandElectricalSpecifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 www.ti.com SPNS141G–AUGUST2010–REVISEDOCTOBER2018 8 Revision History Thisdatasheetrevisionhistoryhighlightsthetechnicalchangesmadetothedeviceorthedatasheet. Date Additions,Deletions,AndModifications Revision March2010 UpdatedMemoryMapsection. A June2010 UpdatedtheMibADCInputEquivalentCircuitillustration. B UpdatedtheZWTPackagePinoutillustration. August2010 UpdatedtheRTPDATAtimingdiagram. October2010 AddednotesofspeculativefetchesonflashECCandRamECC. Updatedthecurrentconsumptionwithcharacterizationdata. C Updatedthetimingrequirementwithcharacterizationdata. AddedRCLK,testpinparameters,fixedtheSPItimingfomulas. January2011 Updatedthedatasheetwithcharacterizationdata.TMSrelease. D July2011 UpdatedDMAChannelcontrolpacketsnumbers. SwitcheddescriptionofSPI1CSandSPI1CLK.SwitcheddescriptionofSPI3CSandSPI3CLK. F Addedtablenotetotable2-7tospecifythetestclockfordifferentRAMs. Modifiedthetablenotefortable7-6toaddressErrataAnalogIP_F035.BTS_VMON_F035_33.2. October2018 RemovedallreferencestotheSIL3certification.Sincethisproductisnotrecommendedfornew designs,TexasInstrumentshaschosennottorenewtheSIL3certification.Nochangeshave G beenmadetoform,fitorfunctionofthispart. Copyright©2010–2018,TexasInstrumentsIncorporated RevisionHistory 101 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

Not Recommended for New Designs TMS570LS20216,TMS570LS20206,TMS570LS10216 TMS570LS10206,TMS570LS10116,TMS570LS10106 SPNS141G–AUGUST2010–REVISEDOCTOBER2018 www.ti.com 9 Mechanical Packaging and Orderable Information The following table(s) show the thermal resistance for the PBGA-ZWT and PQFP-PGE mechanical packages. 9.1 Thermal Data 9.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack Table9-1.PGE(S-PQFP-G144)ThermalResistanceCharacteristics PARAMETER °C/W R 45 ΘJA R 5 ΘJC 9.1.2 ZWT (S-PBGA-N337) Plastic ball grid array Table9-2.ZWT(S-PBGA-N337)ThermalResistanceCharacteristics PARAMETER °C/W R 22 ΘJA R 3.3 ΘJC 9.2 Packaging Information The following packaging information and addendum reflect the most current data available for the designateddevice(s).Thedataissubjecttochangewithoutnoticeandwithoutrevisionofthisdocument. 102 MechanicalPackagingandOrderableInformation Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS570LS20216 TMS570LS20206 TMS570LS10216TMS570LS10206 TMS570LS10116 TMS570LS10106

PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) S5LS10106ASPGEQQ1 NRND LQFP PGE 144 60 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 10106ASPGEQQ1 & no Sb/Br) TMS570LS S5LS10106ASZWTQQ1 NRND NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 & no Sb/Br) LS10106ASZWTQQ1 S5LS10116ASPGEQQ1 NRND LQFP PGE 144 60 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 10116ASPGEQQ1 & no Sb/Br) TMS570LS S5LS10116ASZWTQQ1 NRND NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 & no Sb/Br) LS10116ASZWTQQ1 S5LS10206ASPGEQQ1 NRND LQFP PGE 144 60 TBD Call TI Call TI -40 to 125 S5LS10206ASZWTQQ1 NRND NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 & no Sb/Br) LS10206ASZWTQQ1 S5LS10216ASPGEQQ1 NRND LQFP PGE 144 60 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 10216ASPGEQQ1 & no Sb/Br) TMS570LS S5LS10216ASZWTQQ1 NRND NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 & no Sb/Br) LS10216ASZWTQQ1 S5LS20206ASPGEQQ1 NRND LQFP PGE 144 60 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 20206ASPGEQQ1 & no Sb/Br) TMS570LS S5LS20206ASPGEQQ1R NRND LQFP PGE 144 500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 20206ASPGEQQ1 & no Sb/Br) TMS570LS S5LS20206ASZWTQQ1 NRND NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 & no Sb/Br) LS20206ASZWTQQ1 S5LS20216ASPGEQQ1 NRND LQFP PGE 144 60 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 20216ASPGEQQ1 & no Sb/Br) TMS570LS S5LS20216ASZWTQQ1 NRND NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 & no Sb/Br) LS20216ASZWTQQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS570LS20206, TMS570LS20216 : •Enhanced Product: TMS570LS20206-EP, TMS570LS20216-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE OUTLINE ZWT0337A NFBGA - 1.4 mm max height SCALE 0.950 PLASTIC BALL GRID ARRAY B 16.1 A 15.9 BALL A1 CORNER 16.1 15.9 1.4 MAX C SEATING PLANE 0.45 0.35 TYP BALL TYP 0.12 C 14.4 TYP SYMM (0.8) TYP W V U (0.8) TYP T R P N M 14.4 L SYMM TYP K J H G 0.55 337X F 0.45 E 0.15 C A B D 0.05 C C B A 0.8 TYP 1 2 3 4 5 6 7 8 9 10 111213141516171819 0.8 TYP BALL A1 CORNER 4223381/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT ZWT0337A NFBGA - 1.4 mm max height PLASTIC BALL GRID ARRAY (0.8) TYP 337X ( 0.4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B (0.8) TYP C D E F G H J SYMM K L M N P R T U V W SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:7X ( 0.4) 0.05 MAX 0.05 MIN METAL UNDER SOLDER MASK METAL EXPOSED METAL ( 0.4) SOLDER MASK EXPOSED METAL SOLDER MASK OPENING OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223381/A 02/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com

EXAMPLE STENCIL DESIGN ZWT0337A NFBGA - 1.4 mm max height PLASTIC BALL GRID ARRAY ( 0.4) TYP (0.8) TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B (0.8) TYP C D E F G H J SYMM K L M N P R T U V W SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:7X 4223381/A 02/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,08 M 0,17 0,50 144 37 0,13 NOM 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 0,25 22,20 0,05 MIN 0°–7° SQ 21,80 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040147/C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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